diff --git a/include/nvethernet_type.h b/include/nvethernet_type.h
index 13c65a0..a9fee38 100644
--- a/include/nvethernet_type.h
+++ b/include/nvethernet_type.h
@@ -44,8 +44,6 @@ typedef char			my_int8_t;
 typedef unsigned char		my_uint8_t;
 /** intermediate type for unsigned long long */
 typedef unsigned long long 	my_ulint_64;
-/** intermediate type for long */
-typedef unsigned long		my_uint64_t;
 
 /* Actual type used in code */
 /** typedef equivalent to unsigned int */
@@ -60,8 +58,8 @@ typedef my_int8_t		nve8_t;
 typedef my_uint8_t		nveu8_t;
 /** typedef equivalent to unsigned long  long */
 typedef my_ulint_64		nveul64_t;
-/** typedef equivalent to long long */
-typedef my_uint64_t		nveu64_t;
+/** typedef equivalent to unsigned long long */
+typedef my_ulint_64		nveu64_t;
 /** @} */
 
 #endif /* INCLUDED_NVETHERNET_TYPE_H */
diff --git a/include/osi_common.h b/include/osi_common.h
index 7029234..b0c0c00 100644
--- a/include/osi_common.h
+++ b/include/osi_common.h
@@ -254,7 +254,7 @@
 #define MAC_CORE_VER_TYPE_EQOS_5_30	1U
 /** MAC version type for MGBE IP */
 #define MAC_CORE_VER_TYPE_MGBE		2U
-/** MAC version type for T26x EQOS version 5.40 */
+/** MAC version type for EQOS version 5.40 */
 #define MAC_CORE_VER_TYPE_EQOS_5_40	3U
 
 #define OSI_NULL                ((void *)0)
diff --git a/include/osi_core.h b/include/osi_core.h
index 8827f94..8d88dce 100644
--- a/include/osi_core.h
+++ b/include/osi_core.h
@@ -288,13 +288,12 @@ typedef my_lint_64		nvel64_t;
 #define OSI_XFI_MODE_5G		1U
 #define OSI_USXGMII_MODE_10G	2U
 #define OSI_USXGMII_MODE_5G	3U
-#define OSI_XAUI_MODE_25G	4U
 /**
  * @brief Ethernet UPHY GBE Modes
  */
 #define OSI_GBE_MODE_5G		0U
 #define OSI_GBE_MODE_10G	1U
-#define OSI_UPHY_GBE_MODE_25G	2U
+#define OSI_GBE_MODE_25G	2U
 #define OSI_GBE_MODE_1G		3U
 #define OSI_GBE_MODE_2_5G	4U
 
@@ -1702,6 +1701,12 @@ struct osi_core_priv_data {
 	 * NVETHERNETRM_PIF$OSI_EQOS_MAC_5_30
 	 * and NVETHERNETRM_PIF$OSI_MGBE_MAC_3_10*/
 	nveu32_t mac_ver;
+	/** MAC version
+	 * valid values are NVETHERNETRM_PIF$MAC_CORE_VER_TYPE_EQOS,
+	 * NVETHERNETRM_PIF$MAC_CORE_VER_TYPE_EQOS_5_30,
+	 * NVETHERNETRM_PIF$MAC_CORE_VER_TYPE_MGBE,
+	 * and NVETHERNETRM_PIF$MAC_CORE_VER_TYPE_EQOS_5_40*/
+	nveu32_t mac_ver_type;
 	/** HW supported feature list */
 	struct osi_hw_features *hw_feat;
 	/** MTU size
diff --git a/osi/core/common.h b/osi/core/common.h
index 5b90c88..d86ee4d 100644
--- a/osi/core/common.h
+++ b/osi/core/common.h
@@ -295,13 +295,9 @@ static inline nve32_t validate_mac_ver_update_chans(nveu32_t mac,
 		break;
 #endif /* !OSI_STRIPPED_LIB */
 	case OSI_EQOS_MAC_5_30:
-		*num_max_chans = OSI_EQOS_MAX_NUM_CHANS;
-		*l_mac_ver = MAC_CORE_VER_TYPE_EQOS_5_30;
-		ret = 1;
-		break;
 	case OSI_EQOS_MAC_5_40:
 		*num_max_chans = OSI_EQOS_MAX_NUM_CHANS;
-		*l_mac_ver = MAC_CORE_VER_TYPE_EQOS_5_40;
+		*l_mac_ver = MAC_CORE_VER_TYPE_EQOS_5_30;
 		ret = 1;
 		break;
 	case OSI_MGBE_MAC_3_10:
diff --git a/osi/core/core_common.c b/osi/core/core_common.c
index 602b015..3783f3d 100644
--- a/osi/core/core_common.c
+++ b/osi/core/core_common.c
@@ -218,10 +218,10 @@ nve32_t hw_set_speed(struct osi_core_priv_data *const osi_core, const nve32_t sp
 				MGBE_MAC_TMCR
 			};
 
-	if (((osi_core->mac == OSI_MAC_HW_EQOS) && (speed > OSI_SPEED_1000)) ||
+	if (((osi_core->mac == OSI_MAC_HW_EQOS) && (speed > OSI_SPEED_2500)) ||
 	    (((osi_core->mac == OSI_MAC_HW_MGBE) ||
 	    (osi_core->mac == OSI_MAC_HW_MGBE_T26X)) &&
-	    ((speed < OSI_SPEED_2500) || (speed > OSI_SPEED_25000)))) {
+	    ((speed < OSI_SPEED_2500) && (speed > OSI_SPEED_25000)))) {
 		OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
 			     "unsupported speed\n", (nveul64_t)speed);
 		ret = -1;
@@ -240,7 +240,12 @@ nve32_t hw_set_speed(struct osi_core_priv_data *const osi_core, const nve32_t sp
 		value |= EQOS_MCR_FES;
 		break;
 	case OSI_SPEED_2500:
-		value |= MGBE_MAC_TMCR_SS_2_5G;
+		if (osi_core->mac == OSI_MAC_HW_EQOS) {
+			value &= ~EQOS_MCR_PS;
+			value |= EQOS_MCR_FES;
+		} else {
+			value |= MGBE_MAC_TMCR_SS_2_5G;
+		}
 		break;
 #endif /* !OSI_STRIPPED_LIB */
 	case OSI_SPEED_1000:
@@ -290,12 +295,11 @@ nve32_t hw_set_speed(struct osi_core_priv_data *const osi_core, const nve32_t sp
 			/* Enable Link Status interrupt only after lane bring up success */
 			value |= MGBE_IMR_RGSMIIIE;
 			osi_writela(osi_core, value, (nveu8_t *)osi_core->base + MGBE_MAC_IER);
-		} else if (osi_core->mac_ver == MAC_CORE_VER_TYPE_EQOS_5_40) {
-			//TDB: eqos sgmii pcs changes
-//			ret = eqos_xpcs_init(osi_core);
-//			if (ret < 0) {
-//				goto fail;
-//			}
+		} else if (osi_core->mac_ver == OSI_EQOS_MAC_5_40) {
+			ret = eqos_xpcs_init(osi_core);
+			if (ret < 0) {
+				goto fail;
+			}
 		}
 	}
 fail:
diff --git a/osi/core/debug.c b/osi/core/debug.c
index dc762f1..0265d50 100644
--- a/osi/core/debug.c
+++ b/osi/core/debug.c
@@ -125,9 +125,11 @@ void core_reg_dump(struct osi_core_priv_data *osi_core)
 		max_addr = 0x12E4;
 		break;
 	case OSI_EQOS_MAC_5_30:
+	case OSI_EQOS_MAC_5_40:
 		max_addr = 0x14EC;
 		break;
 	case OSI_MGBE_MAC_3_10:
+	case OSI_MGBE_MAC_4_20:
 		max_addr = 0x35FC;
 		break;
 	default:
diff --git a/osi/core/eqos_core.c b/osi/core/eqos_core.c
index 2042250..6aad4be 100644
--- a/osi/core/eqos_core.c
+++ b/osi/core/eqos_core.c
@@ -163,6 +163,10 @@ static nve32_t eqos_pad_calibrate(struct osi_core_priv_data *const osi_core)
 	nve32_t cond = COND_NOT_MET, ret = 0;
 	nveu32_t value;
 
+	if (osi_core->mac_ver == OSI_EQOS_MAC_5_40) {
+		return 0;
+	}
+
 	(void)__sync_val_compare_and_swap(&osi_core->padctrl.is_pad_cal_in_progress,
 				    OSI_DISABLE, OSI_ENABLE);
 	ret = eqos_pre_pad_calibrate(osi_core);
@@ -1180,14 +1184,16 @@ static nve32_t eqos_core_init(struct osi_core_priv_data *const osi_core)
 			goto fail;
 		}
 	}
-	/* PAD calibration */
-	ret = eqos_pad_calibrate(osi_core);
-	if (ret < 0) {
-		OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
-			     "eqos pad calibration failed\n", 0ULL);
-		goto fail;
-	}
 
+	if (osi_core->mac_ver != OSI_EQOS_MAC_5_40) {
+		/* PAD calibration */
+		ret = eqos_pad_calibrate(osi_core);
+		if (ret < 0) {
+			OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
+				     "eqos pad calibration failed\n", 0ULL);
+			goto fail;
+		}
+	}
 	/* reset mmc counters */
 	osi_writela(osi_core, EQOS_MMC_CNTRL_CNTRST,
 		    (nveu8_t *)osi_core->base + EQOS_MMC_CNTRL);
diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c
index db24b9e..ae55a6f 100644
--- a/osi/core/mgbe_core.c
+++ b/osi/core/mgbe_core.c
@@ -4253,7 +4253,7 @@ static void mgbe_configure_eee(struct osi_core_priv_data *const osi_core,
 	nveu32_t tic_counter = 0;
 	void *addr =  osi_core->base;
 
-	if (osi_core->uphy_gbe_mode == OSI_UPHY_GBE_MODE_25G) {
+	if (osi_core->uphy_gbe_mode == OSI_GBE_MODE_25G) {
 		if (xlgpcs_eee(osi_core, tx_lpi_enabled) != 0) {
 				OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
 					     "xlgpcs_eee call failed\n", 0ULL);
diff --git a/osi/core/osi_hal.c b/osi/core/osi_hal.c
index d9a0d15..9fbacb2 100644
--- a/osi/core/osi_hal.c
+++ b/osi/core/osi_hal.c
@@ -469,7 +469,7 @@ static nve32_t osi_ptp_configuration(struct osi_core_priv_data *const osi_core,
 		 * so addend = (2^32 * 1000)/(ptp_ref_clk_rate in MHZ * SSINC);
 		 */
 		ssinc = OSI_PTP_SSINC_4;
-		if (osi_core->mac_ver == OSI_EQOS_MAC_5_30) {
+		if (osi_core->mac_ver >= OSI_EQOS_MAC_5_30) {
 			ssinc = OSI_PTP_SSINC_6;
 		}
 
@@ -611,8 +611,6 @@ static nve32_t osi_hal_hw_core_init(struct osi_core_priv_data *const osi_core)
 	/* By default enable rxcsum - since passing enable explicitely this API will never fail */
 	(void)hw_config_rxcsum_offload(osi_core, OSI_ENABLE);
 
-	/* Set default PTP settings */
-	osi_core->ptp_config.ptp_rx_queue = 3U;
 	osi_core->ptp_config.ptp_ref_clk_rate = ptp_ref_clk_rate[l_core->l_mac_ver];
 	osi_core->ptp_config.ptp_filter = OSI_MAC_TCR_TSENA | OSI_MAC_TCR_TSCFUPDT |
 					  OSI_MAC_TCR_TSCTRLSSR | OSI_MAC_TCR_TSVER2ENA |
diff --git a/osi/core/xpcs.c b/osi/core/xpcs.c
index 28274ad..92bdd39 100644
--- a/osi/core/xpcs.c
+++ b/osi/core/xpcs.c
@@ -760,11 +760,9 @@ step10:
 	}
 
 	if (xpcs_check_pcs_lock_status(osi_core) < 0) {
-		if (l_core->lane_status == OSI_ENABLE) {
 			OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
 				     "Failed to get PCS block lock\n", 0ULL);
-			l_core->lane_status = OSI_DISABLE;
-		}
+		l_core->lane_status = OSI_DISABLE;
 		ret = -1;
 		goto fail;
 	} else {
@@ -1058,7 +1056,7 @@ nve32_t xlgpcs_init(struct osi_core_priv_data *osi_core)
 	} else {
 		/* Select XLGPCS in wrapper register */
 		if ((osi_core->mac == OSI_MAC_HW_MGBE_T26X) &&
-		    (osi_core->uphy_gbe_mode == OSI_UPHY_GBE_MODE_25G)) {
+		    (osi_core->uphy_gbe_mode == OSI_GBE_MODE_25G)) {
 			value = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
 					   T26X_XPCS_WRAP_CONFIG_0);
 			value |= OSI_BIT(0);
diff --git a/osi/core/xpcs.h b/osi/core/xpcs.h
index 71dfd70..ccec365 100644
--- a/osi/core/xpcs.h
+++ b/osi/core/xpcs.h
@@ -47,9 +47,9 @@
 #define XPCS_WRAP_UPHY_STATUS			0x8044
 #define XPCS_WRAP_UPHY_RX_CONTROL_0_0		0x801C
 #define XPCS_WRAP_INTERRUPT_STATUS		0x8050
-#define T26X_XPCS_WRAP_UPHY_HW_INIT_CTRL	0x8034
-#define T26X_XPCS_WRAP_UPHY_STATUS		0x8074
-#define T26X_XPCS_WRAP_INTERRUPT_STATUS		0x8080
+#define T26X_XPCS_WRAP_UPHY_HW_INIT_CTRL	0x8038
+#define T26X_XPCS_WRAP_UPHY_STATUS		0x8080
+#define T26X_XPCS_WRAP_INTERRUPT_STATUS		0x808C
 #define T26X_XPCS_WRAP_CONFIG_0			0x8094
 
 /** @} */
diff --git a/osi/dma/dma_local.h b/osi/dma/dma_local.h
index 6f80648..3a61b83 100644
--- a/osi/dma/dma_local.h
+++ b/osi/dma/dma_local.h
@@ -28,16 +28,6 @@
 #include "eqos_dma.h"
 #include "mgbe_dma.h"
 
-/**
- * @brief Maximum number of supported MAC IP types (EQOS and MGBE)
- */
-#define MAX_MAC_IP_TYPES       2U
-/** MAC version type for EQOS version previous to 5.30 */
-#define MAC_CORE_VER_TYPE_EQOS		0U
-/** MAC version type for EQOS version 5.30 */
-#define MAC_CORE_VER_TYPE_EQOS_5_30	1U
-/** MAC version type for MGBE IP */
-#define MAC_CORE_VER_TYPE_MGBE		2U
 /**
  * @brief validate_dma_mac_ver_update_chans - Validates mac version and update chan
  *
@@ -78,6 +68,7 @@ static inline nve32_t validate_dma_mac_ver_update_chans(nveu32_t mac,
 		break;
 #endif /* !OSI_STRIPPED_LIB */
 	case OSI_EQOS_MAC_5_30:
+	case OSI_EQOS_MAC_5_40:
 		*num_max_chans = OSI_EQOS_MAX_NUM_CHANS;
 		*l_mac_ver = MAC_CORE_VER_TYPE_EQOS_5_30;
 		ret = 1;
diff --git a/osi/dma/osi_dma.c b/osi/dma/osi_dma.c
index fe0ec6d..dd1a543 100644
--- a/osi/dma/osi_dma.c
+++ b/osi/dma/osi_dma.c
@@ -411,13 +411,6 @@ static nve32_t validate_dma_ops_params(struct osi_dma_priv_data *osi_dma)
 		goto fail;
 	}
 
-	if (osi_dma->mac > OSI_MAC_HW_MGBE) {
-		OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
-			    "DMA: Invalid MAC HW type\n", 0ULL);
-		ret = -1;
-		goto fail;
-	}
-
 	ret = validate_ring_sz(osi_dma);
 fail:
 	return ret;
diff --git a/osi/dma/osi_dma_txrx.c b/osi/dma/osi_dma_txrx.c
index d5bb480..bcf6486 100644
--- a/osi/dma/osi_dma_txrx.c
+++ b/osi/dma/osi_dma_txrx.c
@@ -111,7 +111,9 @@ static inline void process_rx_desc(struct osi_dma_priv_data *osi_dma,
 				   struct osi_rx_pkt_cx *rx_pkt_cx,
 				   nveu32_t chan, const nveu32_t rx_ring_mask)
 {
-	const nveu32_t es_bits_mask[2U] = { RDES3_ES_BITS, RDES3_ES_MGBE };
+	const nveu32_t es_bits_mask[OSI_MAX_MAC_IP_TYPES] = {
+			RDES3_ES_BITS, RDES3_ES_MGBE, RDES3_ES_MGBE
+		};
 	struct osi_rx_desc *context_desc = OSI_NULL;
 	struct osi_rx_swcx *ptp_rx_swcx = OSI_NULL;
 	nveu32_t ip_type = osi_dma->mac;