diff --git a/include/osi_core.h b/include/osi_core.h
index ff8913a..bb9c757 100644
--- a/include/osi_core.h
+++ b/include/osi_core.h
@@ -659,6 +659,8 @@ typedef my_lint_64		nvel64_t;
 #define MAC2MAC_ERR_IDX		8U
 /** @brief Link training monitor error Index */
 #define PCS_LNK_ERR_IDX		9U
+/** @brief mac common interrupt status monitor error Index */
+#define MAC_CMN_INTR_ERR_IDX		10U
 /** @brief MACSEC RX CRC error Index */
 #define MACSEC_RX_CRC_ERR_IDX	0U
 /** @brief MACSEC TX CRC error Index */
@@ -692,7 +694,7 @@ typedef my_lint_64		nvel64_t;
  * @brief Maximum number of different mac error code
  * HSI_SW_ERR_CODE + Two (Corrected and Uncorrected error code)
  */
-#define OSI_HSI_MAX_MAC_ERROR_CODE		10U
+#define OSI_HSI_MAX_MAC_ERROR_CODE		11U
 
 /**
  * @brief Maximum number of different macsec error code
@@ -743,6 +745,8 @@ typedef my_lint_64		nvel64_t;
 #define OSI_M2M_CONFIG_PTP_ERR		0x12U
 /** @brief pcs link status error code */
 #define OSI_PCS_LNK_ERR			0x13U
+/** @brief MAC common interrupt status error code */
+#define OSI_MAC_CMN_INTR_ERR		0x14U
 
 /** @brief EQOS uncorrectable attribute */
 #define OSI_EQOS_UNCORRECTABLE_ATTR	0x109
@@ -1881,6 +1885,8 @@ struct osi_core_priv_data {
 	/** skip auto neg for usxgmii mode.
 	 * 0(enable AN) and 1(disable AN) are the valid values */
 	nveu32_t skip_usxgmii_an;
+	/** MAC common interrupt received */
+	nveu32_t mac_common_intr_rcvd;
 };
 
 /**
diff --git a/osi/core/core_common.c b/osi/core/core_common.c
index e094872..f4adb0a 100644
--- a/osi/core/core_common.c
+++ b/osi/core/core_common.c
@@ -1943,6 +1943,11 @@ nve32_t hsi_common_error_inject(struct osi_core_priv_data *osi_core,
 		osi_core->hsi.report_err = OSI_ENABLE;
 		osi_core->hsi.report_count_err[XPCS_WRITE_FAIL_IDX] = OSI_ENABLE;
 		break;
+	case OSI_MAC_CMN_INTR_ERR:
+		osi_core->hsi.err_code[MAC_CMN_INTR_ERR_IDX] = OSI_MAC_CMN_INTR_ERR;
+		osi_core->hsi.report_err = OSI_ENABLE;
+		osi_core->hsi.report_count_err[MAC_CMN_INTR_ERR_IDX] = OSI_ENABLE;
+		break;
 	case OSI_M2M_TSC_READ_ERR:
 	case OSI_M2M_TIME_CAL_ERR:
 	case OSI_M2M_ADJ_FREQ_ERR:
diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c
index 5c09684..657a59a 100644
--- a/osi/core/mgbe_core.c
+++ b/osi/core/mgbe_core.c
@@ -2193,21 +2193,89 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
 		/* T23X-MGBE_HSIv2-11:Initialization of Watchdog Timer */
 		value = (0xCCU << XPCS_SFTY_1US_MULT_SHIFT) & XPCS_SFTY_1US_MULT_MASK;
 		value |= ((nveu32_t)0x01U << XPCS_FSM_TO_SEL_SHIFT) & XPCS_FSM_TO_SEL_MASK;
+		value |= XPCS_VR_XS_PCS_SFTY_TMR_CTRL_IFT_SEL;
 		ret = xpcs_write_safety(osi_core, XPCS_VR_XS_PCS_SFTY_TMR_CTRL, value);
 		if (ret != 0) {
 			goto fail;
 		}
-		/* T23X-MGBE_HSIv2-1 Configure ECC */
+		/* Below setting is applicable only for 25G in XLGPCS */
+		if (osi_core->uphy_gbe_mode == OSI_GBE_MODE_25G) {
+			/* T264-MGBE_HSIv2-59	Initialization of Transaction Timeout in XLGPCS */
+			/* T264-MGBE_HSIv2-60	Initialization of Watchdog Timer for XLGPCS FSM States */
+			value = (0xCBU << XPCS_SFTY_1US_MULT_SHIFT) & XPCS_SFTY_1US_MULT_MASK;
+			value |= ((nveu32_t)0x01U << XPCS_FSM_TO_SEL_SHIFT) & XPCS_FSM_TO_SEL_MASK;
+			/* IFT_SEL field same as */
+			value |= XPCS_VR_XS_PCS_SFTY_TMR_CTRL_IFT_SEL;
+			ret = xpcs_write_safety(osi_core, XLGPCS_VR_PCS_SFTY_TMR_CTRL, value);
+			if (ret != 0) {
+				goto fail;
+			}
+		}
+
+		/* T23X-MGBE_HSIv2-38: Initialization of Register Parity for control registers */
 		value = osi_readla(osi_core,
-				   (nveu8_t *)osi_core->base + MGBE_MTL_ECC_CONTROL);
-		value &= ~MGBE_MTL_ECC_MTXED;
-		value &= ~MGBE_MTL_ECC_MRXED;
-		value &= ~MGBE_MTL_ECC_MGCLED;
-		value &= ~MGBE_MTL_ECC_MRXPED;
-		value &= ~MGBE_MTL_ECC_TSOED;
-		value &= ~MGBE_MTL_ECC_DESCED;
+				   (nveu8_t *)osi_core->base + MGBE_MAC_SCSR_CONTROL);
+		value |= MGBE_CPEN;
 		osi_writela(osi_core, value,
-			    (nveu8_t *)osi_core->base + MGBE_MTL_ECC_CONTROL);
+			    (nveu8_t *)osi_core->base + MGBE_MAC_SCSR_CONTROL);
+
+		/* For T26x CE/UCE are not handled by SW driver,since they are directly
+		 * reported to FSI through HSM , so not enabling it
+		 */
+		if (osi_core->mac != OSI_MAC_HW_MGBE_T26X) {
+			/* T23X-MGBE_HSIv2-1 Configure ECC */
+			value = osi_readla(osi_core,
+					   (nveu8_t *)osi_core->base + MGBE_MTL_ECC_CONTROL);
+			value &= ~MGBE_MTL_ECC_MTXED;
+			value &= ~MGBE_MTL_ECC_MRXED;
+			value &= ~MGBE_MTL_ECC_MGCLED;
+			value &= ~MGBE_MTL_ECC_MRXPED;
+			value &= ~MGBE_MTL_ECC_TSOED;
+			value &= ~MGBE_MTL_ECC_DESCED;
+			osi_writela(osi_core, value,
+				    (nveu8_t *)osi_core->base + MGBE_MTL_ECC_CONTROL);
+			/* Enable Interrupt */
+			/*  T23X-MGBE_HSIv2-1: Enabling of Memory ECC */
+			value = osi_readla(osi_core,
+					   (nveu8_t *)osi_core->base + MGBE_MTL_ECC_INTERRUPT_ENABLE);
+			value |= MGBE_MTL_TXCEIE;
+			value |= MGBE_MTL_RXCEIE;
+			value |= MGBE_MTL_GCEIE;
+			value |= MGBE_MTL_RPCEIE;
+			osi_writela(osi_core, value,
+				    (nveu8_t *)osi_core->base + MGBE_MTL_ECC_INTERRUPT_ENABLE);
+
+			value = osi_readla(osi_core,
+					   (nveu8_t *)osi_core->base + MGBE_DMA_ECC_INTERRUPT_ENABLE);
+			value |= MGBE_DMA_TCEIE;
+			value |= MGBE_DMA_DCEIE;
+			osi_writela(osi_core, value,
+				    (nveu8_t *)osi_core->base + MGBE_DMA_ECC_INTERRUPT_ENABLE);
+
+			value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
+					   intr_en[osi_core->mac]);
+			value |= MGBE_REGISTER_PARITY_ERR;
+			value |= MGBE_CORE_CORRECTABLE_ERR;
+			value |= MGBE_CORE_UNCORRECTABLE_ERR;
+			osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
+				    intr_en[osi_core->mac]);
+
+			value = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
+					xpcs_intr_ctrl_reg[osi_core->mac]);
+			value |= XPCS_CORE_CORRECTABLE_ERR;
+			value |= XPCS_CORE_UNCORRECTABLE_ERR;
+			value |= XPCS_REGISTER_PARITY_ERR;
+			osi_writela(osi_core, value, (nveu8_t *)osi_core->xpcs_base +
+				    xpcs_intr_ctrl_reg[osi_core->mac]);
+
+			/* T23X-MGBE_HSIv2-2: Enabling of Bus Parity */
+			value = osi_readla(osi_core,
+					   (nveu8_t *)osi_core->base + MGBE_MTL_DPP_CONTROL);
+			value &= ~MGBE_DDPP;
+			osi_writela(osi_core, value,
+				    (nveu8_t *)osi_core->base + MGBE_MTL_DPP_CONTROL);
+
+		}
 
 		/* T23X-MGBE_HSIv2-5: Enabling and Initialization of Transaction Timeout  */
 		value = (0x198U << MGBE_TMR_SHIFT) & MGBE_TMR_MASK;
@@ -2241,53 +2309,6 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
 		osi_writela(osi_core, value,
 			    (nveu8_t *)osi_core->base + MGBE_MMC_RX_INTR_EN);
 
-		/* T23X-MGBE_HSIv2-2: Enabling of Bus Parity */
-		value = osi_readla(osi_core,
-				   (nveu8_t *)osi_core->base + MGBE_MTL_DPP_CONTROL);
-		value &= ~MGBE_DDPP;
-		osi_writela(osi_core, value,
-			    (nveu8_t *)osi_core->base + MGBE_MTL_DPP_CONTROL);
-
-		/* T23X-MGBE_HSIv2-38: Initialization of Register Parity for control registers */
-		value = osi_readla(osi_core,
-				   (nveu8_t *)osi_core->base + MGBE_MAC_SCSR_CONTROL);
-		value |= MGBE_CPEN;
-		osi_writela(osi_core, value,
-			    (nveu8_t *)osi_core->base + MGBE_MAC_SCSR_CONTROL);
-
-		/* Enable Interrupt */
-		/*  T23X-MGBE_HSIv2-1: Enabling of Memory ECC */
-		value = osi_readla(osi_core,
-				   (nveu8_t *)osi_core->base + MGBE_MTL_ECC_INTERRUPT_ENABLE);
-		value |= MGBE_MTL_TXCEIE;
-		value |= MGBE_MTL_RXCEIE;
-		value |= MGBE_MTL_GCEIE;
-		value |= MGBE_MTL_RPCEIE;
-		osi_writela(osi_core, value,
-			    (nveu8_t *)osi_core->base + MGBE_MTL_ECC_INTERRUPT_ENABLE);
-
-		value = osi_readla(osi_core,
-				   (nveu8_t *)osi_core->base + MGBE_DMA_ECC_INTERRUPT_ENABLE);
-		value |= MGBE_DMA_TCEIE;
-		value |= MGBE_DMA_DCEIE;
-		osi_writela(osi_core, value,
-			    (nveu8_t *)osi_core->base + MGBE_DMA_ECC_INTERRUPT_ENABLE);
-
-		value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
-				   intr_en[osi_core->mac]);
-		value |= MGBE_REGISTER_PARITY_ERR;
-		value |= MGBE_CORE_CORRECTABLE_ERR;
-		value |= MGBE_CORE_UNCORRECTABLE_ERR;
-		osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
-			    intr_en[osi_core->mac]);
-
-		value = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
-				   xpcs_intr_ctrl_reg[osi_core->mac]);
-		value |= XPCS_CORE_CORRECTABLE_ERR;
-		value |= XPCS_CORE_UNCORRECTABLE_ERR;
-		value |= XPCS_REGISTER_PARITY_ERR;
-		osi_writela(osi_core, value, (nveu8_t *)osi_core->xpcs_base +
-			    xpcs_intr_ctrl_reg[osi_core->mac]);
 	} else {
 		osi_core->hsi.enabled = OSI_DISABLE;
 
@@ -2296,36 +2317,49 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
 		if (ret != 0) {
 			goto fail;
 		}
-		/* T23X-MGBE_HSIv2-1 Disable ECC */
-		value = osi_readla(osi_core,
-				   (nveu8_t *)osi_core->base + MGBE_MTL_ECC_CONTROL);
-		value |= MGBE_MTL_ECC_MTXED;
-		value |= MGBE_MTL_ECC_MRXED;
-		value |= MGBE_MTL_ECC_MGCLED;
-		value |= MGBE_MTL_ECC_MRXPED;
-		value |= MGBE_MTL_ECC_TSOED;
-		value |= MGBE_MTL_ECC_DESCED;
-		osi_writela(osi_core, value,
-			    (nveu8_t *)osi_core->base + MGBE_MTL_ECC_CONTROL);
 
-		/* T23X-MGBE_HSIv2-5: Enabling and Initialization of Transaction Timeout  */
-		osi_writela(osi_core, 0,
-			    (nveu8_t *)osi_core->base + MGBE_DWCXG_CORE_MAC_FSM_ACT_TIMER);
+		if (osi_core->mac != OSI_MAC_HW_MGBE_T26X) {
+			/* T23X-MGBE_HSIv2-1 Disable ECC */
+			value = osi_readla(osi_core,
+					   (nveu8_t *)osi_core->base + MGBE_MTL_ECC_CONTROL);
+			value |= MGBE_MTL_ECC_MTXED;
+			value |= MGBE_MTL_ECC_MRXED;
+			value |= MGBE_MTL_ECC_MGCLED;
+			value |= MGBE_MTL_ECC_MRXPED;
+			value |= MGBE_MTL_ECC_TSOED;
+			value |= MGBE_MTL_ECC_DESCED;
+			osi_writela(osi_core, value,
+				    (nveu8_t *)osi_core->base + MGBE_MTL_ECC_CONTROL);
+			/* Disable Interrupts */
+			osi_writela(osi_core, 0,
+				    (nveu8_t *)osi_core->base + MGBE_MTL_ECC_INTERRUPT_ENABLE);
 
-		/* T23X-MGBE_HSIv2-4: Enabling of Consistency Monitor for XGMAC FSM State */
-		osi_writela(osi_core, 0,
-			    (nveu8_t *)osi_core->base + MGBE_MAC_FSM_CONTROL);
+			osi_writela(osi_core, 0,
+				    (nveu8_t *)osi_core->base + MGBE_DMA_ECC_INTERRUPT_ENABLE);
 
-		/* T23X-MGBE_HSIv2-20: Enabling of error reporting for Inbound Bus CRC errors */
-		osi_writela(osi_core, 0, (nveu8_t *)osi_core->base + MGBE_MMC_RX_INTR_EN);
+			value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
+					   intr_en[osi_core->mac]);
+			value &= ~MGBE_REGISTER_PARITY_ERR;
+			value &= ~MGBE_CORE_CORRECTABLE_ERR;
+			value &= ~MGBE_CORE_UNCORRECTABLE_ERR;
+			osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
+				    intr_en[osi_core->mac]);
 
-		/* T23X-MGBE_HSIv2-2: Disable of Bus Parity */
-		value = osi_readla(osi_core,
-				   (nveu8_t *)osi_core->base + MGBE_MTL_DPP_CONTROL);
-		value |=  MGBE_DDPP;
-		osi_writela(osi_core, value,
-			    (nveu8_t *)osi_core->base + MGBE_MTL_DPP_CONTROL);
+			value = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
+					   xpcs_intr_ctrl_reg[osi_core->mac]);
+			value &= ~XPCS_CORE_CORRECTABLE_ERR;
+			value &= ~XPCS_CORE_UNCORRECTABLE_ERR;
+			value &= ~XPCS_REGISTER_PARITY_ERR;
+			osi_writela(osi_core, value, (nveu8_t *)osi_core->xpcs_base +
+				    xpcs_intr_ctrl_reg[osi_core->mac]);
 
+			/* T23X-MGBE_HSIv2-2: Disable of Bus Parity */
+			value = osi_readla(osi_core,
+					   (nveu8_t *)osi_core->base + MGBE_MTL_DPP_CONTROL);
+			value |=  MGBE_DDPP;
+			osi_writela(osi_core, value,
+					(nveu8_t *)osi_core->base + MGBE_MTL_DPP_CONTROL);
+		}
 		/* T23X-MGBE_HSIv2-38: Disable Register Parity for control registers */
 		value = osi_readla(osi_core,
 				   (nveu8_t *)osi_core->base + MGBE_MAC_SCSR_CONTROL);
@@ -2333,28 +2367,26 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
 		osi_writela(osi_core, value,
 			    (nveu8_t *)osi_core->base + MGBE_MAC_SCSR_CONTROL);
 
-		/* Disable Interrupts */
-		osi_writela(osi_core, 0,
-			    (nveu8_t *)osi_core->base + MGBE_MTL_ECC_INTERRUPT_ENABLE);
+		/* T23X-MGBE_HSIv2-5: Disabling and DeInitialization of Transaction Timeout  */
+		value = osi_readla(osi_core,
+				  (nveu8_t *)osi_core->base + MGBE_DWCXG_CORE_MAC_FSM_ACT_TIMER);
+		value &= ~(MGBE_TMR_MASK | MGBE_CTMR_MASK | MGBE_LTMRMD_MASK | MGBE_NTMRMD_MASK);
+		osi_writela(osi_core, value,
+			    (nveu8_t *)osi_core->base + MGBE_DWCXG_CORE_MAC_FSM_ACT_TIMER);
 
-		osi_writela(osi_core, 0,
-			    (nveu8_t *)osi_core->base + MGBE_DMA_ECC_INTERRUPT_ENABLE);
+		value = osi_readla(osi_core,
+				  (nveu8_t *)osi_core->base + MGBE_MAC_FSM_CONTROL);
+		value &= ~MGBE_PRTYEN;
+		value &= ~MGBE_TMOUTEN;
+		/* T23X-MGBE_HSIv2-4: Disabling of Consistency Monitor for XGMAC FSM State */
+		osi_writela(osi_core, value,
+			    (nveu8_t *)osi_core->base + MGBE_MAC_FSM_CONTROL);
 
-		value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
-				   intr_en[osi_core->mac]);
-		value &= ~MGBE_REGISTER_PARITY_ERR;
-		value &= ~MGBE_CORE_CORRECTABLE_ERR;
-		value &= ~MGBE_CORE_UNCORRECTABLE_ERR;
-		osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
-			    intr_en[osi_core->mac]);
-
-		value = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
-				   xpcs_intr_ctrl_reg[osi_core->mac]);
-		value &= ~XPCS_CORE_CORRECTABLE_ERR;
-		value &= ~XPCS_CORE_UNCORRECTABLE_ERR;
-		value &= ~XPCS_REGISTER_PARITY_ERR;
-		osi_writela(osi_core, value, (nveu8_t *)osi_core->xpcs_base +
-			    xpcs_intr_ctrl_reg[osi_core->mac]);
+		value = osi_readla(osi_core,
+				   (nveu8_t *)osi_core->base + MGBE_MMC_RX_INTR_EN);
+		value &= ~MGBE_RXCRCERPIE;
+		/* T23X-MGBE_HSIv2-20: Disabling of error reporting for Inbound Bus CRC errors */
+		osi_writela(osi_core, value, (nveu8_t *)osi_core->base + MGBE_MMC_RX_INTR_EN);
 	}
 fail:
 	return ret;
@@ -3058,6 +3090,9 @@ static void mgbe_handle_mac_fpe_intrs(struct osi_core_priv_data *osi_core)
 	/* interrupt bit clear on read as CSR_SW is reset */
 	val = osi_readla(osi_core, (nveu8_t *)
 			 osi_core->base + MGBE_MAC_FPE_CTS);
+	if (val != 0U ) {
+		osi_core->mac_common_intr_rcvd = OSI_ENABLE;
+	}
 
 	if ((val & MGBE_MAC_FPE_CTS_RVER) == MGBE_MAC_FPE_CTS_RVER) {
 		val &= ~MGBE_MAC_FPE_CTS_RVER;
@@ -3128,6 +3163,9 @@ static void mgbe_handle_link_change_and_fpe_intrs(struct osi_core_priv_data *osi
 	nveu32_t link_ok = 0;
 #endif /* HSI_SUPPORT */
 
+	/* T264-MGBE_HSIv2-72, T264-MGBE_HSIv2-78 we wil be relying on MAC interrupt
+	 * for any fault occurs during link training */
+
 	/* Check for Link status change interrupt */
 	if ((mac_isr & MGBE_MAC_ISR_LSI) == OSI_ENABLE) {
 		/* For Local fault need to stop network data and restart the LANE bringup */
@@ -3193,6 +3231,9 @@ static void mgbe_handle_mac_intrs(struct osi_core_priv_data *osi_core)
 
 	mac_isr = osi_readla(osi_core, base + MGBE_MAC_ISR);
 
+	if (mac_isr != 0U ) {
+		osi_core->mac_common_intr_rcvd = OSI_ENABLE;
+	}
 	/* handle mgbe link change and fpe interrupts */
 	mgbe_handle_link_change_and_fpe_intrs(osi_core, mac_isr);
 
@@ -3752,6 +3793,9 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core,
 			/* check if Q has underflow error */
 			qstatus = osi_readl((nveu8_t *)osi_core->base +
 					    MGBE_MTL_QINT_STATUS(qinx));
+			if (qstatus != 0U ) {
+				osi_core->mac_common_intr_rcvd = OSI_ENABLE;
+			}
 			/* Transmit Queue Underflow Interrupt Status */
 			if ((qstatus & MGBE_MTL_QINT_TXUNIFS) == MGBE_MTL_QINT_TXUNIFS) {
 #ifndef OSI_STRIPPED_LIB
@@ -4068,6 +4112,45 @@ static void mgbe_handle_hsi_intr(struct osi_core_priv_data *osi_core)
 }
 #endif
 
+/**
+ * @brief mgbe_check_intr_status - Check interrupt status.
+ *
+ * Algorithm: Check for the MDIO, LPI, PCTH, PCTW status registers
+ *
+ * @param[in] osi_core: OSI core private data structure.
+ *
+ * @note MAC should be init and started. see osi_start_mac()
+ */
+static void mgbe_check_intr_status(struct osi_core_priv_data *const osi_core)
+{
+	nveu32_t value;
+
+#ifndef OSI_STRIPPED_LIB
+	/* Read for MAC_LPI_Control_Status */
+	value = osi_readla(osi_core, (nveu8_t *)osi_core->base + MGBE_MAC_LPI_CSR);
+	if ((value & MGBE_MAC_LPI_STATUS_MASK) != 0U) {
+		osi_core->mac_common_intr_rcvd = OSI_ENABLE;
+	}
+#endif /* !OSI_STRIPPED_LIB */
+
+	/* Read for MDIO_Interrupt_Status */
+	value = osi_readla(osi_core, (nveu8_t *)osi_core->base + MGBE_MAC_MDIO_INTR_STS);
+	if (value != 0U) {
+		osi_core->mac_common_intr_rcvd = OSI_ENABLE;
+	}
+	/* Read for MAC_PCTH_Intr_Status */
+	value = osi_readla(osi_core, (nveu8_t *)osi_core->base + MGBE_MAC_PCTH_INTR_STS);
+	if (value != 0U) {
+		osi_core->mac_common_intr_rcvd = OSI_ENABLE;
+	}
+	/* Read for MAC_PCTW_Intr_Status */
+	value = osi_readla(osi_core, (nveu8_t *)osi_core->base + MGBE_MAC_PCTW_INTR_STS);
+	if (value != 0U) {
+		osi_core->mac_common_intr_rcvd = OSI_ENABLE;
+	}
+
+}
+
 /**
  * @brief mgbe_handle_common_intr - Handles common interrupt.
  *
@@ -4102,7 +4185,7 @@ static void mgbe_handle_common_intr(struct osi_core_priv_data *const osi_core)
 	nveu32_t val = 0;
 
 #ifdef HSI_SUPPORT
-	if (osi_core->hsi.enabled == OSI_ENABLE) {
+	if ((osi_core->hsi.enabled == OSI_ENABLE) && (osi_core->mac != OSI_MAC_HW_MGBE_T26X)) {
 		mgbe_handle_hsi_intr(osi_core);
 	}
 #endif
@@ -4167,6 +4250,9 @@ static void mgbe_handle_common_intr(struct osi_core_priv_data *const osi_core)
 		mgbe_handle_mtl_intrs(osi_core, mtl_isr);
 	}
 
+	/* Check MDIO, LPI, PCTH, PCTW interrupt status */
+	mgbe_check_intr_status(osi_core);
+
 	/* Clear common interrupt status in wrapper register */
 	osi_writela(osi_core, MGBE_MAC_SBD_INTR,
 		   (nveu8_t *)base + intr_status[osi_core->mac]);
@@ -4183,6 +4269,17 @@ static void mgbe_handle_common_intr(struct osi_core_priv_data *const osi_core)
 		MGBE_MTL_RXP_INTR_CS_FOOVIS |
 		MGBE_MTL_RXP_INTR_CS_PDRFIS);
 	osi_writela(osi_core, val, (nveu8_t *)base + MGBE_MTL_RXP_INTR_CS);
+#ifdef HSI_SUPPORT
+	/* if interrupt is not from any of the below conditions then notify error */
+	if ((osi_core->hsi.enabled == OSI_ENABLE) &&
+	    !((dma_sr != 0U) || (dma_isr_ch0_15 != 0U) || (dma_isr_ch16_47 != 0U)
+		|| (mtl_isr != 0U) || (val != 0U) || (osi_core->mac_common_intr_rcvd != 0U))) {
+		osi_core->hsi.err_code[MAC_CMN_INTR_ERR_IDX] = OSI_MAC_CMN_INTR_ERR;
+		osi_core->hsi.report_err = OSI_ENABLE;
+		osi_core->hsi.report_count_err[MAC_CMN_INTR_ERR_IDX] = OSI_ENABLE;
+		osi_core->mac_common_intr_rcvd = OSI_DISABLE;
+	}
+#endif
 
 done:
 	return;
diff --git a/osi/core/mgbe_core.h b/osi/core/mgbe_core.h
index 2307a49..7057f76 100644
--- a/osi/core/mgbe_core.h
+++ b/osi/core/mgbe_core.h
@@ -159,6 +159,7 @@
 #define MGBE_MAC_LPI_CSR_LPITXA			OSI_BIT(19)
 #define MGBE_MAC_LPI_CSR_PLS			OSI_BIT(17)
 #define MGBE_MAC_LPI_CSR_LPIEN			OSI_BIT(16)
+#define MGBE_MAC_LPI_STATUS_MASK		0xF0FU
 #define MGBE_MAC_PFR_VTFE_SHIFT			16
 #define MGBE_MAC_PIDR_PID_MASK			0XFFFFU
 
@@ -382,10 +383,13 @@
 #define MGBE_MAC_EXT_CNF		0x0140
 #define MGBE_MDIO_SCCD			0x0204
 #define MGBE_MDIO_SCCA			0x0200
+#define MGBE_MAC_MDIO_INTR_STS		0x0214
 #define MGBE_MAC_ADDRH(x)		((0x0008U * (x)) + 0x0300U)
 #define MGBE_MAC_ADDRL(x)		((0x0008U * (x)) + 0x0304U)
 #define MGBE_MAC_INDIR_AC		0x0700
 #define MGBE_MAC_INDIR_DATA		0x0704
+#define MGBE_MAC_PCTH_INTR_STS		0x070C
+#define MGBE_MAC_PCTW_INTR_STS		0x0734
 #define MGBE_MMC_TX_INTR_EN		0x0810
 #define MGBE_MMC_RX_INTR_EN		0x080C
 #define MGBE_MMC_CNTRL			0x0800
diff --git a/osi/core/osi_hal.c b/osi/core/osi_hal.c
index 5a52652..705276f 100644
--- a/osi/core/osi_hal.c
+++ b/osi/core/osi_hal.c
@@ -548,7 +548,7 @@ static void fill_hsi_attributes(struct osi_core_priv_data *const osi_core)
 	nveu32_t i = 0U;
 	nveu32_t instance = 0U;
 
-	if (osi_core->mac == OSI_MAC_HW_MGBE) {
+	if ((osi_core->mac == OSI_MAC_HW_MGBE) || (osi_core->mac == OSI_MAC_HW_MGBE_T26X)) {
 		/* Update MGBE instance */
 		instance = osi_core->instance_id + 1U;
 	} else {
diff --git a/osi/core/xpcs.h b/osi/core/xpcs.h
index 3b33395..941e844 100644
--- a/osi/core/xpcs.h
+++ b/osi/core/xpcs.h
@@ -209,6 +209,8 @@
 #define XPCS_FSM_TO_SEL_MASK				0xC00U
 #define EQOS_PCS_SFTY_TMR_CTRL				0x7E03D4
 #define EQOS_PCS_SFTY_TMR_CTRL_RXFPEI			OSI_BIT(8)
+#define XLGPCS_VR_PCS_SFTY_TMR_CTRL			0xE03E4
+#define XPCS_VR_XS_PCS_SFTY_TMR_CTRL_IFT_SEL		OSI_BIT(8)
 #endif
 /** @} */