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osi: core: correct SSINC value for thor EQOS

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Issue: SSINC and ptp_ref_clk are wongly
programmed
Fix: SSINC should be 4 as per HW guideline
ptp_ref_clk should be 312.5 MHz

Bug 4747430

Change-Id: Ibbcbfa072c91ccb0cf0271169a52fa09869b5038
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3198414
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
This commit is contained in:
Rakesh Goyal
2024-08-22 09:58:33 +00:00
committed by mobile promotions
parent c8bea5c22f
commit cc7aae9570
2 changed files with 11 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
osi/core/core_common.c
View File

@@ -631,9 +631,11 @@ void hw_config_ssir(struct osi_core_priv_data *const osi_core)
const nveu32_t ptp_ssinc[3] = {OSI_PTP_SSINC_4, OSI_PTP_SSINC_6, OSI_PTP_SSINC_4}; const nveu32_t ptp_ssinc[3] = {OSI_PTP_SSINC_4, OSI_PTP_SSINC_6, OSI_PTP_SSINC_4};
/* by default Fine method is enabled */ /* by default Fine method is enabled */
/* Fix the SSINC value based on Exact MAC used */
//TBD: review for T264
val = ptp_ssinc[l_core->l_mac_ver]; val = ptp_ssinc[l_core->l_mac_ver];
/* EQOS T234 SSINC is different from EOQS T264, Logic added for EQOS T264 */
if (osi_core->mac_ver == OSI_EQOS_MAC_5_40) {
val = OSI_PTP_SSINC_4;
}
val |= val << MAC_SSIR_SSINC_SHIFT; val |= val << MAC_SSIR_SSINC_SHIFT;
/* update Sub-second Increment Value */ /* update Sub-second Increment Value */

11
osi/core/osi_hal.c
View File

@@ -472,7 +472,7 @@ static nve32_t osi_ptp_configuration(struct osi_core_priv_data *const osi_core,
* so addend = (2^32 * 1000)/(ptp_ref_clk_rate in MHZ * SSINC); * so addend = (2^32 * 1000)/(ptp_ref_clk_rate in MHZ * SSINC);
*/ */
ssinc = OSI_PTP_SSINC_4; ssinc = OSI_PTP_SSINC_4;
if (osi_core->mac_ver >= OSI_EQOS_MAC_5_30) { if (osi_core->mac_ver == OSI_EQOS_MAC_5_30) {
ssinc = OSI_PTP_SSINC_6; ssinc = OSI_PTP_SSINC_6;
} }
@@ -481,14 +481,13 @@ static nve32_t osi_ptp_configuration(struct osi_core_priv_data *const osi_core,
temp1 = div_u64(temp, temp1 = div_u64(temp,
(nveu64_t)osi_core->ptp_config.ptp_ref_clk_rate); (nveu64_t)osi_core->ptp_config.ptp_ref_clk_rate);
temp2 = div_u64(temp1, (nveu64_t)ssinc); temp2 = div_u64(temp1, (nveu64_t)ssinc);
if (temp2 < UINT_MAX) { if (temp2 <= UINT_MAX) {
osi_core->default_addend = (nveu32_t)temp2; osi_core->default_addend = (nveu32_t)temp2;
} else { } else {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
"core: temp2 >= UINT_MAX\n", 0ULL); "core: temp2 > UINT_MAX\n", (nveu64_t)temp2);
ret = -1; ret = -1;
goto fail; goto fail;
} }
@@ -615,6 +614,10 @@ static nve32_t osi_hal_hw_core_init(struct osi_core_priv_data *const osi_core)
(void)hw_config_rxcsum_offload(osi_core, OSI_ENABLE); (void)hw_config_rxcsum_offload(osi_core, OSI_ENABLE);
osi_core->ptp_config.ptp_ref_clk_rate = ptp_ref_clk_rate[l_core->l_mac_ver]; osi_core->ptp_config.ptp_ref_clk_rate = ptp_ref_clk_rate[l_core->l_mac_ver];
if (osi_core->mac_ver == OSI_EQOS_MAC_5_40) {
osi_core->ptp_config.ptp_ref_clk_rate = MGBE_PTP_CLK_SPEED;
}
osi_core->ptp_config.ptp_filter = OSI_MAC_TCR_TSENA | OSI_MAC_TCR_TSCFUPDT | osi_core->ptp_config.ptp_filter = OSI_MAC_TCR_TSENA | OSI_MAC_TCR_TSCFUPDT |
OSI_MAC_TCR_TSCTRLSSR | OSI_MAC_TCR_TSVER2ENA | OSI_MAC_TCR_TSCTRLSSR | OSI_MAC_TCR_TSVER2ENA |
OSI_MAC_TCR_TSIPENA | OSI_MAC_TCR_TSIPV6ENA | OSI_MAC_TCR_TSIPENA | OSI_MAC_TCR_TSIPV6ENA |