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osi: core: update boundary for lo and hi credit

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As per HW specification update boundary check
for locredit and hicredit.

Bug 3927833

Change-Id: I3b6efeba52a7c40d3f4d276dea50e95310011d5f
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2837043
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Rakesh Goyal
2023-01-04 12:25:43 +05:30
committed by mobile promotions
parent 47e6662a46
commit d2bb5de0f5
1 changed files with 6 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
osi/core/core_common.c
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -1795,10 +1795,8 @@ nve32_t hw_validate_avb_input(struct osi_core_priv_data *const osi_core,
MGBE_MTL_TCQ_ETS_QW_ISCQW_MASK}; MGBE_MTL_TCQ_ETS_QW_ISCQW_MASK};
nveu32_t ETS_SSCR_SSC_MASK[MAX_MAC_IP_TYPES] = {EQOS_MTL_TXQ_ETS_SSCR_SSC_MASK, nveu32_t ETS_SSCR_SSC_MASK[MAX_MAC_IP_TYPES] = {EQOS_MTL_TXQ_ETS_SSCR_SSC_MASK,
MGBE_MTL_TCQ_ETS_SSCR_SSC_MASK}; MGBE_MTL_TCQ_ETS_SSCR_SSC_MASK};
nveu32_t ETS_HCR_HC_MASK[MAX_MAC_IP_TYPES] = {EQOS_MTL_TXQ_ETS_HCR_HC_MASK, nveu32_t ETS_HC_BOUND = 0x8000000U;
MGBE_MTL_TCQ_ETS_HCR_HC_MASK}; nveu32_t ETS_LC_BOUND = 0xF8000000U;
nveu32_t ETS_LCR_LC_MASK[MAX_MAC_IP_TYPES] = {EQOS_MTL_TXQ_ETS_LCR_LC_MASK,
MGBE_MTL_TCQ_ETS_LCR_LC_MASK};
nveu32_t mac = osi_core->mac; nveu32_t mac = osi_core->mac;
if (avb->idle_slope > ETS_QW_ISCQW_MASK[mac]) { if (avb->idle_slope > ETS_QW_ISCQW_MASK[mac]) {
@@ -1815,21 +1813,21 @@ nve32_t hw_validate_avb_input(struct osi_core_priv_data *const osi_core,
ret = -1; ret = -1;
goto fail; goto fail;
} }
if (avb->hi_credit > ETS_HCR_HC_MASK[mac]) { if (avb->hi_credit > ETS_HC_BOUND) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
"Invalid hi credit\n", "Invalid hi credit\n",
(nveul64_t)avb->hi_credit); (nveul64_t)avb->hi_credit);
ret = -1; ret = -1;
goto fail; goto fail;
} }
if (avb->low_credit > ETS_LCR_LC_MASK[mac]) { if ((avb->low_credit < ETS_LC_BOUND) &&
(avb->low_credit != 0U)) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
"Invalid low credit\n", "Invalid low credit\n",
(nveul64_t)avb->low_credit); (nveul64_t)avb->low_credit);
ret = -1; ret = -1;
goto fail; goto fail;
} }
fail: fail:
return ret; return ret;
} }