From d7ecf48908b0bea67bca482348ff7c85cbd3ea2c Mon Sep 17 00:00:00 2001 From: Ajay Gupta Date: Thu, 31 Oct 2019 11:23:32 -0700 Subject: [PATCH] nvethernetrm: fix AXI clock to 125MHz Fixes incorrect number of rx interrupt triggered with rx coalescing (rx-usecs in ethtool) parameter. Bug 200529168 Change-Id: I49ea2c469667e05f7e12f2741984f609127f395c Signed-off-by: Ajay Gupta Reviewed-on: https://git-master.nvidia.com/r/2229564 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-cert Reviewed-by: Narayan Reddy Reviewed-by: Bhadram Varka GVS: Gerrit_Virtual_Submit Reviewed-by: Srinivas Ramachandran Reviewed-by: Ashutosh Jha Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/osi_common.h | 2 -- osi/dma/eqos_dma.c | 15 +++++++++------ osi/dma/eqos_dma.h | 13 ++++++++++++- 3 files changed, 21 insertions(+), 9 deletions(-) diff --git a/include/osi_common.h b/include/osi_common.h index f050c52..d1fab0d 100644 --- a/include/osi_common.h +++ b/include/osi_common.h @@ -35,8 +35,6 @@ #define OSI_NSEC_PER_SEC 1000000000ULL #define OSI_INVALID_VALUE 0xFFFFFFFFU -/* System clock is 62.5MHz */ -#define OSI_ETHER_SYSCLOCK 62500000U #define OSI_PTP_REQ_CLK_FREQ 250000000U #define OSI_ONE_MEGA_HZ 1000000U #define OSI_MAX_RX_COALESCE_USEC 1020U diff --git a/osi/dma/eqos_dma.c b/osi/dma/eqos_dma.c index 3d9f768..540bf7a 100644 --- a/osi/dma/eqos_dma.c +++ b/osi/dma/eqos_dma.c @@ -660,21 +660,24 @@ static void eqos_configure_dma_channel(unsigned int chan, /* Set Receive Interrupt Watchdog Timer Count */ /* conversion of usec to RWIT value - * Eg:System clock is 62.5MHz, each clock cycle would then be 16ns - * For value 0x1 in watchdog timer,device would wait for 256 clk cycles, - * ie, (16ns x 256) => 4.096us (rounding off to 4us) + * Eg:System clock is 125MHz, each clock cycle would then be 8ns + * For value 0x1 in RWT, device would wait for 512 clk cycles with + * RWTU as 0x1, + * ie, (8ns x 512) => 4.096us (rounding off to 4us) * So formula with above values is,ret = usec/4 */ if (osi_dma->use_riwt == OSI_ENABLE && osi_dma->rx_riwt < UINT_MAX) { value = osi_readl((unsigned char *)osi_dma->base + EQOS_DMA_CHX_RX_WDT(chan)); - /* Mask the RWT value */ - value &= ~EQOS_DMA_CHX_RX_WDT_RWT_MASK; + /* Mask the RWT and RWTU value */ + value &= ~(EQOS_DMA_CHX_RX_WDT_RWT_MASK | + EQOS_DMA_CHX_RX_WDT_RWTU_MASK); /* Conversion of usec to Rx Interrupt Watchdog Timer Count */ value |= ((osi_dma->rx_riwt * - (OSI_ETHER_SYSCLOCK / OSI_ONE_MEGA_HZ)) / + (EQOS_AXI_CLK_FREQ / OSI_ONE_MEGA_HZ)) / EQOS_DMA_CHX_RX_WDT_RWTU) & EQOS_DMA_CHX_RX_WDT_RWT_MASK; + value |= EQOS_DMA_CHX_RX_WDT_RWTU_512_CYCLE; osi_writel(value, (unsigned char *)osi_dma->base + EQOS_DMA_CHX_RX_WDT(chan)); } diff --git a/osi/dma/eqos_dma.h b/osi/dma/eqos_dma.h index 93a66ab..766c586 100644 --- a/osi/dma/eqos_dma.h +++ b/osi/dma/eqos_dma.h @@ -23,6 +23,15 @@ #ifndef EQOS_DMA_H_ #define EQOS_DMA_H_ +/** + * @addtogroup EQOS AXI Clock defines + * + * @brief AXI Clock defines + * @{ + */ +#define EQOS_AXI_CLK_FREQ 125000000U +/** @} */ + /** * @addtogroup EQOS1 DMA Channel Register offsets * @@ -81,7 +90,9 @@ #define EQOS_DMA_CHX_TX_CTRL_TXPBL_RECOMMENDED 0x200000U #define EQOS_DMA_CHX_RX_CTRL_RXPBL_RECOMMENDED 0xC0000U #define EQOS_DMA_CHX_RX_WDT_RWT_MASK 0xFFU -#define EQOS_DMA_CHX_RX_WDT_RWTU 256U +#define EQOS_DMA_CHX_RX_WDT_RWTU_MASK 0x30000U +#define EQOS_DMA_CHX_RX_WDT_RWTU_512_CYCLE 0x10000U +#define EQOS_DMA_CHX_RX_WDT_RWTU 512U /* Below macros are used for periodic reg validation for functional safety. * HW register mask - to mask out reserved and self-clearing bits