diff --git a/include/osi_core.h b/include/osi_core.h
index d3fe4c5..a857cd6 100644
--- a/include/osi_core.h
+++ b/include/osi_core.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -1309,6 +1309,9 @@ struct osi_core_priv_data {
 	 * 1 - Primary interface, 2 - secondary interface, 0 - inactive interface
 	 */
 	nveu32_t m2m_role;
+	/** control pps output signal
+	 */
+	nveu32_t pps_frq;
 };
 
 /**
diff --git a/osi/core/core_local.h b/osi/core/core_local.h
index 0cd03a4..d030d65 100644
--- a/osi/core/core_local.h
+++ b/osi/core/core_local.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -355,6 +355,8 @@ struct core_local {
 	nveu32_t hw_init_successful;
 	/** Dynamic MAC to MAC time sync control for secondary interface */
 	nveu32_t m2m_tsync;
+	/** control pps output signal */
+	nveu32_t pps_freq;
 };
 
 /**
diff --git a/osi/core/eqos_core.c b/osi/core/eqos_core.c
index 855580b..21636bb 100644
--- a/osi/core/eqos_core.c
+++ b/osi/core/eqos_core.c
@@ -4186,7 +4186,9 @@ static void eqos_config_tscr(struct osi_core_priv_data *const osi_core,
 			     const nveu32_t ptp_filter)
 {
 	void *addr = osi_core->base;
+	struct core_local *l_core = (struct core_local *)osi_core;
 	nveu32_t mac_tcr = 0U, i = 0U, temp = 0U;
+	nveu32_t value = 0x0U;
 
 	if (ptp_filter != OSI_DISABLE) {
 		mac_tcr = (OSI_MAC_TCR_TSENA	|
@@ -4244,6 +4246,12 @@ static void eqos_config_tscr(struct osi_core_priv_data *const osi_core,
 	eqos_core_safety_writel(osi_core, mac_tcr,
 				(nveu8_t *)addr + EQOS_MAC_TCR,
 				EQOS_MAC_TCR_IDX);
+	value = osi_readla(osi_core, (nveu8_t *)addr + EQOS_MAC_PPS_CTL);
+	value &= ~EQOS_MAC_PPS_CTL_PPSCTRL0;
+	if (l_core->pps_freq == OSI_ENABLE) {
+		value |= OSI_ENABLE;
+	}
+	osi_writela(osi_core, value, (nveu8_t *)addr + EQOS_MAC_PPS_CTL);
 }
 
 /**
diff --git a/osi/core/eqos_core.h b/osi/core/eqos_core.h
index bea364f..1f4cf07 100644
--- a/osi/core/eqos_core.h
+++ b/osi/core/eqos_core.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -129,6 +129,7 @@
 #define EQOS_MAC_PIDR0			0x0BC4
 #define EQOS_MAC_PIDR1			0x0BC8
 #define EQOS_MAC_PIDR2			0x0BCC
+#define EQOS_MAC_PPS_CTL		0x0B70
 #define EQOS_DMA_BMR			0x1000
 #define EQOS_DMA_SBUS			0x1004
 #define EQOS_DMA_ISR			0x1008
@@ -277,6 +278,8 @@
 						 OSI_BIT(4))
 #define EQOS_MAC_RQC1R_OMCBCQ			OSI_BIT(28)
 #define EQOS_MAC_RQC1R_PTPQ_SHIFT		4U
+#define EQOS_MAC_PPS_CTL_PPSCTRL0		(OSI_BIT(3) | OSI_BIT(2) |\
+						 OSI_BIT(1) | OSI_BIT(0))
 #define EQOS_MTL_QTOMR_FTQ_LPOS			OSI_BIT(0)
 #define EQOS_DMA_ISR_MTLIS			OSI_BIT(16)
 #define EQOS_DMA_ISR_MACIS			OSI_BIT(17)
diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c
index ce18c51..bbe882f 100644
--- a/osi/core/mgbe_core.c
+++ b/osi/core/mgbe_core.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -5523,7 +5523,9 @@ static int mgbe_adjust_mactime(struct osi_core_priv_data *osi_core,
 static void mgbe_config_tscr(struct osi_core_priv_data *osi_core,
 			     unsigned int ptp_filter)
 {
+	struct core_local *l_core = (struct core_local *)osi_core;
 	unsigned int mac_tcr = 0;
+	nveu32_t value = 0x0U;
 	void *addr = osi_core->base;
 
 	if (ptp_filter != OSI_DISABLE) {
@@ -5585,6 +5587,13 @@ static void mgbe_config_tscr(struct osi_core_priv_data *osi_core,
 	}
 
 	osi_writela(osi_core, mac_tcr, (unsigned char *)addr + MGBE_MAC_TCR);
+
+	value = osi_readla(osi_core, (nveu8_t *)addr + MGBE_MAC_PPS_CTL);
+	value &= ~MGBE_MAC_PPS_CTL_PPSCTRL0;
+	if (l_core->pps_freq == OSI_ENABLE) {
+		value |= OSI_ENABLE;
+	}
+	osi_writela(osi_core, value, (nveu8_t *)addr + MGBE_MAC_PPS_CTL);
 }
 
 /**
diff --git a/osi/core/mgbe_core.h b/osi/core/mgbe_core.h
index 5591f6d..b038b1f 100644
--- a/osi/core/mgbe_core.h
+++ b/osi/core/mgbe_core.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -112,6 +112,7 @@
 #define MGBE_MAC_TSNSSEC		0x0D30
 #define MGBE_MAC_TSSEC			0x0D34
 #define MGBE_MAC_TSPKID			0x0D38
+#define MGBE_MAC_PPS_CTL		0x0D70
 #define MGBE_MAC_PTO_CR			0x0DC0
 #define MGBE_MAC_PIDR0			0x0DC4
 #define MGBE_MAC_PIDR1			0x0DC8
@@ -252,6 +253,8 @@
 #define MGBE_MAC_L4_ADDR_SP_MASK	0x0000FFFFU
 #define MGBE_MAC_L4_ADDR_DP_MASK	0xFFFF0000U
 #define MGBE_MAC_L4_ADDR_DP_SHIFT	16
+#define MGBE_MAC_PPS_CTL_PPSCTRL0	(OSI_BIT(3) | OSI_BIT(2) |\
+					 OSI_BIT(1) | OSI_BIT(0))
 /** @} */
 
 /**
diff --git a/osi/core/osi_core.c b/osi/core/osi_core.c
index 9656878..7fa9d97 100644
--- a/osi/core/osi_core.c
+++ b/osi/core/osi_core.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -124,6 +124,7 @@ struct osi_core_priv_data *osi_get_core(void)
 
 	g_core[i].tx_ts_head.prev = &g_core[i].tx_ts_head;
 	g_core[i].tx_ts_head.next = &g_core[i].tx_ts_head;
+	g_core[i].pps_freq = OSI_DISABLE;
 
 	return &g_core[i].osi_core;
 }
@@ -202,6 +203,14 @@ nve32_t osi_init_core_ops(struct osi_core_priv_data *const osi_core)
 		l_core->m2m_tsync = OSI_DISABLE;
 	}
 
+	if (osi_core->pps_frq <= OSI_ENABLE) {
+		l_core->pps_freq = osi_core->pps_frq;
+	} else {
+		OSI_CORE_ERR(OSI_NULL, OSI_LOG_ARG_INVALID,
+			     "invalid pps_frq\n", (nveu64_t)osi_core->pps_frq);
+		ret = -1;
+	}
+
 	return ret;
 }