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osi: Enable BASE-R FEC support for 25G

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Bug 4674473

Change-Id: Ic4a0f67158449094a9489afbe8de8d2efc0fdf99
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3316844
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
This commit is contained in:
Mahesh Patil
2025-03-10 22:49:52 +00:00
committed by mobile promotions
parent c13a414c34
commit df0be09573
2 changed files with 43 additions and 23 deletions
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63
osi/core/xpcs.c
View File

@@ -364,32 +364,36 @@ nve32_t xlgpcs_start(struct osi_core_priv_data *osi_core)
ret = -1; ret = -1;
goto fail; goto fail;
} }
/* * XLGPCS programming guideline IAS section 7.1.3.2.2.2 /* * XLGPCS programming guideline IAS section 7.1.3.2.2.2
*/ */
/* 4 Poll SR_PCS_CTRL1 reg RST bit */ if (osi_core->pcs_base_r_fec_en != OSI_ENABLE) {
ctrl = xpcs_read(xpcs_base, XLGPCS_SR_PCS_CTRL1); /* 4 Poll SR_PCS_CTRL1 reg RST bit */
ctrl |= XLGPCS_SR_PCS_CTRL1_RST;
xpcs_write(xpcs_base, XLGPCS_SR_PCS_CTRL1, ctrl);
count = 0;
while (cond == 1) {
if (count > retry) {
ret = -1;
goto fail;
}
count++;
ctrl = xpcs_read(xpcs_base, XLGPCS_SR_PCS_CTRL1); ctrl = xpcs_read(xpcs_base, XLGPCS_SR_PCS_CTRL1);
if ((ctrl & XLGPCS_SR_PCS_CTRL1_RST) == 0U) { ctrl |= XLGPCS_SR_PCS_CTRL1_RST;
cond = 0; xpcs_write(xpcs_base, XLGPCS_SR_PCS_CTRL1, ctrl);
} else {
/* Maximum wait delay as per HW team is 10msec. count = 0;
* So add a loop for 1000 iterations with 1usec delay, while (cond == 1) {
* so that if check get satisfies before 1msec will come if (count > retry) {
* out of loop and it can save some boot time ret = -1;
*/ goto fail;
osi_core->osd_ops.udelay(10U); }
count++;
ctrl = xpcs_read(xpcs_base, XLGPCS_SR_PCS_CTRL1);
if ((ctrl & XLGPCS_SR_PCS_CTRL1_RST) == 0U) {
cond = 0;
} else {
/* Maximum wait delay as per HW team is 10msec.
* So add a loop for 1000 iterations with 1usec delay,
* so that if check get satisfies before 1msec will come
* out of loop and it can save some boot time
*/
osi_core->osd_ops.udelay(10U);
}
} }
} }
/* 5 Program SR_AN_CTRL reg AN_EN bit to disable auto-neg */ /* 5 Program SR_AN_CTRL reg AN_EN bit to disable auto-neg */
ctrl = xpcs_read(xpcs_base, XLGPCS_SR_AN_CTRL); ctrl = xpcs_read(xpcs_base, XLGPCS_SR_AN_CTRL);
ctrl &= ~XLGPCS_SR_AN_CTRL_AN_EN; ctrl &= ~XLGPCS_SR_AN_CTRL_AN_EN;
@@ -856,6 +860,21 @@ static nve32_t xpcs_base_r_fec(struct osi_core_priv_data *osi_core)
nveu32_t ctrl = 0; nveu32_t ctrl = 0;
nve32_t ret = 0; nve32_t ret = 0;
if ((osi_core->pcs_base_r_fec_en == OSI_ENABLE) &&
(osi_core->uphy_gbe_mode == OSI_GBE_MODE_25G)) {
/* Program SR_AN_CTRL reg AN_EN bit to disable auto-neg */
ctrl = xpcs_read(xpcs_base, XLGPCS_SR_AN_CTRL);
ctrl &= ~XLGPCS_SR_AN_CTRL_AN_EN;
ret = xpcs_write_safety(osi_core, XLGPCS_SR_AN_CTRL, ctrl);
if (ret != 0) {
goto fail;
}
osi_writela(osi_core, XPCS_WRAP_UPHY_TIMEOUT_CONTROL_0_0_VALUE,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_TIMEOUT_CONTROL_0_0);
}
/* Enable/Disable BASE-R FEC */ /* Enable/Disable BASE-R FEC */
ctrl = xpcs_read(xpcs_base, XPCS_SR_PMA_KR_FEC_CTRL); ctrl = xpcs_read(xpcs_base, XPCS_SR_PMA_KR_FEC_CTRL);
if (osi_core->pcs_base_r_fec_en == OSI_ENABLE) { if (osi_core->pcs_base_r_fec_en == OSI_ENABLE) {
@@ -869,7 +888,7 @@ static nve32_t xpcs_base_r_fec(struct osi_core_priv_data *osi_core)
ret = xpcs_write_safety(osi_core, XPCS_SR_PMA_KR_FEC_CTRL, ctrl); ret = xpcs_write_safety(osi_core, XPCS_SR_PMA_KR_FEC_CTRL, ctrl);
if (ret != 0) { if (ret != 0) {
goto fail; goto fail;
} }
fail: fail:
return ret; return ret;

3
osi/core/xpcs.h
View File

@@ -70,7 +70,7 @@
#define T26X_XPCS_WRAP_UPHY_TX_CTRL_2 0x8008 #define T26X_XPCS_WRAP_UPHY_TX_CTRL_2 0x8008
#define T26X_XPCS_WRAP_UPHY_RX_CTRL_2 0x8040 #define T26X_XPCS_WRAP_UPHY_RX_CTRL_2 0x8040
#define T26X_XPCS_WRAP_UPHY_RX_CTRL_3 0x8044 #define T26X_XPCS_WRAP_UPHY_RX_CTRL_3 0x8044
#define T26X_XPCS_WRAP_UPHY_TIMEOUT_CONTROL_0_0 0x8070
/** @} */ /** @} */
@@ -134,6 +134,7 @@
#define XPCS_10G_WRAP_UPHY_RX_CTRL_2_SLEEP_CAL_EN_DLY 0xCAAU #define XPCS_10G_WRAP_UPHY_RX_CTRL_2_SLEEP_CAL_EN_DLY 0xCAAU
#define XPCS_10G_WRAP_UPHY_TX_CTRL_3_DATAREADY_DATAEN_DLY 0x50U #define XPCS_10G_WRAP_UPHY_TX_CTRL_3_DATAREADY_DATAEN_DLY 0x50U
#define XPCS_10G_WRAP_UPHY_RX_CTRL_3_CAL_DONE_DATA_EN_DLY 0x32U #define XPCS_10G_WRAP_UPHY_RX_CTRL_3_CAL_DONE_DATA_EN_DLY 0x32U
#define XPCS_WRAP_UPHY_TIMEOUT_CONTROL_0_0_VALUE 0x3FFFD90
#define EQOS_XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8038 #define EQOS_XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8038
#define EQOS_XPCS_WRAP_UPHY_STATUS 0x8064 #define EQOS_XPCS_WRAP_UPHY_STATUS 0x8064