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osi: core: Set QHLBF bit

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As per HW fix, program QHLBF to 1 to get
HLBF error in 1-2 cycle of GCL.

Bug 200778825
Bug 200649072
case: 01085007

Change-Id: I18cfa6ad4eda56e2684abd86b7dc02c7a143c0ef
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2601421
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Rakesh Goyal
2021-09-28 01:40:39 +05:30
committed by mobile promotions
parent d58825f314
commit e6a2dd50b4
4 changed files with 4 additions and 0 deletions
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1
osi/core/eqos_core.c
View File

@@ -4731,6 +4731,7 @@ static int eqos_hw_config_est(struct osi_core_priv_data *osi_core,
/* Store table */
val |= EQOS_MTL_EST_CONTROL_SSWL;
val |= EQOS_MTL_EST_CONTROL_EEST;
val |= EQOS_MTL_EST_CONTROL_QHLBF;
osi_writela(osi_core, val, (nveu8_t *)base + EQOS_MTL_EST_CONTROL);
return ret;

1
osi/core/eqos_core.h
View File

@@ -560,6 +560,7 @@
#define EQOS_MTL_EST_CONTROL_LCSE_VAL 0U
#define EQOS_MTL_EST_CONTROL_DFBS OSI_BIT(5)
#define EQOS_MTL_EST_CONTROL_DDBF OSI_BIT(4)
#define EQOS_MTL_EST_CONTROL_QHLBF OSI_BIT(3)
#define EQOS_MTL_EST_CONTROL_SSWL OSI_BIT(1)
#define EQOS_MTL_EST_CONTROL_EEST OSI_BIT(0)
#define EQOS_MTL_EST_OVERHEAD_OVHD (OSI_BIT(5) | OSI_BIT(4) | \

1
osi/core/mgbe_core.c
View File

@@ -4810,6 +4810,7 @@ static int mgbe_hw_config_est(struct osi_core_priv_data *osi_core,
/* Store table */
val |= MGBE_MTL_EST_SSWL;
val |= MGBE_MTL_EST_EEST;
val |= MGBE_MTL_EST_QHLBF;
osi_writela(osi_core, val, (unsigned char *)
base + MGBE_MTL_EST_CONTROL);

1
osi/core/mgbe_core.h
View File

@@ -648,6 +648,7 @@
/* EST controlOSI_BITmap */
#define MGBE_MTL_EST_EEST OSI_BIT(0)
#define MGBE_MTL_EST_SSWL OSI_BIT(1)
#define MGBE_MTL_EST_QHLBF OSI_BIT(3)
/* EST GCL controlOSI_BITmap */
#define MGBE_MTL_EST_ADDR_SHIFT 8
#define MGBE_MTL_EST_ADDR_MASK (OSI_BIT(8) | OSI_BIT(9) | \