From e8fbce237cef2d28da9c3bb6058f03a1be65fcbc Mon Sep 17 00:00:00 2001 From: Om Prakash Singh Date: Mon, 19 Sep 2022 09:32:58 +0530 Subject: [PATCH] osi: core: Disable HSI causing problem 1) Disable PCS FEC_EN programming as should be enabled only for autonagotiation mode and phy support is also needed. Current phy AQR113C does not has FEC capability (Bug 3799112) 2) Enabling MAC_FSM_CONTROL.TMOUTEN cauing uncorrected error on boot (Bug 3584387) Bug 3590939 Change-Id: Ib5491c64c1028e312470d113934848098e2b0fd5 Signed-off-by: Om Prakash Singh Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2777890 Reviewed-by: svcacv Reviewed-by: Bhadram Varka Reviewed-by: Mohan Thadikamalla Reviewed-by: Ashutosh Jha Tested-by: Sanath Kumar Gampa GVS: Gerrit_Virtual_Submit --- osi/core/eqos_core.c | 3 ++- osi/core/mgbe_core.c | 14 ++------------ 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/osi/core/eqos_core.c b/osi/core/eqos_core.c index 86848c7..0826004 100644 --- a/osi/core/eqos_core.c +++ b/osi/core/eqos_core.c @@ -1028,7 +1028,8 @@ static nve32_t eqos_hsi_configure(struct osi_core_priv_data *const osi_core, /* T23X-EQOS_HSIv2-3: Enabling and Initialization of Watchdog */ /* T23X-EQOS_HSIv2-4: Enabling of Consistency Monitor for FSM States */ - value = (EQOS_PRTYEN | EQOS_TMOUTEN); + /* TODO enable EQOS_TMOUTEN. Bug 3584387 */ + value = EQOS_PRTYEN; osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MAC_FSM_CONTROL); diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c index 07260a7..d5f8e10 100644 --- a/osi/core/mgbe_core.c +++ b/osi/core/mgbe_core.c @@ -2154,12 +2154,6 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core, osi_core->hsi.enabled = OSI_ENABLE; osi_core->hsi.reporter_id = hsi_err_code[osi_core->instance_id][REPORTER_IDX]; - /* T23X-MGBE_HSIv2-10 Enable PCS ECC */ - value = (EN_ERR_IND | FEC_EN); - ret = xpcs_write_safety(osi_core, XPCS_BASE_PMA_MMD_SR_PMA_KR_FEC_CTRL, value); - if (ret != 0) { - return ret; - } /* T23X-MGBE_HSIv2-12:Initialization of Transaction Timeout in PCS */ /* T23X-MGBE_HSIv2-11:Initialization of Watchdog Timer */ value = (0xCCU << XPCS_SFTY_1US_MULT_SHIFT) & XPCS_SFTY_1US_MULT_MASK; @@ -2189,7 +2183,8 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core, /* T23X-MGBE_HSIv2-3: Enabling and Initialization of Watchdog Timer */ /* T23X-MGBE_HSIv2-4: Enabling of Consistency Monitor for XGMAC FSM State */ - value = (MGBE_PRTYEN | MGBE_TMOUTEN); + /* TODO enable MGBE_TMOUTEN. Bug 3584387 */ + value = MGBE_PRTYEN; osi_writela(osi_core, value, (nveu8_t *)osi_core->base + MGBE_MAC_FSM_CONTROL); @@ -2243,11 +2238,6 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core, } else { osi_core->hsi.enabled = OSI_DISABLE; - /* T23X-MGBE_HSIv2-10 Disable PCS ECC */ - ret = xpcs_write_safety(osi_core, XPCS_BASE_PMA_MMD_SR_PMA_KR_FEC_CTRL, 0); - if (ret != 0) { - return ret; - } /* T23X-MGBE_HSIv2-11:Deinitialization of Watchdog Timer */ ret = xpcs_write_safety(osi_core, XPCS_VR_XS_PCS_SFTY_TMR_CTRL, 0); if (ret != 0) {