diff --git a/include/osi_dma.h b/include/osi_dma.h
index 8127561..5421beb 100644
--- a/include/osi_dma.h
+++ b/include/osi_dma.h
@@ -58,6 +58,15 @@
 #define osi_likely(x)			__builtin_expect(!!(x), 1)
 /** @} */
 
+/**
+ * @addtogroup Channel Mask
+ * @brief Chanel mask for Tx and Rx interrupts
+ * @{
+ */
+#define OSI_VM_IRQ_TX_CHAN_MASK(x)	OSI_BIT((x) * 2U)
+#define OSI_VM_IRQ_RX_CHAN_MASK(x)	OSI_BIT(((x) * 2U) + 1U)
+/** @} */
+
 /**
  * OSI error macro definition,
  * @param[in] priv: OSD private data OR NULL
diff --git a/osi/common/mgbe_common.c b/osi/common/mgbe_common.c
index 315fdbf..0ca6879 100644
--- a/osi/common/mgbe_common.c
+++ b/osi/common/mgbe_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -70,3 +70,16 @@ nveul64_t mgbe_get_systime_from_mac(void *addr)
 
 	return ns;
 }
+
+nveu32_t mgbe_is_mac_enabled(void *addr)
+{
+	nveu32_t enable = OSI_DISABLE;
+	nveu32_t reg;
+
+	reg = osi_readl((nveu8_t *)addr + MGBE_MAC_TX);
+	if ((reg & (MGBE_MCR_TE)) == MGBE_MCR_TE) {
+		enable = OSI_ENABLE;
+	}
+
+	return enable;
+}
diff --git a/osi/common/mgbe_common.h b/osi/common/mgbe_common.h
index 1baff90..7ebffeb 100644
--- a/osi/common/mgbe_common.h
+++ b/osi/common/mgbe_common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -24,15 +24,20 @@
 #define INCLUDED_MGBE_COMMON_H
 
 /**
- * @addtogroup MGBE-MAC MGBE MAC PTP HW feature registers
+ * @addtogroup MGBE-MAC MGBE MAC common HW feature registers
  *
  * @{
  */
 #define MGBE_MAC_STSR			0x0D08
 #define MGBE_MAC_STNSR			0x0D0C
 #define MGBE_MAC_STNSR_TSSS_MASK	0x7FFFFFFFU
+
+#define MGBE_MAC_TX			0x0000
+#define MGBE_MCR_TE			OSI_BIT(0)
 /** @} */
 
+
 nveul64_t mgbe_get_systime_from_mac(void *addr);
+nveu32_t mgbe_is_mac_enabled(void *addr);
 
 #endif /* INCLUDED_MGBE_COMMON_H */
diff --git a/osi/common/osi_common.c b/osi/common/osi_common.c
index 9e2b26e..18df8ff 100644
--- a/osi/common/osi_common.c
+++ b/osi/common/osi_common.c
@@ -21,6 +21,7 @@
  */
 
 #include "eqos_common.h"
+#include "mgbe_common.h"
 #include "../osi/common/common.h"
 
 void common_get_systime_from_mac(void *addr, nveu32_t mac, nveu32_t *sec,
@@ -29,15 +30,12 @@ void common_get_systime_from_mac(void *addr, nveu32_t mac, nveu32_t *sec,
 	nveu64_t temp;
 	nveu64_t remain;
 	nveul64_t ns;
+	typedef nveul64_t (*get_time)(void *addr);
+	get_time i_ops[MAX_MAC_IP_TYPES] = {
+		eqos_get_systime_from_mac, mgbe_get_systime_from_mac
+	};
 
-	if (mac == OSI_MAC_HW_EQOS) {
-		ns = eqos_get_systime_from_mac(addr);
-	} else if (mac == OSI_MAC_HW_MGBE) {
-		ns = eqos_get_systime_from_mac(addr);
-	} else {
-		/* Non EQOS HW is supported yet */
-		return;
-	}
+	ns = i_ops[mac](addr);
 
 	temp = div_u64_rem((nveu64_t)ns, OSI_NSEC_PER_SEC, &remain);
 	if (temp < UINT_MAX) {
@@ -54,12 +52,12 @@ void common_get_systime_from_mac(void *addr, nveu32_t mac, nveu32_t *sec,
 
 nveu32_t common_is_mac_enabled(void *addr, nveu32_t mac)
 {
-	if (mac == OSI_MAC_HW_EQOS) {
-		return eqos_is_mac_enabled(addr);
-	} else {
-		/* Non EQOS HW is supported yet */
-		return OSI_DISABLE;
-	}
+	typedef nveu32_t (*mac_enable_arr)(void *addr);
+	mac_enable_arr i_ops[MAX_MAC_IP_TYPES] = {
+		eqos_is_mac_enabled, mgbe_is_mac_enabled
+	};
+
+	return i_ops[mac](addr);
 }
 
 nveu64_t div_u64_rem(nveu64_t dividend, nveu64_t divisor,
diff --git a/osi/core/xpcs.c b/osi/core/xpcs.c
index b6578e8..8b9c392 100644
--- a/osi/core/xpcs.c
+++ b/osi/core/xpcs.c
@@ -135,6 +135,13 @@ int xpcs_start(struct osi_core_priv_data *osi_core)
 	int ret = 0;
 	int cond = 1;
 
+	if (osi_core->xpcs_base == OSI_NULL) {
+		OSI_CORE_ERR(OSI_NULL, OSI_LOG_ARG_HW_FAIL,
+			     "XPCS base is NULL", 0ULL);
+		/* TODO: Remove this once silicon arrives */
+		return 0;
+	}
+
 	ctrl = xpcs_read(xpcs_base, XPCS_SR_MII_CTRL);
 	ctrl |= XPCS_SR_MII_CTRL_AN_ENABLE;
 	xpcs_write(xpcs_base, XPCS_SR_MII_CTRL, ctrl);
@@ -205,8 +212,12 @@ int xpcs_init(struct osi_core_priv_data *osi_core)
 	unsigned int ctrl = 0;
 	int cond = 1;
 
-	if (osi_core->xpcs_base == OSI_NULL)
-		return -1;
+	if (osi_core->xpcs_base == OSI_NULL) {
+		OSI_CORE_ERR(OSI_NULL, OSI_LOG_ARG_HW_FAIL,
+			     "XPCS base is NULL", 0ULL);
+		/* TODO: Remove this once silicon arrives */
+		return 0;
+	}
 
 	/* Switching to USXGMII Mode based on
 	 * XPCS programming guideline 7.6