Issue: default IVC error threshoud 16k. Which is not same as
Other error like RX/TX CRC error. It is conflicting with
expection of DT based error reporting threshold
"nvidia,hsi_err_count_threshold"
Fix: Set ICV error threshold to 1 to match the other error interrupt
frequnecy.
Bug 3543410
Change-Id: Ic64fcdaa007e9a57823515dc8f970d636b34eaa1
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2696380
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
Issue: Found aroung 900 MISRA?COVERITY defects on
OSI MACSEC changes
Fix: Fixed the defects by making minor changes without
impacting the functionality
Removed calling poll_for_dbg_buf_update, poll_for_kt_update
and poll_for_lut_update before lut_write as we are anyhow
polling after the lut_write
Bug 3460422
Change-Id: Ib33e8188cd90472b851732f0936c3e29142bb4a3
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2618714
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
- Convert primitive data type to nv_ type's
- Replace debug pr_ prints with OSI_CORE_ print macro's
- Add all macsec register macro's with prefix MACSEC_
- Update all osi function header as per 5.2 coding guidelines(PLC)
- Remove printk.h header file and use OSI_CORE_ERR macro's in all prints
- Implement clean up LUT's in add_upd_sc() and del_upd_sc()
Bug 3264523
Change-Id: Ie41097c85fbcb90ce0c4cac470fe0f068ed22247
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2548476
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit adds support for MACsec controller HW
operations. The MACsec HW ops can be accessed via
osi_core layer.
Currently, MACsec HW is enabled when MAC interface
is brough up, with no LUT entry so that packets
will still be bypassed. MTU check is enabled and
default interrupts are enabled for statistics.
Bug 2913560
Change-Id: I62e8567fac6603db47f4069a40458038f9b4178a
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
