Commit Graph

13 Commits

Author SHA1 Message Date
Rakesh Goyal
a5c2423f63 core: enable m2m_sync for primary and secondary interfaces
Issue: Ask is to enable Mac-to-Mac tsync
on interface for primary and secondary interface.

Fix: update default value.

Bug 200733666

Change-Id: Ie00e3cf96d0deb75d7c623a63bc0d06ed637ca2c
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2628723
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Sheetal Tigadoli <stigadoli@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-12-06 04:35:42 -08:00
Rakesh Goyal
81e1442693 nvethernetrm: core: MAC to MAC tsync dynamic support
Add code to support enable/disable M2M sync using
ioctl.

Bug 200733666

Change-Id: Ifedad7981644c816345f3e10a0b0f8289e032200
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614964
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-11-02 04:07:38 -07:00
Rakesh Goyal
61be2488de nvethernetrm: MAC to MAC time sync
- Add code to store role of FD
- Function to return osi_core pointer for
  first role match.
- add code to calculate time offset between
  Primary and Secondary PTP controller HW time.
- calculate frequency adjustment calculation.
- call appropriate HAL function for
  secondary interface.

Bug 200733666

Change-Id: I7a141ea691d80d9f69fd18b28ae0964cb1bf2fb3
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614283
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-11-02 04:07:33 -07:00
Mohan Thadikamalla
31058b6774 osi: core: Add MTU IOCTL support
Issue:
When the ethernet server got enabled,
the MTU changes are not getting
communicated to the ethernet server.

Fix:
Add new OSI IOCTL and implement HAL
and IVC message for ethernet server.

Bug 3402313

Change-Id: I28bab58c2847d275324e54229ac50459d3059d26
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2610189
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-10-18 21:43:48 -07:00
Rakesh Goyal
972305578c core: add CMD_PTP_TSC_CAP to capture time
issue: Requirement is to have a method by which
       TSC-PTP-CAPTURE can be initiated.

fix: Having osi_core ioctl to trigger and capture
     TSC-PTP timestamp using HW logic.
     Caller need to call osi_handle_ioctl with
     command as OSI_CMD_CAP_TSC_PTP,
     osi_core pointer and osi_core_ptp_tsc_data
     structure.

Bug 200736396

Change-Id: I511dc4f490fdef81655a62c18268764741855fe4
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2554284
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-09-22 15:39:49 -07:00
Rakesh Goyal
a9b03b83a9 core: mgbe: use lock for time stamping
Using lock for protect critical section between
common interrupt and ioctl call to read
timestamp

Add mmc counters for lock failure during node
addition and deletion.

Bug 200743666

Change-Id: I12a2e57993e91d6ed50ed0efc84d1b60ef736677
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2590099
Tested-by: Gaurav Asati <gasati@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-09-20 11:09:19 -07:00
Narayan Reddy
36510e26ad eqos: set ssnic to 6
Set SSIN to 6 for EQOS mac version 5.3

Bug 200760072

Change-Id: I72923d42313880dd362b7b6b197269f3495a18de
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2575178
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-08-16 15:26:00 -07:00
Bhadram Varka
3293a90aba osi: Add core debug for registers/structures
- Adds core debugging for registers/structures.
- Add change to use single macro for CORE and DMA.

Bug 200737108

Change-Id: If96af2ef0c39e01b6c1dad74ee11fd820df76a8d
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2559319
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-07-16 16:46:03 -07:00
Bhadram Varka
d4e6ad6ec6 osi: use max_chans based on MAC version
Issue: Maximum number of DMA channels is different for
Xavier/Orin EQOS/MGBE IP's. Using macro of maximum number
of channels will create problem for other IP's.

Fix: Assign maximum number of DMA channels based on MAC version.

Bug 200741194

Change-Id: I321780b6868dfb36700863a5852b76424d3bbf6b
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2556425
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-07-13 09:22:21 -07:00
rakesh goyal
1a2c9a3d94 osi: common: Add support for MGBE 2 step timestamp
- OSI DMA
-- During Trasnmit:
--- For EQOS/MGBE one steps PTP Reads TS and update
    in TX done structure.

--- For MGBE 2 steps PTP or 1 step slave, update flags
    TS_POLL and update pkt_id as unique ID to be used
    for polling by OSD after Common interrupt handling.
    packet_id = MSB 4 bits channel_number and LSB 6-bits,
    local index of PTP TS FIFO.

-- On transmit complete
--- If TS is part of Tx done context set OSI_TXDONE_CX_TS
--- If TS is not part of Tx done context and delayed set
OSI_TXDONE_CX_TS_DELAY.

- OSI Core
-- On Common interrupt:
--- If MGBE_ISR_TSIS is set, read time stamp to internal
    array from HW fifo, until it is completely read or array
    is full.
--- Provide an IOCTL OSI_CMD_GET_TX_TS, to read TS for the
    specified pkt_id from OSD via structure osi_core_tx_ts
--- Provide an IOCTL OSI_CMD_FREE_TS, to free TS for the
    specified pkt_id from OSD path

Bug 200603265

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Change-Id: Ib3e02031393e40988074095e5a135bb4e839d7f4
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2543792
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-06-29 10:36:51 -07:00
nannaiah
41b0480d3b nvethernetrm: Update IVC support for macsec
1. Cleanup ivc_cmd to remove unwanted commands.
2. Update macsec IVC API's.
3. Add HAL read and write register.

Bug 2694285
Bug 2694285

Change-Id: I4d120b7bcfdc9ed65e2bf35a54fa4233a8b6e534
Signed-off-by: Nagaraj annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2529496
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
2021-06-21 07:07:10 +05:30
Bhadram Varka
1eadb81047 osi: enable validation of function pointer
Function pointer mgbe_validate_dma_regs() missing
for mgbe which resulted in failure. Adding dummy
function to make sure validate function pointers
will pass.

Bug 200671160

Change-Id: I4c998c86b56451e180e4ee0614192b6100d88bde
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2517631
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
2021-06-21 07:07:10 +05:30
Rakesh Goyal
6cb30389f3 nvethernetrm: add interface operations for virtualization/non-virtualization
Issue:  In current implementation virualization
	callback are at HW ops level, which leads
        to multiple IVC calls.
Fix:	- IVC call happens only for core API's in case
	virtualization
	- For non-virtualization case HW operations will
	be invoked directly from OS OSD.
	- From Ethernet server OSD - OSI HAL API's
	should be called to access the HW operations

Bug 200671160

Change-Id: Ic3730fb822ae37fdf29fabf429f18f5d5bacd210
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2509243
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
2021-06-21 07:07:10 +05:30