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222 Commits

Author SHA1 Message Date
Om Prakash Singh
36a6a3d487 osi: core: macsec: enable SECURE_REG_VIOL intr 
enable SECURE_REG_VIOL interrupt to generate
uncorrected Error for illegal access errors
for MACSEC Registers

Bug 3590939

Change-Id: I4f50c1b709ed3662eb6062dcbbbe42a8e36f101c
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2767836
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-11-09 11:18:14 -08:00
Narayan Reddy
81242cd874 osi: core: Fix misc optimizations 
1) remove duplicate checks
2) remove unused APIs
3) moved to STRIPPED if not used

Bug 3701869

Change-Id: Id6ba8649ff5135affa949ea8dde947db10003f80
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2784309
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-04 16:17:25 -07:00
Zhongjie Wang
4a9893133d osi: dma: using swcx to store nvsocket rx data idx 
- Added a data_idx field in rx swcx to store nvsocket data index.
  Tx data idx has been added in a earlier commit.

Jira NET-242

Change-Id: I81e4c41efceabab4dbf556ac3f57ca26e0737a81
Signed-off-by: Zhongjie Wang <zhowang@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2778530
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-10-25 18:05:24 -07:00
Diptanshu Jamgade
4a8382d6fb nvethernetrm: update OSI_PAUSE_FRAMES_ENABLE macro 
Update OSI_PAUSE_FRAMES_ENABLE as per the updated
DT-bindings.

Bug 3529804

Change-Id: Ice290ef85c370956cec2a7b29cc0b6f82ac39093
Signed-off-by: Diptanshu Jamgade <djamgade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2790122
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-10-20 02:13:37 -07:00
Bhadram Varka
492fa1868d osi: core: remove safety backup and save/restore code 
Bug 3701869

Change-Id: Ib2b139db7c8829d01f57581a18506ba6641cd4ab
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2787478
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-10-06 17:26:44 -07:00
Narayan Reddy
4c85b5e49e osi: core: Fix MISRA issues 
===== DIFF ======
Total misra violation count changed by -71
Rule: MISRA_C-2012_Directive_4.5 Diff: -3
Rule: MISRA_C-2012_Rule_11.1 Diff: -5
Rule: MISRA_C-2012_Rule_11.3 Diff: -1
Rule: MISRA_C-2012_Rule_11.5 Diff: 1
Rule: MISRA_C-2012_Rule_12.1 Diff: -6
Rule: MISRA_C-2012_Rule_12.2 Diff: -7
Rule: MISRA_C-2012_Rule_15.1 Diff: -1
Rule: MISRA_C-2012_Rule_15.6 Diff: -1
Rule: MISRA_C-2012_Rule_16.1 Diff: -1
Rule: MISRA_C-2012_Rule_16.3 Diff: -1
Rule: MISRA_C-2012_Rule_17.7 Diff: -4
Rule: MISRA_C-2012_Rule_17.8 Diff: -5
Rule: MISRA_C-2012_Rule_2.4 Diff: -4
Rule: MISRA_C-2012_Rule_2.5 Diff: -18
Rule: MISRA_C-2012_Rule_20.5 Diff: -1
Rule: MISRA_C-2012_Rule_5.6 Diff: -1
Rule: MISRA_C-2012_Rule_5.8 Diff: -1
Rule: MISRA_C-2012_Rule_5.9 Diff: -4
Rule: MISRA_C-2012_Rule_8.3 Diff: -2
Rule: MISRA_C-2012_Rule_8.9 Diff: -5
Rule: MISRA_C-2012_Rule_9.5 Diff: -1
Rule: Total Diff: -71

Bug 3695218

Change-Id: I9bd904f8a77195ca34fb2d47639a214f0083ccf7
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2776281
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-29 19:38:37 -07:00
Bhadram Varka
5fba408c31 osi: mgbe: configure MTL RXFIFO and flow control 
MTL RXFIFO memory available for MGBE - 192KB
Below is the distribution -
1) Q0 - 160KB
2) Q1 to Q8 - 2KB
3) Q9 - 16KB

It also update flow control parameters for
the Rx queues
1) Q0 - FULL_MINUS_32K
2) Q1 to Q9 - FULL_MINUS_1_5K

Bug 3787316

Change-Id: I3049d742e784aa3273090191856482121a3e1d3e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2779472
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-09-28 12:47:58 -07:00
Rakesh Goyal
80575def01 nvethernetrm: support L2 filter from ioctls 
Move L2 and L3 structure to osi_core as new structure
at OSD level created to user data.
Number of max L2 filter check based on mac version.

Bug 3659048

Change-Id: I9e1e7c015e8c3a0579a363ccd6bcfe9d84e67eea
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2777333
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-24 13:21:25 -07:00
Rakesh Goyal
fdf60cfb28 nvethernetrm: update filename and location 
Update file name to be added in SDK

Bug 3704251

Change-Id: Ibc6b53a6c152973f249d8af94a33cd537b1ea7ec
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2778302
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-21 01:13:51 -07:00
Rakesh Goyal
6b4ddb8043 nvethernetrm: take exported ioctl related header out 
Issue: SW needs to support IOCTL on safety builds and
these header should be exposed to user

Fix: Create new header file which is exposed externally
     Fix Coverity issues
     Enable TSN and FRP for safety build
     Optimize the code between eqos and mgbe

Bug 3704251

Change-Id: I2807f8283a296de1f96d3f902cb4ad5a4781be50
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2759333
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
 2022-09-12 20:52:00 -07:00
Hareesh Kesireddy
744ff93208 osi: dma: provide choice for driver to skip dmb 
- Added a skip dmb flag in tx_ring to let driver
  decide whether barrier need to be performed or not.
- Using rsvd1 in tx swcx for storing nvsocket data index.

Bug 3672681
Jira NET-332

Change-Id: Ie35b7487c6ba2ae92acd46ec51ec4342b856e404
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2771038
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-09-11 23:37:21 -07:00
Bhadram Varka
f77e6e4eb6 osi: dma: Fix MISRA issues 
===== DIFF ======
Total misra violation count changed by -162
Rule: MISRA_C-2012_Directive_4.6 Diff: -13
Rule: MISRA_C-2012_Directive_4.9 Diff: 5
Rule: MISRA_C-2012_Rule_10.1 Diff: -2
Rule: MISRA_C-2012_Rule_11.3 Diff: -15
Rule: MISRA_C-2012_Rule_11.5 Diff: 15
Rule: MISRA_C-2012_Rule_12.2 Diff: -2
Rule: MISRA_C-2012_Rule_15.1 Diff: 64
Rule: MISRA_C-2012_Rule_15.4 Diff: 5
Rule: MISRA_C-2012_Rule_15.5 Diff: -76
Rule: MISRA_C-2012_Rule_15.6 Diff: -1
Rule: MISRA_C-2012_Rule_15.7 Diff: -2
Rule: MISRA_C-2012_Rule_16.4 Diff: -1
Rule: MISRA_C-2012_Rule_2.3 Diff: -2
Rule: MISRA_C-2012_Rule_2.4 Diff: -1
Rule: MISRA_C-2012_Rule_2.5 Diff: -106
Rule: MISRA_C-2012_Rule_5.7 Diff: -1
Rule: MISRA_C-2012_Rule_5.9 Diff: -6
Rule: MISRA_C-2012_Rule_8.13 Diff: -18
Rule: MISRA_C-2012_Rule_8.2 Diff: -1
Rule: MISRA_C-2012_Rule_8.3 Diff: -2
Rule: MISRA_C-2012_Rule_8.9 Diff: -2
Rule: Total Diff: -162
*******************CERT report
Analysis summary report:
Defects/Coding rule violations found : 47 Total
	CERT_INT30-C 	 47 - (Deviation Not approved)
	Total 	 47
===== DIFF ======
Total cert violation count changed by -16
Rule: CERT_INT30-C Diff: -16
Rule: Total Diff: -16
*******************CERT ADV report
Analysis summary report:
Defects/Coding rule violations found : 36 Total
	CERT_DCL37-C (Full Deviation) 	 36 - (Deviation Approved)
	Total 	 36
===== DIFF ======
Total cert_adv violation count changed by -76
Rule: CERT_DCL37-C Diff: -62
Rule: CERT_EXP39-C Diff: -14
Rule: Total Diff: -76

JIRA NET-224

Change-Id: I2084da3d98646e6f9fb7933adbee39343e509e8d
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2744955
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-09 11:15:17 -07:00
Narayan Reddy
28053a560e osi: core: fix misra 2.x rules 
===== DIFF ======
Total misra violation count changed by -591
Rule: MISRA_C-2012_Rule_2.2 Diff: -1
Rule: MISRA_C-2012_Rule_2.3 Diff: -3
Rule: MISRA_C-2012_Rule_2.4 Diff: -2
Rule: MISRA_C-2012_Rule_2.5 Diff: -585
Rule: Total Diff: -591

Bug 3695218

Change-Id: I57e85ba94f434cb3bd729b4f5f75bb4a592fb279
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2768383
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-02 04:58:41 -07:00
Narayan Reddy
f816ebf1e8 osi: core: fix misra 4.6 rule 
===== DIFF ======
Total misra violation count changed by -240
Rule: MISRA_C-2012_Directive_4.6 Diff: -240
Rule: Total Diff: -240

Bug 3695218

Change-Id: Ida2d3a775872637eda3058ea361a00346c86f7f7
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2767895
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-08-30 00:05:29 -07:00
Narayan Reddy
3bf72bdd4a mgbe: core: call lane bringup on local fault 
call lane bringup when there are local faults
and stop the network queues.
restart the network queues when proper link is up

Bug 3744088
Bug 3654543
Bug 3665378

Change-Id: I33180c965b29543dcdfb0d8f611be06b6b97a42e
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2730882
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-08-17 10:38:17 -07:00
Bhadram Varka
0417da8260 osi: dma: compile out not required code for Safety QNX 
Bug 200770328

Change-Id: I8ee51c89954b47ceff5e261b6a2d8cc6b3f16f36
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2735897
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-08-06 05:04:20 -07:00
Narayan Reddy
f971d40513 osi: core: skip out not required code for Safety QNX 
Bug 3701869

Change-Id: Ic1f676708ff6e3faf7dbed09f0e7048448252e57
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2739627
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Bhadram Varka <vbhadram@nvidia.com>
 2022-08-06 05:04:15 -07:00
Sanath Kumar Gampa
aedaf1db80 osi: macsec API cleanup 
Bug 3709820

Change-Id: I935ca2d373bea1b7d8b15f790ffc3719fa9d0881
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2738227
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-26 10:06:20 -07:00
Narayan Reddy
be51977e02 osi: core: combine config_fw_err_pkts 
Bug 3701869

Change-Id: I5a0fe6e24d8aa69054a18f927d7135552482e8b9
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2739131
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-07-13 16:28:15 -07:00
Bhadram Varka
dea34fa933 osi: core: common poll_for_swr 
Combine MGBE/EQOS HW level functions into single function.

Bug 3701869

Change-Id: I02c4881ec95cc5637867d68e560f4790c3548737
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2732106
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-13 16:27:31 -07:00
Bhadram Varka
ce582ae644 osi: dma: combine init_dma_channel 
This change combines EQOS and MGBE init into
single function and also removes the safety
registers validation.

Bug 200770328

Change-Id: I75b575a53318b10770b40d76e209b6f6aa9bbead
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2737141
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-11 07:29:47 -07:00
Bhadram Varka
c91c65bb13 osi: dma: combine rx_buf_len 
Bug 200770328

Change-Id: I573462275d13eba1417203eb44606913b7885552
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2736236
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-11 07:29:43 -07:00
Bhadram Varka
bbc86f54f6 osi: dma: combine stop_dma 
Bug 200770328

Change-Id: I7ecf219ce16ca9bbdde1c5301eaa8accb105e048
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2734404
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-11 07:29:34 -07:00
Bhadram Varka
422c7eeec1 osi: dma: combine start_dma 
Bug 200770328

Change-Id: I106acca1253dd3d03b5e032f8b0acd7484828c58
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2734346
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-11 07:29:29 -07:00
Sanath Kumar Gampa
b3d2774241 osi: macsec: fixes for misra defects 
Below are the rules addressed

Rule: MISRA_C-2012_Rule_15.5 Diff: -90
Rule: MISRA_C-2012_Rule_2.5 Diff: -34
Rule: MISRA_C-2012_Rule_8.13 Diff: -5
Rule: MISRA_C-2012_Rule_8.6 Diff: -1

Rule: CERT_INT31-C Diff: -2

Bug 3691236

Change-Id: I0b943b7626ea47e34eee585e42f0c9b98d67a7f4
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2732627
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-08 13:37:45 -07:00
Rakesh Goyal
509dfc9329 core: delete stale TX time stamp from OSI hw queue 
Issue: In corner case TX TS form hardware in OSI list,
not claimed by OSD which lead to stale time at OSI.

Fix: if there is no timestamp read from OSD in last
2 seconds, remove that time stamp from OSI list

Bug 3620425

Change-Id: I0a77cfe716aa13ddf49bdd32f56fb49b74b9d265
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2731974
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-07 07:33:25 -07:00
Narayan Reddy
21b6f6aeb9 osi: core: Fix MISRA issues 
Fixed straight forward MISRA issues

===== DIFF ======
Total misra violation count changed by -319
Rule: MISRA_C-2012_Directive_4.4 Diff: -3
Rule: MISRA_C-2012_Directive_4.6 Diff: -32
Rule: MISRA_C-2012_Directive_4.9 Diff: 3
Rule: MISRA_C-2012_Rule_10.1 Diff: -4
Rule: MISRA_C-2012_Rule_10.3 Diff: -2
Rule: MISRA_C-2012_Rule_10.4 Diff: -21
Rule: MISRA_C-2012_Rule_11.1 Diff: -20
Rule: MISRA_C-2012_Rule_12.1 Diff: -74
Rule: MISRA_C-2012_Rule_15.5 Diff: 1
Rule: MISRA_C-2012_Rule_15.7 Diff: -2
Rule: MISRA_C-2012_Rule_16.1 Diff: -1
Rule: MISRA_C-2012_Rule_16.3 Diff: -1
Rule: MISRA_C-2012_Rule_17.7 Diff: -5
Rule: MISRA_C-2012_Rule_2.5 Diff: -157
Rule: MISRA_C-2012_Rule_8.6 Diff: -1
Rule: Total Diff: -319

JIRA NET-96
Bug 3695218

Change-Id: I221f95aaf23e9214fde21632b68425b705552752
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2735077
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-06 02:37:19 -07:00
Sanath Kumar Gampa
e316212c0c osi: macsec: Update the sak len to 256 
Bug 3673435

Change-Id: I841a9d631ff1b186f1a59e29d26822698b6e6e3d
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2730246
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-06-23 18:13:17 -07:00
Bhadram Varka
6f287777f1 osi: core: support for suspend/resume IOCTL's 
Issue: While ethernet going into suspend all registers
of controllers saved through save_registers IOCTL and
same will be restored during resume. Register restoring
without following sequence will lead to multiple issues.

Fix: For every dynamic configuration save the input
parameters and use the same parameters through API's
to restore the controller configuration. API approach
will follow the specific sequence for programming the
controller registers.

Bug 3665476

Change-Id: Ia31303daf0ba5c78f3eb5cd2706a1ce420536539
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2662333
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-06-06 05:51:24 -07:00
Om Prakash Singh
44b2f25bfa ivc: add change to support diag interface 
Add below IVC commands that will be use by nvethmgr
for diag test:
 nvethmgr_get_status
 nvethmgr_verify_ts
 nvethmgr_get_avb_perf

Bug 3620612
Change-Id: I900e97e12988035648b86fe2e8becaa6f312b256
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2709692
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-06-01 11:30:45 -07:00
Bhadram Varka
49097d2565 osi: dma: remove unused functions 
Remove below functions which are not used.
osi_enable_chan_tx_intr
osi_disable_chan_tx_intr
osi_disable_chan_rx_intr
osi_enable_chan_rx_intr

Bug 3503523

Change-Id: I1b414c3d763922d3d87b29516de8d0bdc0ac5526
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2714137
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-05-18 09:12:58 -07:00
Om Prakash Singh
6bdbdb32c6 osi: dma/core: add interface to configure debug interrupt 
add interface to configure debug related interrupt

Bug 3600647
Change-Id: Iae43ceb441254b89a5b32ef9441ce42fca812e49
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2703337
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-05-16 17:41:38 -07:00
Bhadram Varka
e8355532b8 osi: dma: interrupt enable/disable retry 
Adds retry for interrupt enable/disable and
combine interrupt handling part for EQOS/MGBE

Bug 3503523

Change-Id: Icc8b10cd786c878972e2e508ede3edb8d52addf8
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2652907
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-05-13 00:58:30 -07:00
Bhadram Varka
1f4753bbb3 osi: dma: Support for variable Tx/Rx ring length 
o Adds support for variable Tx/Rx ring length
o Default ring size 1K used if ring size passed
from OSD is zero.

Bug 3489814

Change-Id: I9c57b8d9e0c424bf39633998e0845fc97975de8f
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2652960
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-05-12 00:22:13 -07:00
Nagaraj Annaiah
bdc90d7ddc osi core: Fix macsec and eqos compiler warnings for HVRTOS 
Issue:
1. conversion to ‘nveu16_t {aka short unsigned int}’ from
‘unsigned int’ may alter its value.
2. mac_tcr may be used uninitialized in this function
3. Explicitly assigning value of variable of type 'nveu32_t' (aka
'unsigned int') to itself - mac_tcr |= mac_tcr;

Fix:
1. Add Typecast before conversion.
2. init mac_tcr to zero
3. Remove unused get_rx_err_stats function.
4. Remove mac_tcr from default.

Bug 3562777

Change-Id: I9030bf73d13ffd1d848266301a1df97144eaa391
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2707197
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-05-09 15:46:39 -07:00
Hareesh Kesireddy
ede22ef36d osi: remove extra args for tx complete callback 
Dma phy address, virtual address and packet length can be
obtained from tx swcx structure. Hence passing
pointer to tx swcx is sufficient. In future, if more information
from osi is needed, it can be embedded into tx swcx itself rather than
adding more arguments to osd tx complete call back.

Bug 3576506

Change-Id: I061ea27cd1b4d68c19f3e9d95a247505c511ce0c
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2700341
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-04-30 06:15:57 -07:00
Sanath Kumar Gampa
62917832dc osi:macsec reduce complexity of MACSEC APIs 
Issue: Complexity of OSI APIs cannot be greater than 10

Fix: Split the functionality of complex APIs to multiple APIs.
Added De-oxygen comments as well for macsec osi APIs

Bug 3460422

Change-Id: I2383904d8581efa54a8d2ec2f85a50cb12b22e89
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2688990
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-04-27 20:18:14 -07:00
Sanath Kumar Gampa
437680030d osi:macsec: Fix MISRA defects in QNX OSD 
Dependent change made in osi to fix a misra defect in QNX OSD

Bug 3598679

Change-Id: Ie6b48a6d1cb8d34b00c437cc3b57971ad447fa3b
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2695627
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-26 04:07:19 -07:00
Bibhay Ranjan
4fae8741fb nvethernetrm: fix code defects 
Issue: SPARSE errors
Fix: Fix code as per the guidelines in the errors

Bug 3568991

Change-Id: If52bf7d5b3e8d4ca10a254e802ee5257a8816633
Signed-off-by: Bibhay Ranjan <bibhayr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2688520
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-21 15:53:24 -07:00
Nagaraj Annaiah
221989d875 osi core: Fix compiler warnings for HVRTOS 
Issue: Unused variables are treated as errors with HVRTOS compiler.

Fix:
1. Add unused attributes macro for unused function arguments.
2. Fix typecast errors.
3. Add flag to check if ethernet server status, this is needed to
   skip check for function pointer validation.

Bug 3562777

Change-Id: I0a4a36fb330c580d1879f46304842c610e62316c
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670097
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-21 15:52:01 -07:00
Sanath Kumar Gampa
70fdb56a05 osi:macsec: Separate lut_status for each IP 
Issue: If macsec is created on EQOS and then created on MGBE, we are
over writing the lut_status of EQOS with MGBE lut_status.

Fix: Create different lut_status structure in osi_core so that each
IP will have its own lut_status structure.

Bug 3587231

Change-Id: I826c3d210ed18350140f1cbcb41b748550f92844
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2690839
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-04-15 04:29:14 -07:00
Sanath Kumar Gampa
37ab92517f osi:macsec: Fix osi macsec Misra/coverity issues 
Issue: Found aroung 900 MISRA?COVERITY defects on
OSI MACSEC changes

Fix: Fixed the defects by making minor changes without
impacting the functionality

Removed calling poll_for_dbg_buf_update, poll_for_kt_update
and poll_for_lut_update before lut_write as we are anyhow
polling after the lut_write

Bug 3460422

Change-Id: Ib33e8188cd90472b851732f0936c3e29142bb4a3
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2618714
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-04-11 13:17:05 -07:00
Om Prakash Singh
65f78eba09 osi: core: add support for HSI 
1) Add OSI IOCTL to enable HSI feature at runtime
2) Enable LIC interrupt for Correctable, Uncorrectable and
   Parity error
3) Program register to enable safety feature

Bug 3543410

Change-Id: I8a9f33bab72eb37e8aa64c16c610be6e5271c7f8
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670989
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-09 16:26:37 -07:00
Sanath Kumar Gampa
6dc6e28282 osi:macsec:Change to update MACSEC MTU 
Issue: If MTU is increased after Supplicant is initialized
we are not updating the MACSEC MTU so the frames will get
dropped as the MACSEC MTU is lesser than the frames received

Fix: Changes to update the MACSEC MTU along with MAC MTU

Bug 3577143

Change-Id: Iff61099ff2a9ae1f6fe6e48948d842604fd9e2c4
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2685281
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-07 03:18:33 -07:00
Sanath Kumar Gampa
92924602ba osi:macsec: Address SC over-writing issue 
Issue: In multi VM use case if multiple SCs are added using supplicants
Then we may over-write an exisitng SC if we stop and start the first
supplicant

Fix: Before adding an SC find the vacant SC slot

Bug 3522740

Change-Id: Ic10f7a542a01328876b0103c34cc1115bfd426b5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2675003
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-03-09 21:04:38 -08:00
Bhadram Varka
f65faa73f2 osi: dma: Define macro for DMA TX max buffer size 
Bug 3528173

Change-Id: If7152ec75bcf21d820cd68c3aff31e3c6aa8ae6b
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2675628
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-03-02 18:05:00 -08:00
Rakesh Goyal
288c525a36 nvethenetrm: core: SW WAR implementation for switching of Gates 
Issue: switching of Gates did not happen for
intermediate cycles when CTR is
less than GCL execution time

Fix: SW WAR as per recommendation.
1) At the programming time make sure
  (CTR - total TI) should be 0 or more than
  8PTP clock time.
2) Switching to New List
   check for following
   Old BTR + n(CTR) - New GCL list's BTR >= 8PTP or
   New GCL list's BTR – (Old BTR + n(CTR)) >= 8PTP

Bug 200724911

Change-Id: I19127a134655a66bb66d025f964b85afc6c23c2e
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2622942
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-02-28 10:49:29 -08:00
Gaurav Asati
85da4dbc4d osi: dma: update tx and rx completion API's. 
- Add tx and rx completion API's with
  failure return value.

JIRA T23XMGBE-443

Change-Id: Ib6aa3b559f1356e9285f8d4cc129abc049884342
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2618556
(cherry picked from commit 6bd8b7fe13f258928bb81ebe22c30fe5b51688c0)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2658600
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-02-27 18:09:02 -08:00
Gaurav Asati
f1125b7063 osi: update API headers 
Use @usage instead of @note and group all classification and API
group details under @usage.

Bug 3350640

Change-Id: If77cfd76519f17427b95a2300ad722dc6f83f518
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2587106
(cherry picked from commit 0002e2d0b2cf85811b09e8c7157dbd777c8fc117)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2657079
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-02-27 18:08:46 -08:00
Gaurav Asati
9a6c5dbc4b osi: Add Async-sync details to API header 
Issue:
Async-sync details to API header is needed.

Fix:
Add Async-sync details to API header and remove duplicate Thread
details.

Bug 3350640

Change-Id: I0838e53951389c9fa408323324cedba0268f4706
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2572939
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
(cherry picked from commit 8acef05c924ed72e256e792a8cd623a221494287)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2657054
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-02-27 18:08:35 -08:00