mirror of
git://nv-tegra.nvidia.com/kernel/nvethernetrm.git
synced 2025-12-22 09:12:10 +03:00
606235ffb2
Issue: Currentlt MTL TXFIFO is divided by 10 for MGBE since there are 10 MTL TX queues but in Linux maximum 8 channels and in QNX maximum two channels can be used. On TX, DMA channel to MTL queue is static mapping so two queues memory in Linux and 8 queues memory in QNX is not getting used. Fix: Divide the TXFIFO size based on enabled DMA channels. Bug 4443026 Bug 4283087 Bug 4266776 Change-Id: I92ac5da644f2df05503ac44979e0d16079cf9231 Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3009823 Reviewed-by: Ashutosh Jha <ajha@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
298 lines
8.1 KiB
C
298 lines
8.1 KiB
C
/*
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* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef INCLUDED_OSI_COMMON_H
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#define INCLUDED_OSI_COMMON_H
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#include <nvethernet_type.h>
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/**
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* @addtogroup FC Flow Control Threshold Macros
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*
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* @brief These bits control the threshold (fill-level of Rx queue) at which
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* the flow control is asserted or de-asserted
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* @{
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*/
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#define FULL_MINUS_1_5K ((nveu32_t)1)
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#define FULL_MINUS_16_K ((nveu32_t)30)
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#define FULL_MINUS_32_K ((nveu32_t)62)
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/** @} */
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/**
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* @addtogroup OSI-Helper OSI Helper MACROS
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* @{
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*/
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#define OSI_UNLOCKED 0x0U
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#define OSI_LOCKED 0x1U
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#define OSI_NSEC_PER_SEC 1000000000ULL
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#ifndef OSI_STRIPPED_LIB
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#define OSI_MAX_RX_COALESCE_USEC 1020U
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#define OSI_EQOS_MIN_RX_COALESCE_USEC 5U
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#define OSI_MGBE_MIN_RX_COALESCE_USEC 6U
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#define OSI_MIN_RX_COALESCE_FRAMES 1U
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#define OSI_MAX_TX_COALESCE_USEC 1020U
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#define OSI_MIN_TX_COALESCE_USEC 32U
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#define OSI_MIN_TX_COALESCE_FRAMES 1U
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#define OSI_PAUSE_FRAMES_DISABLE 0U
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#define OSI_PAUSE_FRAMES_ENABLE 1U
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#endif /* !OSI_STRIPPED_LIB */
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/* Compiler hints for branch prediction */
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#define osi_unlikely(x) __builtin_expect(!!(x), 0)
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/** @} */
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/**
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* @addtogroup Helper MACROS
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*
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* @brief EQOS generic helper MACROS.
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* @{
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*/
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#define OSI_MAX_24BITS 0xFFFFFFU
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#define OSI_MAX_28BITS 0xFFFFFFFU
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#define OSI_MAX_32BITS 0xFFFFFFFFU
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#define OSI_MASK_16BITS 0xFFFFU
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#define OSI_MASK_20BITS 0xFFFFFU
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#define OSI_MASK_24BITS 0xFFFFFFU
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#define OSI_GCL_SIZE_64 64U
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#define OSI_GCL_SIZE_128 128U
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#define OSI_GCL_SIZE_512 512U
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#define OSI_GCL_SIZE_1024 1024U
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/** @} */
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#ifndef OSI_STRIPPED_LIB
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/**
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* @addtogroup Helper MACROS
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*
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* @brief EQOS generic helper MACROS.
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* @{
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*/
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#define OSI_PTP_REQ_CLK_FREQ 250000000U
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#define OSI_FLOW_CTRL_DISABLE 0U
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#define OSI_ADDRESS_32BIT 0
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#define OSI_ADDRESS_40BIT 1
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#define OSI_ADDRESS_48BIT 2
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/** @ } */
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/**
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* @addtogroup - LPI-Timers LPI configuration macros
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*
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* @brief LPI timers and config register field masks.
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* @{
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*/
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/* LPI LS timer - minimum time (in milliseconds) for which the link status from
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* PHY should be up before the LPI pattern can be transmitted to the PHY.
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* Default 1sec.
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*/
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#define OSI_DEFAULT_LPI_LS_TIMER (nveu32_t)1000
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#define OSI_LPI_LS_TIMER_MASK 0x3FFU
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#define OSI_LPI_LS_TIMER_SHIFT 16U
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/* LPI TW timer - minimum time (in microseconds) for which MAC wait after it
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* stops transmitting LPI pattern before resuming normal tx.
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* Default 21us
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*/
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#define OSI_DEFAULT_LPI_TW_TIMER 0x15U
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#define OSI_LPI_TW_TIMER_MASK 0xFFFFU
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/* LPI entry timer - Time in microseconds that MAC will wait to enter LPI mode
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* after all tx is complete.
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* Default 1sec.
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*/
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#define OSI_LPI_ENTRY_TIMER_MASK 0xFFFF8U
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/* LPI entry timer - Time in microseconds that MAC will wait to enter LPI mode
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* after all tx is complete. Default 1sec.
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*/
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#define OSI_DEFAULT_TX_LPI_TIMER 0xF4240U
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/* Max Tx LPI timer (in usecs) based on the timer value field length in HW
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* MAC_LPI_ENTRY_TIMER register */
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#define OSI_MAX_TX_LPI_TIMER 0xFFFF8U
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/* Min Tx LPI timer (in usecs) based on the timer value field length in HW
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* MAC_LPI_ENTRY_TIMER register */
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#define OSI_MIN_TX_LPI_TIMER 0x8U
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/* Time in 1 microseconds tic counter used as reference for all LPI timers.
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* It is clock rate of CSR slave port (APB clock[eqos_pclk] in eqos) minus 1
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* Current eqos_pclk is 204MHz
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*/
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#define OSI_LPI_1US_TIC_COUNTER_DEFAULT 0xCBU
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#define OSI_LPI_1US_TIC_COUNTER_MASK 0xFFFU
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/** @} */
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#endif /* !OSI_STRIPPED_LIB */
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#define OSI_POLL_COUNT 1000U
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#ifndef UINT_MAX
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#define UINT_MAX (~0U)
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#endif
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#ifndef INT_MAX
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#define INT_MAX (0x7FFFFFFF)
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#ifndef OSI_LLONG_MAX
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#define OSI_LLONG_MAX (0x7FFFFFFFFFFFFFFF)
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#endif
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#endif
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/** @} */
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/**
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* @addtogroup Generic helper MACROS
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*
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* @brief These are Generic helper macros used at various places.
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* @{
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*/
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#define OSI_UCHAR_MAX (0xFFU)
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/* Logging defines */
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/* log levels */
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#define OSI_LOG_INFO 1U
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#ifndef OSI_STRIPPED_LIB
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#define OSI_LOG_WARN 2U
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#endif /* OSI_STRIPPED_LIB */
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#define OSI_LOG_ERR 3U
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/* Error types */
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#define OSI_LOG_ARG_OUTOFBOUND 1U
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#define OSI_LOG_ARG_INVALID 2U
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#define OSI_LOG_ARG_HW_FAIL 4U
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#define OSI_LOG_ARG_OPNOTSUPP 3U
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/* Default maximum Giant Packet Size Limit is 16K */
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#define OSI_MAX_MTU_SIZE 16383U
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#ifdef UPDATED_PAD_CAL
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/* MAC Tx/Rx Idle retry and delay count */
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#define OSI_TXRX_IDLE_RETRY 5000U
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#define OSI_DELAY_COUNT 10U
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#endif
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#define EQOS_DMA_CHX_STATUS(x) ((0x0080U * (x)) + 0x1160U)
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#define MGBE_DMA_CHX_STATUS(x) ((0x0080U * (x)) + 0x3160U)
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#define EQOS_DMA_CHX_IER(x) ((0x0080U * (x)) + 0x1134U)
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#define MGBE_MTL_CHX_TX_OP_MODE(x) ((0x0080U * (x)) + 0x1100U)
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/* FIXME add logic based on HW version */
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#define OSI_EQOS_MAX_NUM_CHANS 8U
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#define OSI_EQOS_MAX_NUM_QUEUES 8U
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#define OSI_MGBE_MAX_L3_L4_FILTER 8U
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#define OSI_MGBE_MAX_NUM_CHANS 10U
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#define OSI_MGBE_MAX_NUM_QUEUES 10U
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#define OSI_EQOS_XP_MAX_CHANS 4U
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/* MACSEC max SC's supported 16*/
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#define OSI_MACSEC_SC_INDEX_MAX 16
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#ifndef OSI_STRIPPED_LIB
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/* HW supports 8 Hash table regs, but eqos_validate_core_regs only checks 4 */
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#define OSI_EQOS_MAX_HASH_REGS 4U
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#endif /* OSI_STRIPPED_LIB */
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#define MAC_VERSION 0x110
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#define MAC_VERSION_SNVER_MASK 0x7FU
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#define OSI_MAC_HW_EQOS 0U
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#define OSI_MAC_HW_MGBE 1U
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#define OSI_MAX_VM_IRQS 5U
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#define OSI_NULL ((void *)0)
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#define OSI_ENABLE 1U
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#define OSI_NONE 0U
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#define OSI_NONE_SIGNED 0
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#define OSI_DISABLE 0U
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#define OSI_H_DISABLE 0x10101010U
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#define OSI_H_ENABLE (~OSI_H_DISABLE)
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#define OSI_BIT(nr) ((nveu32_t)1 << (nr))
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#ifndef OSI_STRIPPED_LIB
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#define OSI_MGBE_MAC_3_00 0x30U
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#define OSI_EQOS_MAC_4_10 0x41U
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#define OSI_EQOS_MAC_5_10 0x51U
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#define OSI_MGBE_MAC_4_00 0x40U
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#endif /* OSI_STRIPPED_LIB */
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#define OSI_EQOS_MAC_5_00 0x50U
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#define OSI_EQOS_MAC_5_30 0x53U
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#define OSI_MGBE_MAC_3_10 0x31U
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#define OSI_MAX_VM_IRQS 5U
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#ifndef OSI_STRIPPED_LIB
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#define OSI_HASH_FILTER_MODE 1U
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#define OSI_L4_FILTER_TCP 0U
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#define OSI_L4_FILTER_UDP 1U
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#define OSI_PERFECT_FILTER_MODE 0U
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#define OSI_INVALID_CHAN_NUM 0xFFU
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#endif /* OSI_STRIPPED_LIB */
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/** @} */
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/**
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* @addtogroup OSI-DEBUG helper macros
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*
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* @brief OSI debug type macros
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* @{
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*/
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#ifdef OSI_DEBUG
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#define OSI_DEBUG_TYPE_DESC 1U
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#define OSI_DEBUG_TYPE_REG 2U
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#define OSI_DEBUG_TYPE_STRUCTS 3U
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#endif /* OSI_DEBUG */
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/** @} */
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/**
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* @brief unused function attribute
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*/
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#define OSI_UNUSED __attribute__((__unused__))
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/**
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* @brief osi_update_stats_counter - update value by increment passed
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* as parameter
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* @note
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* Algorithm:
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* - Check for boundary and return sum
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*
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* @param[in] last_value: last value of stat counter
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* @param[in] incr: increment value
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*
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* @note Input parameter should be only nveu64_t type
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*
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* @note
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* API Group:
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* - Initialization: No
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* - Run time: Yes
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* - De-initialization: No
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*
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* @retval 0 on sucess
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* @retval -1 on failure
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*/
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static inline nveu64_t osi_update_stats_counter(nveu64_t last_value,
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nveu64_t incr)
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{
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nveu64_t temp = last_value + incr;
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if (temp < last_value) {
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/* Stats overflow, so reset it to zero */
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temp = 0UL;
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}
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return temp;
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}
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#endif /* OSI_COMMON_H */
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