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4864073566
Bug 5068365 Change-Id: Ib25276760ec49685a918354c31364f23093f9558 Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3297947 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
66 lines
2.6 KiB
C
66 lines
2.6 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef INCLUDED_OSI_DMA_TXRX_H
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#define INCLUDED_OSI_DMA_TXRX_H
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/**
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* @addtogroup EQOS_Help Descriptor Helper MACROS
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*
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* @brief Helper macros for defining Tx/Rx descriptor count
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* @{
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*/
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/** EQOS Tx descriptor count */
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#define OSI_EQOS_TX_DESC_CNT 1024U
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/** EQOS Rx descriptor count */
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#define OSI_EQOS_RX_DESC_CNT 1024U
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/** MGBE Tx descriptor count */
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#define OSI_MGBE_TX_DESC_CNT 4096U
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/** MGBE Max Rx descriptor count */
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#define OSI_MGBE_MAX_RX_DESC_CNT 16384U
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/** @} */
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/* TSO Header length divisor */
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#define OSI_TSO_HDR_LEN_DIVISOR 4U
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/**
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* @addtogroup EQOS_Help1 Helper MACROS for descriptor index operations
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*
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* @brief Helper macros for incrementing or decrementing Tx/Rx descriptor index
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* @{
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*/
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/** Increment the tx descriptor index */
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#define INCR_TX_DESC_INDEX(idx, x) ((idx) = (((idx) & ((nveu32_t)0x7FFFFFFFU)) + (1U)) & ((x) - 1U))
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/** Increment the rx descriptor index */
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#define INCR_RX_DESC_INDEX(idx, x) ((idx) = (((idx) & ((nveu32_t)0x7FFFFFFFU)) + (1U)) & ((x) - 1U))
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/** Decrement the tx descriptor index */
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#define DECR_TX_DESC_INDEX(idx, x) ((idx) = (((idx) & ((nveu32_t)0x7FFFFFFFU)) - (1U)) & ((x) - 1U))
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#ifndef OSI_STRIPPED_LIB
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/** Decrement the rx descriptor index */
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#define DECR_RX_DESC_INDEX(idx, x) (((idx) & ((nveu32_t)0x7FFFFFFFU)) = ((idx) - (1U)) & ((x) - 1U))
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#endif /* !OSI_STRIPPED_LIB */
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/** @} */
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#endif /* INCLUDED_OSI_DMA_TXRX_H */
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