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016ce07cdc
Bug 3701869 Change-Id: I802497b6f973c69b994373697251964e532243f7 Signed-off-by: Narayan Reddy <narayanr@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2739139 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
77 lines
2.9 KiB
C
77 lines
2.9 KiB
C
/*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef INCLUDED_CORE_COMMON_H
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#define INCLUDED_CORE_COMMON_H
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#include "core_local.h"
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#define MTL_EST_ADDR_MASK (OSI_BIT(8) | OSI_BIT(9) | \
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OSI_BIT(10) | OSI_BIT(11) | \
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OSI_BIT(12) | OSI_BIT(13) | \
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OSI_BIT(14) | OSI_BIT(15) | \
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OSI_BIT(16) | (17U) | \
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OSI_BIT(18) | OSI_BIT(19))
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#define MTL_EST_SRWO OSI_BIT(0)
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#define MTL_EST_R1W0 OSI_BIT(1)
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#define MTL_EST_GCRR OSI_BIT(2)
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#define MTL_EST_DBGM OSI_BIT(4)
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#define MTL_EST_DBGB OSI_BIT(5)
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#define MTL_EST_ERR0 OSI_BIT(20)
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#define MTL_EST_CONTROL_EEST OSI_BIT(0)
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#define MTL_EST_STATUS_SWOL OSI_BIT(7)
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#define DMA_MODE_SWR OSI_BIT(0)
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#define MTL_QTOMR_FTQ OSI_BIT(0)
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#define MTL_RXQ_OP_MODE_FEP OSI_BIT(4)
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/**
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* @addtogroup typedef related info
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*
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* @brief typedefs that indeicates variable address and memory addr
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* @{
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*/
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struct est_read {
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/* variable pointer */
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nveu32_t *var;
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/* memory register/address offset */
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nveu32_t addr;
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};
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/** @} */
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nve32_t gcl_validate(struct osi_core_priv_data *const osi_core,
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struct osi_est_config *const est,
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const nveu32_t *btr, nveu32_t mac);
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nve32_t hw_poll_for_swr(struct osi_core_priv_data *const osi_core);
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void hw_start_mac(struct osi_core_priv_data *const osi_core);
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void hw_stop_mac(struct osi_core_priv_data *const osi_core);
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nve32_t hw_set_mode(struct osi_core_priv_data *const osi_core, const nve32_t mode);
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nve32_t hw_set_speed(struct osi_core_priv_data *const osi_core, const nve32_t speed);
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nve32_t hw_flush_mtl_tx_queue(struct osi_core_priv_data *const osi_core,
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const nveu32_t qinx);
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nve32_t hw_config_fw_err_pkts(struct osi_core_priv_data *osi_core,
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const nveu32_t qinx, const nveu32_t enable_fw_err_pkts);
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nve32_t hw_config_rxcsum_offload(struct osi_core_priv_data *const osi_core,
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nveu32_t enabled);
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#endif /* INCLUDED_CORE_COMMON_H */
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