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git://nv-tegra.nvidia.com/kernel/nvethernetrm.git
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12bdb2f1ea
Issue: 1. compilation issue: error: the frame size of 3232 bytes is larger than 2048 bytes [-Werror=frame-larger-than=] Because of increase in the value of OSI_MACSEC_SC_INDEX_MAX it resulted in increase in the size of ivc_msg_common more than 2048 bytes. 2. IVC communication breaking because IVC buffer size increased more than 2048 because of #1. WAR: Revert back to the orin value for OSI_MACSEC_SC_INDEX_MAX Bug 4687787 Change-Id: I5262cd772acf6b4275cc3f47696f0072b70916e0 Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
339 lines
9.6 KiB
C
339 lines
9.6 KiB
C
/* SPDX-License-Identifier: LicenseRef-NvidiaProprietary
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* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef INCLUDED_OSI_COMMON_H
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#define INCLUDED_OSI_COMMON_H
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#include <nvethernet_type.h>
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/**
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* @brief Maximum number of supported MAC IP types (EQOS, MGBE, MGBE_T26X)
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*/
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#define OSI_MAX_MAC_IP_TYPES 3U
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/**
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* @addtogroup FC Flow Control Threshold Macros
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*
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* @brief These bits control the threshold (fill-level of Rx queue) at which
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* the flow control is asserted or de-asserted
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* @{
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*/
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#define FULL_MINUS_1_5K ((nveu32_t)1)
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#define FULL_MINUS_16_K ((nveu32_t)30)
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#define FULL_MINUS_32_K ((nveu32_t)62)
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/** @} */
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/**
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* @addtogroup OSI-Helper OSI Helper MACROS
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* @{
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*/
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#define OSI_UNLOCKED 0x0U
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#define OSI_LOCKED 0x1U
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/** @brief Number of Nano seconds per second */
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#define OSI_NSEC_PER_SEC 1000000000ULL
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#define OSI_MGBE_MAX_RX_RIIT_NSEC 17500U
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#define OSI_MGBE_MIN_RX_RIIT_NSEC 535U
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#ifndef OSI_STRIPPED_LIB
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#define OSI_MAX_RX_COALESCE_USEC 1020U
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#define OSI_EQOS_MIN_RX_COALESCE_USEC 5U
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#define OSI_MGBE_MIN_RX_COALESCE_USEC 6U
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#define OSI_MIN_RX_COALESCE_FRAMES 1U
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#define OSI_MAX_TX_COALESCE_USEC 1020U
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#define OSI_MIN_TX_COALESCE_USEC 32U
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#define OSI_MIN_TX_COALESCE_FRAMES 1U
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#endif /* !OSI_STRIPPED_LIB */
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/* Compiler hints for branch prediction */
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#define osi_unlikely(x) __builtin_expect(!!(x), 0)
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/** @} */
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/**
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* @addtogroup FC-Helper Flow control enable/disable macros.
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* @{
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*/
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/** @brief flag to disable pause frames */
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#define OSI_PAUSE_FRAMES_DISABLE 0U
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/** @brief flag to enable pause frames */
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#define OSI_PAUSE_FRAMES_ENABLE 1U
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/** @} */
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/**
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* @addtogroup helper MACROS
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*
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* @brief EQOS generic helper MACROS.
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* @{
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*/
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#define OSI_MAX_24BITS 0xFFFFFFU
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#define OSI_MAX_28BITS 0xFFFFFFFU
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#define OSI_MAX_32BITS 0xFFFFFFFFU
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#define OSI_MASK_16BITS 0xFFFFU
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#define OSI_MASK_20BITS 0xFFFFFU
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#define OSI_MASK_24BITS 0xFFFFFFU
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#define OSI_GCL_SIZE_64 64U
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#define OSI_GCL_SIZE_128 128U
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#define OSI_GCL_SIZE_512 512U
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#define OSI_GCL_SIZE_1024 1024U
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/** @} */
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#ifndef OSI_STRIPPED_LIB
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/**
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* @addtogroup Helper MACROS
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*
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* @brief EQOS generic helper MACROS.
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* @{
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*/
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#define OSI_FLOW_CTRL_DISABLE 0U
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#define OSI_ADDRESS_32BIT 0
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#define OSI_ADDRESS_40BIT 1
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#define OSI_ADDRESS_48BIT 2
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/** @ } */
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/**
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* @addtogroup - LPI-Timers LPI configuration macros
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*
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* @brief LPI timers and config register field masks.
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* @{
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*/
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/* LPI LS timer - minimum time (in milliseconds) for which the link status from
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* PHY should be up before the LPI pattern can be transmitted to the PHY.
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* Default 1sec.
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*/
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#define OSI_DEFAULT_LPI_LS_TIMER (nveu32_t)1000
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#define OSI_LPI_LS_TIMER_MASK 0x3FFU
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#define OSI_LPI_LS_TIMER_SHIFT 16U
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/* LPI TW timer - minimum time (in microseconds) for which MAC wait after it
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* stops transmitting LPI pattern before resuming normal tx.
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* Default 21us
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*/
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#define OSI_DEFAULT_LPI_TW_TIMER 0x15U
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#define OSI_LPI_TW_TIMER_MASK 0xFFFFU
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/* LPI entry timer - Time in microseconds that MAC will wait to enter LPI mode
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* after all tx is complete.
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* Default 1sec.
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*/
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#define OSI_LPI_ENTRY_TIMER_MASK 0xFFFF8U
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/* LPI entry timer - Time in microseconds that MAC will wait to enter LPI mode
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* after all tx is complete. Default 1sec.
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*/
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#define OSI_DEFAULT_TX_LPI_TIMER 0xF4240U
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/* Max Tx LPI timer (in usecs) based on the timer value field length in HW
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* MAC_LPI_ENTRY_TIMER register */
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#define OSI_MAX_TX_LPI_TIMER 0xFFFF8U
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/* Min Tx LPI timer (in usecs) based on the timer value field length in HW
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* MAC_LPI_ENTRY_TIMER register */
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#define OSI_MIN_TX_LPI_TIMER 0x8U
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/* Time in 1 microseconds tic counter used as reference for all LPI timers.
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* It is clock rate of CSR slave port (APB clock[eqos_pclk] in eqos) minus 1
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* Current eqos_pclk is 204MHz
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*/
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#define OSI_LPI_1US_TIC_COUNTER_DEFAULT 0xCBU
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#define OSI_LPI_1US_TIC_COUNTER_MASK 0xFFFU
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/** @} */
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#endif /* !OSI_STRIPPED_LIB */
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#define OSI_PTP_REQ_CLK_FREQ 250000000U
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#define OSI_POLL_COUNT 1000U
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#ifndef UINT_MAX
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/** Max value of uint */
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#define UINT_MAX (0xFFFFFFFFU)
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#endif
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#ifndef INT_MAX
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#define INT_MAX (0x7FFFFFFF)
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#ifndef OSI_LLONG_MAX
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#define OSI_LLONG_MAX (0x7FFFFFFFFFFFFFFF)
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#endif
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#endif
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/** @} */
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/**
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* @addtogroup Generic helper MACROS
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*
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* @brief These are Generic helper macros used at various places.
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* @{
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*/
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#define OSI_UCHAR_MAX (0xFFU)
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/* Logging defines */
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/* log levels */
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#define OSI_LOG_INFO 1U
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#ifndef OSI_STRIPPED_LIB
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#define OSI_LOG_WARN 2U
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#endif /* OSI_STRIPPED_LIB */
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#define OSI_LOG_ERR 3U
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/* Error types */
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#define OSI_LOG_ARG_OUTOFBOUND 1U
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#define OSI_LOG_ARG_INVALID 2U
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#define OSI_LOG_ARG_HW_FAIL 4U
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#define OSI_LOG_ARG_OPNOTSUPP 3U
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/** Default maximum Giant Packet Size Limit is 16383 */
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#define OSI_MAX_MTU_SIZE 16383U
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/* MAC Tx/Rx Idle retry and delay count */
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#define OSI_TXRX_IDLE_RETRY 5000U
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#define OSI_DELAY_COUNT 10U
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#define EQOS_DMA_CHX_STATUS(x) ((0x0080U * (x)) + 0x1160U)
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#define MGBE_DMA_CHX_STATUS(x) ((0x0080U * (x)) + 0x3160U)
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#define EQOS_DMA_CHX_IER(x) ((0x0080U * (x)) + 0x1134U)
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/* FIXME add logic based on HW version */
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/**
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* @brief Maximum number of channels in EQOS
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*/
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#define OSI_EQOS_MAX_NUM_CHANS 8U
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/** @brief Maximum number of queues in EQOS */
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#define OSI_EQOS_MAX_NUM_QUEUES 8U
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/** @brief Maximum number of L3L4 filters supported */
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#define OSI_MGBE_MAX_L3_L4_FILTER 8U
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/** @brief Maximum number of L3L4 filters supported for T264 */
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#define OSI_MGBE_MAX_L3_L4_FILTER_T264 48U
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/**
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* @brief Maximum number of channels in MGBE
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*/
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//TBD: T264, NET05 supports only 20 VDMA, change to 48 later
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#define OSI_MGBE_MAX_NUM_CHANS 20U
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#define OSI_MGBE_T23X_MAX_NUM_CHANS 10U
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/**
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* @brief Maximum number of PDMA channels in MGBE
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*/
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#define OSI_MGBE_MAX_NUM_PDMA_CHANS 10U
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/** @brief Maximum number of queues in MGBE */
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#define OSI_MGBE_MAX_NUM_QUEUES 10U
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#define OSI_EQOS_XP_MAX_CHANS 4U
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/* max riit DT configs for supported speeds */
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#define OSI_MGBE_MAX_NUM_RIIT 4U
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/**
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* @brief Maximum number of Secure Channels supported
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*/
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#define OSI_MACSEC_SC_INDEX_MAX 16
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#ifndef OSI_STRIPPED_LIB
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/* HW supports 8 Hash table regs, but eqos_validate_core_regs only checks 4 */
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#define OSI_EQOS_MAX_HASH_REGS 4U
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#endif /* OSI_STRIPPED_LIB */
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#define MAC_VERSION 0x110
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#define MAC_VERSION_SNVER_MASK 0x7FU
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/** @brief flag indicating EQOS MAC */
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#define OSI_MAC_HW_EQOS 0U
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/** @brief flag indicating MGBE MAC */
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#define OSI_MAC_HW_MGBE 1U
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/** @brief flag indicating MGBE MAC on T26X */
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#define OSI_MAC_HW_MGBE_T26X 2U
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/** MAC version type for EQOS version previous to 5.30 */
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#define MAC_CORE_VER_TYPE_EQOS 0U
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/** MAC version type for EQOS version 5.30 */
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#define MAC_CORE_VER_TYPE_EQOS_5_30 1U
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/** MAC version type for MGBE IP */
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#define MAC_CORE_VER_TYPE_MGBE 2U
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/** MAC version type for T26x EQOS version 5.40 */
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#define MAC_CORE_VER_TYPE_EQOS_5_40 3U
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#define OSI_NULL ((void *)0)
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/** Enable Flag */
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#define OSI_ENABLE 1U
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#define OSI_NONE 0U
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#define OSI_NONE_SIGNED 0
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/** Disable Flag */
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#define OSI_DISABLE 0U
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#define OSI_H_DISABLE 0x10101010U
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#define OSI_H_ENABLE (~OSI_H_DISABLE)
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#define OSI_BIT(nr) ((nveu32_t)1 << (((nveu32_t)nr) & 0x1FU))
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#define OSI_BIT_64(nr) ((nveu64_t)1 << (nr))
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#ifndef OSI_STRIPPED_LIB
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#define OSI_MGBE_MAC_3_00 0x30U
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#define OSI_EQOS_MAC_4_10 0x41U
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#define OSI_EQOS_MAC_5_10 0x51U
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#define OSI_MGBE_MAC_4_00 0x40U
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#endif /* OSI_STRIPPED_LIB */
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/** @brief EQOS MAC version before Orin */
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#define OSI_EQOS_MAC_5_00 0x50U
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/** @brief EQOS MAC version Orin */
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#define OSI_EQOS_MAC_5_30 0x53U
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#define OSI_EQOS_MAC_5_40 0x54U
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/** @brief MGBE MAC version Orin */
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#define OSI_MGBE_MAC_3_10 0x31U
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#define OSI_MGBE_MAC_3_20 0x32U
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#define OSI_MGBE_MAC_4_20 0x42U
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/**
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* @brief Maximum number of VM IRQs
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*/
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#define OSI_MAX_VM_IRQS 5U
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#ifndef OSI_STRIPPED_LIB
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#define OSI_HASH_FILTER_MODE 1U
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#define OSI_L4_FILTER_TCP 0U
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#define OSI_L4_FILTER_UDP 1U
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#define OSI_PERFECT_FILTER_MODE 0U
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#define OSI_INVALID_CHAN_NUM 0xFFU
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#endif /* OSI_STRIPPED_LIB */
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/** @} */
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/**
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* @addtogroup OSI-DEBUG helper macros
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*
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* @brief OSI debug type macros
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* @{
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*/
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#ifdef OSI_DEBUG
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#define OSI_DEBUG_TYPE_DESC 1U
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#define OSI_DEBUG_TYPE_REG 2U
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#define OSI_DEBUG_TYPE_STRUCTS 3U
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#endif /* OSI_DEBUG */
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/** @} */
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/**
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* @brief unused function attribute
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*/
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#define OSI_UNUSED __attribute__((__unused__))
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/** @brief macro for 1 micro second delay */
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#define OSI_DELAY_1US 1U
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/**
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* @brief OSI PDMA to VDMA mapping data
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*/
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struct osi_pdma_vdma_data {
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/** PDMA channel */
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nveu32_t pdma_chan;
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/** Number of VDMA channels */
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nveu32_t num_vdma_chans;
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/** Array of VDMA channel list */
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nveu32_t vdma_chans[OSI_MGBE_MAX_NUM_CHANS];
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};
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#endif /* OSI_COMMON_H */
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