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git://nv-tegra.nvidia.com/kernel/nvethernetrm.git
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4864073566
Bug 5068365 Change-Id: Ib25276760ec49685a918354c31364f23093f9558 Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3297947 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
109 lines
3.8 KiB
C
109 lines
3.8 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef INCLUDED_NVETHERNETRM_L3L4_H
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#define INCLUDED_NVETHERNETRM_L3L4_H
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#include <nvethernet_type.h>
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/** helper macro for enable */
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#define OSI_L3L4_ENABLE (1U)
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/** helper macro to disable */
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#define OSI_L3L4_DISABLE (0U)
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/** helper macro for enable */
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#define OSI_TRUE (OSI_L3L4_ENABLE)
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/** helper macro to disable */
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#define OSI_FALSE (OSI_L3L4_DISABLE)
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/**
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* @brief L3/L4 filter function dependent parameter
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*/
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struct osi_l3_l4_filter {
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struct {
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#ifndef OSI_STRIPPED_LIB
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/** udp (OSI_L3L4_ENABLE) or tcp (OSI_L3L4_DISABLE) */
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nveu32_t is_udp;
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/** ipv6 (OSI_L3L4_ENABLE) or ipv4 (OSI_L3L4_DISABLE) */
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nveu32_t is_ipv6;
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/** match combined L3, L4 filters (OSI_TRUE) or ignore L3,L4
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* combined filter match (OSI_FALSE) */
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nveu32_t is_l3l4_match_en;
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#endif /* !OSI_STRIPPED_LIB */
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struct {
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/** ipv4 address
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* valid values from 0 to 0xFF in each array element */
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nveu8_t ip4_addr[4];
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#ifndef OSI_STRIPPED_LIB
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/** ipv6 address */
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nveu16_t ip6_addr[8];
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/** Port number */
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nveu16_t port_no;
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/** addr match enable (OSI_L3L4_ENABLE) or disable (OSI_L3L4_DISABLE) */
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nveu32_t addr_match;
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/** perfect(OSI_L3L4_DISABLE) or inverse(OSI_L3L4_ENABLE)
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* match for address */
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nveu32_t addr_match_inv;
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/** port match enable (OSI_L3L4_ENABLE) or disable (OSI_L3L4_DISABLE) */
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nveu32_t port_match;
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/** perfect(OSI_L3L4_DISABLE) or inverse(OSI_L3L4_ENABLE) match for port */
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nveu32_t port_match_inv;
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#endif /* !OSI_STRIPPED_LIB */
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} dst;
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#ifndef OSI_STRIPPED_LIB
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/** ip address and port information */
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struct {
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/** ipv4 address */
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nveu8_t ip4_addr[4];
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/** ipv6 address */
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nveu16_t ip6_addr[8];
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/** Port number */
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nveu16_t port_no;
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/** addr match enable (OSI_L3L4_ENABLE) or disable (OSI_L3L4_DISABLE) */
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nveu32_t addr_match;
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/** perfect(OSI_L3L4_DISABLE) or inverse(OSI_L3L4_ENABLE)
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* match for address */
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nveu32_t addr_match_inv;
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/** port match enable (OSI_L3L4_ENABLE) or disable (OSI_L3L4_DISABLE) */
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nveu32_t port_match;
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/** perfect(OSI_L3L4_DISABLE) or inverse(OSI_L3L4_ENABLE) match for port */
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nveu32_t port_match_inv;
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} src;
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#endif /* !OSI_STRIPPED_LIB */
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} data;
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#ifndef OSI_STRIPPED_LIB
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/** Represents whether DMA routing enabled (OSI_L3L4_ENABLE) or not (OSI_L3L4_DISABLE) */
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nveu32_t dma_routing_enable;
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#endif /* !OSI_STRIPPED_LIB */
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/** DMA channel number if routing enabled
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* valid values are from 0 to NVETHERNETRM_PIF$OSI_EQOS_MAX_NUM_CHANS for EQOS
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* and 0 to NVETHERNETRM_PIF$OSI_MGBE_MAX_NUM_CHANS for MGBE */
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nveu32_t dma_chan;
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/** filter enable (OSI_L3L4_ENABLE) or disable (OSI_L3L4_DISABLE) */
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nveu32_t filter_enb_dis;
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};
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#endif /* INCLUDED_NVETHERNETRM_L3L4_H */
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