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git://nv-tegra.nvidia.com/kernel/nvethernetrm.git
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4864073566
Bug 5068365 Change-Id: Ib25276760ec49685a918354c31364f23093f9558 Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3297947 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
145 lines
4.5 KiB
C
145 lines
4.5 KiB
C
// SPDX-License-Identifier: MIT
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/* SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef OSI_STRIPPED_LIB
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#include "dma_local.h"
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#include "eqos_dma.h"
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/**
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* @brief eqos_config_slot - Configure slot Checking for DMA channel
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*
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* @note
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* Algorithm:
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* - Set/Reset the slot function of DMA channel based on given inputs
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*
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* @param[in] osi_dma: OSI DMA private data structure.
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* @param[in] chan: DMA channel number to enable slot function
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* @param[in] set: flag for set/reset with value OSI_ENABLE/OSI_DISABLE
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* @param[in] interval: slot interval from 0usec to 4095usec
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*
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* @pre
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* - MAC should be init and started. see osi_start_mac()
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* - OSD should be initialized
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*
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* @note
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* API Group:
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* - Initialization: Yes
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* - Run time: Yes
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* - De-initialization: No
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*/
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static void eqos_config_slot(struct osi_dma_priv_data *osi_dma,
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nveu32_t chan,
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nveu32_t set,
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nveu32_t interval)
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{
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nveu32_t value;
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nveu32_t intr;
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#if 0
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CHECK_CHAN_BOUND(chan);
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#endif
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if (set == OSI_ENABLE) {
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/* Program SLOT CTRL register SIV and set ESC bit */
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value = osi_dma_readl((nveu8_t *)osi_dma->base +
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EQOS_DMA_CHX_SLOT_CTRL(chan));
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value &= ~EQOS_DMA_CHX_SLOT_SIV_MASK;
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/* remove overflow bits of interval */
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intr = interval & EQOS_DMA_CHX_SLOT_SIV_MASK;
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value |= (intr << EQOS_DMA_CHX_SLOT_SIV_SHIFT);
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/* Set ESC bit */
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value |= EQOS_DMA_CHX_SLOT_ESC;
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osi_dma_writel(value, (nveu8_t *)osi_dma->base +
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EQOS_DMA_CHX_SLOT_CTRL(chan));
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} else {
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/* Clear ESC bit of SLOT CTRL register */
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value = osi_dma_readl((nveu8_t *)osi_dma->base +
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EQOS_DMA_CHX_SLOT_CTRL(chan));
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value &= ~EQOS_DMA_CHX_SLOT_ESC;
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osi_dma_writel(value, (nveu8_t *)osi_dma->base +
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EQOS_DMA_CHX_SLOT_CTRL(chan));
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}
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}
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#ifdef OSI_DEBUG
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/**
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* @brief Enable/disable debug interrupt
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*
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* @param[in] osi_dma: OSI DMA private data structure.
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*
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* Algorithm:
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* - if osi_dma->ioctl_data.arg_u32 == OSI_ENABLE enable debug interrupt
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* - else disable bebug inerrupts
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*/
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static void eqos_debug_intr_config(struct osi_dma_priv_data *osi_dma)
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{
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nveu32_t chinx;
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nveu32_t chan;
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nveu32_t val;
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nveu32_t enable = osi_dma->ioctl_data.arg_u32;
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if (enable == OSI_ENABLE) {
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for (chinx = 0; chinx < osi_dma->num_dma_chans; chinx++) {
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chan = osi_dma->dma_chans[chinx];
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val = osi_dma_readl((nveu8_t *)osi_dma->base +
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EQOS_DMA_CHX_INTR_ENA(chan));
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val |= (EQOS_DMA_CHX_INTR_AIE |
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EQOS_DMA_CHX_INTR_FBEE |
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EQOS_DMA_CHX_INTR_RBUE |
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EQOS_DMA_CHX_INTR_TBUE |
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EQOS_DMA_CHX_INTR_NIE);
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osi_dma_writel(val, (nveu8_t *)osi_dma->base +
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EQOS_DMA_CHX_INTR_ENA(chan));
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}
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} else {
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for (chinx = 0; chinx < osi_dma->num_dma_chans; chinx++) {
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chan = osi_dma->dma_chans[chinx];
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val = osi_dma_readl((nveu8_t *)osi_dma->base +
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EQOS_DMA_CHX_INTR_ENA(chan));
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val &= (~EQOS_DMA_CHX_INTR_AIE &
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~EQOS_DMA_CHX_INTR_FBEE &
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~EQOS_DMA_CHX_INTR_RBUE &
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~EQOS_DMA_CHX_INTR_TBUE &
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~EQOS_DMA_CHX_INTR_NIE);
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osi_dma_writel(val, (nveu8_t *)osi_dma->base +
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EQOS_DMA_CHX_INTR_ENA(chan));
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}
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}
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}
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#endif
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/*
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* @brief eqos_init_dma_chan_ops - Initialize EQOS DMA operations.
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*
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* @param[in] ops: DMA channel operations pointer.
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*/
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void eqos_init_dma_chan_ops(struct dma_chan_ops *ops)
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{
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ops->config_slot = eqos_config_slot;
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#ifdef OSI_DEBUG
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ops->debug_intr_config = eqos_debug_intr_config;
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#endif
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}
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#endif /* !OSI_STRIPPED_LIB */
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