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git://nv-tegra.nvidia.com/kernel/nvethernetrm.git
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4864073566
Bug 5068365 Change-Id: Ib25276760ec49685a918354c31364f23093f9558 Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3297947 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
147 lines
5.2 KiB
C
147 lines
5.2 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef INCLUDED_HW_DESC_H
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#define INCLUDED_HW_DESC_H
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/**
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* @addtogroup EQOS_RxDesc Receive Descriptors bit fields
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*
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* @brief These macros are used to check the value in specific bit fields of
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* the descriptor. The fields in the descriptor are mapped as
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* defined in the HW manual
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* @{
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*/
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#define RDES3_OWN OSI_BIT(31)
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#define RDES3_CTXT OSI_BIT(30)
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#define RDES3_IOC OSI_BIT(30)
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#define RDES3_B1V OSI_BIT(24)
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#define RDES3_CDA OSI_BIT(27)
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#define RDES3_LD OSI_BIT(28)
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#define RDES3_FD OSI_BIT(29)
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#define RDES3_ERR_CRC OSI_BIT(24)
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#define RDES3_ERR_GP OSI_BIT(23)
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#define RDES3_ERR_WD OSI_BIT(22)
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#define RDES3_ERR_ORUN OSI_BIT(21)
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#define RDES3_ERR_RE OSI_BIT(20)
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#define RDES3_ERR_DRIB OSI_BIT(19)
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#define RDES3_PKT_LEN 0x00007fffU
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#define RDES3_RS1V OSI_BIT(26)
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#define RDES3_TSD OSI_BIT(6)
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#define RDES3_TSA OSI_BIT(4)
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#define RDES1_TSA OSI_BIT(14)
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#define RDES1_TD OSI_BIT(15)
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#ifndef OSI_STRIPPED_LIB
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#define RDES3_LT (OSI_BIT(16) | OSI_BIT(17) | OSI_BIT(18))
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#define RDES3_LT_VT OSI_BIT(18)
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#define RDES3_LT_DVT (OSI_BIT(16) | OSI_BIT(18))
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#define RDES0_OVT 0x0000FFFFU
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#define RDES3_RS0V OSI_BIT(25)
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#define RDES3_RSV OSI_BIT(26)
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#define RDES3_L34T 0x00F00000U
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#define RDES3_L34T_IPV4_TCP OSI_BIT(20)
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#define RDES3_L34T_IPV4_UDP OSI_BIT(21)
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#define RDES3_L34T_IPV6_TCP (OSI_BIT(23) | OSI_BIT(20))
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#define RDES3_L34T_IPV6_UDP (OSI_BIT(23) | OSI_BIT(21))
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#define RDES3_ELLT_CVLAN 0x90000U
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#define RDES3_ERR_MGBE_CRC (OSI_BIT(16) | OSI_BIT(17))
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#endif /* !OSI_STRIPPED_LIB */
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#define RDES1_IPCE OSI_BIT(7)
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#define RDES1_IPCB OSI_BIT(6)
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#define RDES1_IPV6 OSI_BIT(5)
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#define RDES1_IPV4 OSI_BIT(4)
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#define RDES1_IPHE OSI_BIT(3)
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#define RDES1_PT_MASK (OSI_BIT(2) | OSI_BIT(1) | OSI_BIT(0))
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#define RDES3_ELLT 0xF0000U
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#define RDES3_ELLT_IPHE 0x50000U
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#define RDES3_ELLT_CSUM_ERR 0x60000U
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/** @} */
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/** Error Summary bits for Received packet */
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#define RDES3_ES_BITS \
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(RDES3_ERR_CRC | RDES3_ERR_GP | RDES3_ERR_WD | \
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RDES3_ERR_ORUN | RDES3_ERR_RE | RDES3_ERR_DRIB)
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/** MGBE error summary bits for Received packet */
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#define RDES3_ES_MGBE 0x8000U
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/**
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* @addtogroup EQOS_TxDesc Transmit Descriptors bit fields
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*
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* @brief These macros are used to check the value in specific bit fields of
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* the descriptor. The fields in the descriptor are mapped as
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* defined in the HW manual
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* @{
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*/
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#define TDES2_IOC OSI_BIT(31)
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#define TDES2_MSS_MASK 0x3FFFU
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#define TDES3_OWN OSI_BIT(31)
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#define TDES3_CTXT OSI_BIT(30)
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#define TDES3_TCMSSV OSI_BIT(26)
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#define TDES3_FD OSI_BIT(29)
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#define TDES3_LD OSI_BIT(28)
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#define TDES3_OSTC OSI_BIT(27)
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#define TDES3_TSE OSI_BIT(18)
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#define TDES3_HW_CIC_ALL (OSI_BIT(16) | OSI_BIT(17))
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#define TDES3_HW_CIC_IP_ONLY (OSI_BIT(16))
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#define TDES3_VT_MASK 0xFFFFU
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#define TDES3_THL_MASK 0xFU
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#define TDES3_TPL_MASK 0x3FFFFU
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#define TDES3_PL_MASK 0x7FFFU
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#define TDES3_THL_SHIFT 19U
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#define TDES3_VLTV OSI_BIT(16)
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#define TDES3_TTSS OSI_BIT(17)
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#define TDES3_PIDV OSI_BIT(25)
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/* Tx Errors */
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#define TDES3_IP_HEADER_ERR OSI_BIT(0)
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#define TDES3_UNDER_FLOW_ERR OSI_BIT(2)
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#define TDES3_EXCESSIVE_DEF_ERR OSI_BIT(3)
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#define TDES3_EXCESSIVE_COL_ERR OSI_BIT(8)
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#define TDES3_LATE_COL_ERR OSI_BIT(9)
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#define TDES3_NO_CARRIER_ERR OSI_BIT(10)
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#define TDES3_LOSS_CARRIER_ERR OSI_BIT(11)
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#define TDES3_PL_CHK_SUM_ERR OSI_BIT(12)
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#define TDES3_PKT_FLUSH_ERR OSI_BIT(13)
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#define TDES3_JABBER_TIMEO_ERR OSI_BIT(14)
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/* VTIR = 0x2 (Insert a VLAN tag with the tag value programmed in the
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* MAC_VLAN_Incl register or context descriptor.)
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*/
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#define TDES2_VTIR ((nveu32_t)0x2 << 14U)
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#define TDES2_TTSE ((nveu32_t)0x1 << 30U)
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/** @} */
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/** Error Summary bits for Transmitted packet */
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#define TDES3_ES_BITS (TDES3_IP_HEADER_ERR | \
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TDES3_UNDER_FLOW_ERR | \
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TDES3_EXCESSIVE_DEF_ERR | \
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TDES3_EXCESSIVE_COL_ERR | \
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TDES3_LATE_COL_ERR | \
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TDES3_NO_CARRIER_ERR | \
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TDES3_LOSS_CARRIER_ERR | \
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TDES3_PL_CHK_SUM_ERR | \
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TDES3_PKT_FLUSH_ERR | \
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TDES3_JABBER_TIMEO_ERR)
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#endif /* INCLUDED_HW_DESC_H */
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