Bhadram Varka 5b45034d1c osi: eqos: mgbe: program SID through HV window ...

Issue: In non-hypervisor configurations SID programmed
through RM window. In orin EQOS/MGBE these SID should
program through HV window to get reflected in controller
register space.

Fix: Program SID through HV window

Bug 3358505
Bug 200761024

Change-Id: I1db99c85e875aeaf6c692011a0d2fbe16277d288
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2582062
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit

2024-02-21 16:32:06 +05:30

..

ivc_core.h

nvethernetrm: Update IVC support for macsec

2024-02-21 16:32:00 +05:30

mmc.h

nvethernetrm: address review comments

2024-02-21 16:32:06 +05:30

osi_common.h

osi: Add core debug for registers/structures

2024-02-21 16:32:06 +05:30

osi_core.h

osi: eqos: mgbe: program SID through HV window

2024-02-21 16:32:06 +05:30

osi_dma_txrx.h

nvethernetrm: mgbe: add support for RSS

2024-02-21 16:31:59 +05:30

osi_dma.h

osi: Add core debug for registers/structures

2024-02-21 16:32:06 +05:30

osi_macsec.h

nvethernetrm: address review comments

2024-02-21 16:32:06 +05:30