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6c637ac71e
Bug 3918941 Change-Id: Iae1cce6bb0bffaa20d601a0c5da62045ce9458fc Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2852448 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
47 lines
1.8 KiB
C
47 lines
1.8 KiB
C
/*
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* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef INCLUDED_HW_COMMON_H
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#define INCLUDED_HW_COMMON_H
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/**
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* @addtogroup COMMON HW specific offset macros
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*
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* @brief Register offset values common for EQOS and MGBE
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* @{
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*/
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#define HW_GLOBAL_DMA_STATUS 0x8700U
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#define VIRT_INTR_CHX_CNTRL(x) (0x8600U + ((x) * 8U))
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#define VIRT_INTR_CHX_STATUS(x) (0x8604U + ((x) * 8U))
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#define AXI_BUS_WIDTH 0x10U
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#define DMA_CHX_INTR_TIE OSI_BIT(0)
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#define DMA_CHX_INTR_RIE OSI_BIT(6)
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#define DMA_CHX_CTRL_PBLX8 OSI_BIT(16)
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#define DMA_CHX_TX_CTRL_OSP OSI_BIT(4)
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#define DMA_CHX_TX_CTRL_TSE OSI_BIT(12)
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#define DMA_CHX_RBSZ_MASK 0x7FFEU
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#define DMA_CHX_RBSZ_SHIFT 1U
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#define DMA_CHX_RX_WDT_RWT_MASK 0xFFU
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/** @} */
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#endif /* INCLUDED_HW_COMMON_H */
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