mirror of
git://nv-tegra.nvidia.com/kernel/nvethernetrm.git
synced 2025-12-22 17:34:29 +03:00
8c7f7328e8
Bug 4043836 Ported from the change - https://git-master.nvidia.com/r/c/nvethernet-docs/+/2896005 Change-Id: Iabbbde0d2733f04bba5d7128e7b8ac5956605424 Signed-off-by: Mahesh Patil <maheshp@nvidia.com> Signed-off-by: Michael Hsu <mhsu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3149288 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Tested-by: Bhadram Varka <vbhadram@nvidia.com> Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Ashutosh Jha <ajha@nvidia.com> Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
218 lines
8.2 KiB
C
218 lines
8.2 KiB
C
/* SPDX-License-Identifier: LicenseRef-NvidiaProprietary
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* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef INCLUDED_CORE_COMMON_H
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#define INCLUDED_CORE_COMMON_H
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#include "core_local.h"
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#ifndef OSI_STRIPPED_LIB
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#define MAC_PFR_PR OSI_BIT(0)
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#define MAC_TCR_TSCFUPDT OSI_BIT(1)
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#define MAC_TCR_TSCTRLSSR OSI_BIT(9)
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#define MAC_PFR_PM OSI_BIT(4)
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#endif /* !OSI_STRIPPED_LIB */
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#define MTL_EST_ADDR_SHIFT 8
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#define MTL_EST_ADDR_MASK (OSI_BIT(8) | OSI_BIT(9) | \
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OSI_BIT(10) | OSI_BIT(11) | \
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OSI_BIT(12) | OSI_BIT(13) | \
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OSI_BIT(14) | OSI_BIT(15) | \
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OSI_BIT(16) | (17U) | \
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OSI_BIT(18) | OSI_BIT(19))
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#define MTL_EST_SRWO OSI_BIT(0)
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#define MTL_EST_R1W0 OSI_BIT(1)
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#define MTL_EST_GCRR OSI_BIT(2)
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#define MTL_EST_DBGM OSI_BIT(4)
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#define MTL_EST_DBGB OSI_BIT(5)
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#define MTL_EST_ERR0 OSI_BIT(20)
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#define MTL_EST_CONTROL_EEST OSI_BIT(0)
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#define MTL_EST_STATUS_SWOL OSI_BIT(7)
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/* EST control OSI_BIT map */
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#define MTL_EST_EEST OSI_BIT(0)
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#define MTL_EST_SSWL OSI_BIT(1)
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#define MTL_EST_QHLBF OSI_BIT(3)
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#define MTL_EST_CTR_HIGH_MAX 0xFFU
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#define MTL_EST_ITRE_CGCE OSI_BIT(4)
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#define MTL_EST_ITRE_IEHS OSI_BIT(3)
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#define MTL_EST_ITRE_IEHF OSI_BIT(2)
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#define MTL_EST_ITRE_IEBE OSI_BIT(1)
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#define MTL_EST_ITRE_IECC OSI_BIT(0)
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/* MTL_FPE_CTRL_STS */
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#define MTL_FPE_CTS_PEC (OSI_BIT(8) | OSI_BIT(9) | \
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OSI_BIT(10) | OSI_BIT(11) | \
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OSI_BIT(12) | OSI_BIT(13) | \
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OSI_BIT(14) | OSI_BIT(15))
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#define MTL_FPE_CTS_PEC_SHIFT 8U
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#define MAC_FPE_CTS_EFPE OSI_BIT(0)
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#define MAC_FPE_CTS_SVER OSI_BIT(1)
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/* MTL FPE adv registers */
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#define MTL_FPE_ADV_HADV_MASK (0xFFFFU)
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#define MTL_FPE_ADV_HADV_VAL 100U
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#define DMA_MODE_SWR OSI_BIT(0)
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#define MTL_QTOMR_FTQ OSI_BIT(0)
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#define MTL_RXQ_OP_MODE_FEP OSI_BIT(4)
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#define MAC_TCR_TSINIT OSI_BIT(2)
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#define MAC_TCR_TSADDREG OSI_BIT(5)
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#define MAC_PPS_CTL_PPSCTRL0 (OSI_BIT(3) | OSI_BIT(2) |\
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OSI_BIT(1) | OSI_BIT(0))
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#define MAC_SSIR_SSINC_SHIFT 16U
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#define MAC_PFR_DAIF OSI_BIT(3)
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#define MAC_PFR_DBF OSI_BIT(5)
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#define MAC_PFR_PCF (OSI_BIT(6) | OSI_BIT(7))
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#define MAC_PFR_SAIF OSI_BIT(8)
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#define MAC_PFR_SAF OSI_BIT(9)
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#define MAC_PFR_HPF OSI_BIT(10)
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#define MAC_PFR_VTFE OSI_BIT(16)
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#define MAC_PFR_IPFE OSI_BIT(20)
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#if !defined(L3L4_WILDCARD_FILTER)
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#define MAC_PFR_IPFE_SHIFT 20U
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#endif /* !L3L4_WILDCARD_FILTER */
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#define MAC_PFR_DNTU OSI_BIT(21)
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#define MAC_PFR_RA OSI_BIT(31)
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#define WRAP_SYNC_TSC_PTP_CAPTURE 0x800CU
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#define WRAP_TSC_CAPTURE_LOW 0x8010U
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#define WRAP_TSC_CAPTURE_HIGH 0x8014U
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#define WRAP_PTP_CAPTURE_LOW 0x8018U
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#define WRAP_PTP_CAPTURE_HIGH 0x801CU
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#define MAC_PKT_FILTER_REG 0x0008
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#define HW_MAC_IER 0x00B4U
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#define WRAP_COMMON_INTR_ENABLE 0x8704U
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/* common l3 l4 register bit fields for eqos and mgbe */
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#ifndef OSI_STRIPPED_LIB
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#define MAC_L3L4_CTR_L3PEN_SHIFT 0
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#define MAC_L3L4_CTR_L3SAM_SHIFT 2
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#define MAC_L3L4_CTR_L3SAIM_SHIFT 3
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#endif /* !OSI_STRIPPED_LIB */
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#define MAC_L3L4_CTR_L3DAM_SHIFT 4
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#ifndef OSI_STRIPPED_LIB
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#define MAC_L3L4_CTR_L3DAIM_SHIFT 5
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#define MAC_L3L4_CTR_L4PEN_SHIFT 16
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#define MAC_L3L4_CTR_L4SPM_SHIFT 18
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#define MAC_L3L4_CTR_L4SPIM_SHIFT 19
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#define MAC_L3L4_CTR_L4DPM_SHIFT 20
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#define MAC_L3L4_CTR_L4DPIM_SHIFT 21
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#endif /* !OSI_STRIPPED_LIB */
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#define MAC_L3L4_CTR_DMCHN_SHIFT 24
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#define EQOS_MAC_L3L4_CTR_DMCHEN_SHIFT 28
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#define MGBE_MAC_L3L4_CTR_DMCHEN_SHIFT 31
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#define MAC_QX_TX_FLW_CTRL(x) ((0x0004U * (x)) + 0x0070U)
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#define MAC_QX_TX_FLW_CTRL_TFE OSI_BIT(1)
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#define MAC_PAUSE_TIME_MASK 0xFFFF0000U
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#define MAC_PAUSE_TIME 0xFFFF0000U
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#define MAC_RX_FLW_CTRL 0x0090
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#define MAC_RX_FLW_CTRL_RFE OSI_BIT(0)
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#ifdef HSI_SUPPORT
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/**
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* @addtogroup MMC HW register offsets
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*
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* @brief MMC HW register offsets
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* @{
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*/
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#define EQOS_MMC_RXCRCERROR 0x00794
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#define EQOS_MMC_RXIPV4_HDRERR_PKTS 0x00814
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#define EQOS_MMC_RXIPV6_HDRERR_PKTS 0x00828
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#define EQOS_MMC_RXUDP_ERR_PKTS 0x00834
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#define EQOS_MMC_RXTCP_ERR_PKTS 0x0083c
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#define MGBE_MMC_RXCRCERROR_L 0x00928
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#define MGBE_MMC_RXIPV4_HDRERR_PKTS_L 0x00A6C
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#define MGBE_MMC_RXIPV6_HDRERR_PKTS_L 0x00A94
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#define MGBE_MMC_RXUDP_ERR_PKTS_L 0x00AAC
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#define MGBE_MMC_RXTCP_ERR_PKTS_L 0x00ABC
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/** @} */
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#endif /* HSI_SUPPORT */
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/**
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* @addtogroup typedef related info
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*
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* @brief typedefs that indeicates variable address and memory addr
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* @{
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*/
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struct est_read {
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/** variable pointer */
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nveu32_t *var;
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/** memory register/address offset */
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nveu32_t addr;
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};
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/** @} */
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nve32_t poll_check(struct osi_core_priv_data *const osi_core, nveu8_t *addr,
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nveu32_t bit_check, nveu32_t *value);
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nve32_t hw_poll_for_swr(struct osi_core_priv_data *const osi_core);
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void hw_start_mac(struct osi_core_priv_data *const osi_core);
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void hw_stop_mac(struct osi_core_priv_data *const osi_core);
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nve32_t hw_set_mode(struct osi_core_priv_data *const osi_core, const nve32_t mode);
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nve32_t hw_set_speed(struct osi_core_priv_data *const osi_core, const nve32_t speed);
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nve32_t hw_flush_mtl_tx_queue(struct osi_core_priv_data *const osi_core,
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const nveu32_t q_inx);
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nve32_t hw_config_fw_err_pkts(struct osi_core_priv_data *osi_core,
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const nveu32_t q_inx, const nveu32_t enable_fw_err_pkts);
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nve32_t hw_config_rxcsum_offload(struct osi_core_priv_data *const osi_core,
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nveu32_t enabled);
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nve32_t hw_set_systime_to_mac(struct osi_core_priv_data *const osi_core,
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const nveu32_t sec, const nveu32_t nsec);
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nve32_t hw_config_addend(struct osi_core_priv_data *const osi_core,
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const nveu32_t addend);
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void hw_config_tscr(struct osi_core_priv_data *const osi_core, const nveu32_t ptp_filter);
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void hw_config_ssir(struct osi_core_priv_data *const osi_core);
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nve32_t hw_ptp_tsc_capture(struct osi_core_priv_data *const osi_core,
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struct osi_core_ptp_tsc_data *data);
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nve32_t hw_config_mac_pkt_filter_reg(struct osi_core_priv_data *const osi_core,
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const struct osi_filter *filter);
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#if !defined(L3L4_WILDCARD_FILTER)
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void hw_config_l3_l4_filter_enable(struct osi_core_priv_data *const osi_core,
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const nveu32_t filter_enb_dis);
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#endif /* !L3L4_WILDCARD_FILTER */
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nve32_t hw_config_est(struct osi_core_priv_data *const osi_core,
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struct osi_est_config *const est);
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nve32_t hw_config_fpe(struct osi_core_priv_data *const osi_core,
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struct osi_fpe_config *const fpe);
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void hw_tsn_init(struct osi_core_priv_data *osi_core);
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void prepare_l3l4_registers(const struct osi_core_priv_data *const osi_core,
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const struct osi_l3_l4_filter *const l3_l4,
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#ifndef OSI_STRIPPED_LIB
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nveu32_t *l3_addr0_reg,
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nveu32_t *l3_addr2_reg,
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nveu32_t *l3_addr3_reg,
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nveu32_t *l4_addr_reg,
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#endif /* !OSI_STRIPPED_LIB */
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nveu32_t *l3_addr1_reg,
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nveu32_t *ctr_reg);
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#ifdef HSI_SUPPORT
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#ifdef NV_VLTEST_BUILD
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nve32_t hsi_common_error_inject(struct osi_core_priv_data *osi_core,
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nveu32_t error_code);
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#endif
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void hsi_read_err(struct osi_core_priv_data *const osi_core);
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#endif
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nve32_t hw_validate_avb_input(struct osi_core_priv_data *const osi_core,
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const struct osi_core_avb_algorithm *const avb);
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void hw_config_flow_control(struct osi_core_priv_data *const osi_core);
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void core_get_systime_from_mac(void *addr, nveu32_t mac, nveu32_t *sec, nveu32_t *nsec);
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#endif /* INCLUDED_CORE_COMMON_H */
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