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Updating prebuilts and/or headers

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ed288ef2d308f39dc4a10efde8c5041db138a145 - nvscibuf.h
e91fc7a9c1daab4c34970804792b70df556ee9f8 - nvsciipc.cfg
c2219e53c743c6453b1a54ffec54bfce9907b571 - nvscistream_api.h
211f46a8c41805aff5142c3552fec95ce72c7d03 - nvscisync.h
6b8809ed1b39dcb64c4da2f34ffee2aec10bb0b1 - nvscistream.h
d0ddab94c11685c63a68694bed69f02c951c170b - nvscievent.h
60df71827224ad5951cf42d18b8005ad6f9a0399 - nvscistream_types.h
90b2d50de948c0f2486fcfae0833370ea8a2d03f - nvscierror.h
af012d853fbe7ddf90af9cb1b8bd136948b7bb58 - nvsciipc.h

Change-Id: Id61f81a78a139d61519048fea32d6030be614032
This commit is contained in:
svcmobrel-release
2024-09-06 00:00:46 -07:00
parent 7c6da0aae1
commit cbac85587f
12 changed files with 13246 additions and 0 deletions
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80
nvsciipc.cfg Normal file
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#
# Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
#
# Format of NvSciIpc Config file
#
# First column should specify the backend. All possible backend types
# are listed below:
# INTER_THREAD, INTER_PROCESS, INTER_VM, INTER_CHIP
#
# For INTER_THREAD/PROCESS backend type, format will be:
# <backend_type> <endpoint1_name> <endpoint2_name> <backend_info1> <backend_info2>
#
# For INTER_THREAD and INTER_PROCESS, two endpoints name should be different.
# You can use different suffix with basename for them. <backend_info1> denotes
# "number of frames" and <backend_info2> denotes "frame size"
#
# For INTER_VM/CHIP backend type, format will be:
# <backend_type> <endpoint_name> <backend_info1>
#
# For INTER_CHIP optional backend info is derive with below rule:
# <xfer_role><device_id>
# Both should be written as two digit decimal number.
# eg: device_id = 5, xfer_role = producer
# backend info: 0105
#
# For INTER_VM backend type, BACKEND_INFO1 denotes ivc queue number
#
# This is NvSciIpc CFG file for x86 machine, so only 3 backends are supported
# as of now : INTER_PROCESS, INTER_THREAD and INTER_CHIP
INTER_PROCESS ipc_test_0 ipc_test_1 64 1536
INTER_PROCESS ipc_test_a_0 ipc_test_a_1 64 1536
INTER_PROCESS ipc_test_b_0 ipc_test_b_1 64 1536
INTER_PROCESS ipc_test_c_0 ipc_test_c_1 64 1536
INTER_THREAD itc_test_0 itc_test_1 64 1536
INTER_PROCESS nvscistream_0 nvscistream_1 16 24576
INTER_PROCESS nvscistream_2 nvscistream_3 16 24576
INTER_PROCESS nvscistream_4 nvscistream_5 16 24576
INTER_PROCESS nvscistream_6 nvscistream_7 16 24576
INTER_PROCESS nvscisync_a_0 nvscisync_a_1 16 24576
INTER_PROCESS nvscisync_b_0 nvscisync_b_1 16 24576
INTER_PROCESS nvscisync_c_0 nvscisync_c_1 16 24576
INTER_PROCESS nvscisync_d_0 nvscisync_d_1 16 24576
INTER_PROCESS nvscibuf_ipc_A_B nvscibuf_ipc_B_A 16 24576
INTER_PROCESS nvscibuf_ipc_B_C nvscibuf_ipc_C_B 16 24576
INTER_PROCESS nvscibuf_ipc_A_D nvscibuf_ipc_D_A 16 24576
INTER_PROCESS nvscibuf_ipc_B_E nvscibuf_ipc_E_B 16 24576
INTER_PROCESS nvmap_sciipc_1 nvmap_sciipc_2 16 24576
INTER_PROCESS nvmap_sciipc_3 nvmap_sciipc_4 16 24576
INTER_CHIP nvscic2c_pcie_s0_c5_1 0000
INTER_CHIP nvscic2c_pcie_s0_c5_2 0000
INTER_CHIP nvscic2c_pcie_s0_c5_3 0000
INTER_CHIP nvscic2c_pcie_s0_c5_4 0000
INTER_CHIP nvscic2c_pcie_s0_c5_5 0000
INTER_CHIP nvscic2c_pcie_s0_c5_6 0000
INTER_CHIP nvscic2c_pcie_s0_c5_7 0000
INTER_CHIP nvscic2c_pcie_s0_c5_8 0000
INTER_CHIP nvscic2c_pcie_s0_c5_9 0000
INTER_CHIP nvscic2c_pcie_s0_c5_10 0000
INTER_CHIP nvscic2c_pcie_s0_c5_11 0000
INTER_CHIP nvscic2c_pcie_s0_c6_1 0000
INTER_CHIP nvscic2c_pcie_s0_c6_2 0000
INTER_CHIP nvscic2c_pcie_s0_c6_3 0000
INTER_CHIP nvscic2c_pcie_s0_c6_4 0000
INTER_CHIP nvscic2c_pcie_s0_c6_5 0000
INTER_CHIP nvscic2c_pcie_s0_c6_6 0000
INTER_CHIP nvscic2c_pcie_s0_c6_7 0000
INTER_CHIP nvscic2c_pcie_s0_c6_8 0000
INTER_CHIP nvscic2c_pcie_s0_c6_9 0000
INTER_CHIP nvscic2c_pcie_s0_c6_10 0000
INTER_CHIP nvscic2c_pcie_s0_c6_11 0000
INTER_CHIP egl_nvscic2c_5_prod 0105
INTER_CHIP egl_nvscic2c_5_cons 1005
INTER_CHIP egl_nvscic2c_6_prod 0106
INTER_CHIP egl_nvscic2c_6_cons 1006
INTER_CHIP egl_nvscic2c_7_prod 0107
INTER_CHIP egl_nvscic2c_7_cons 1007
INTER_CHIP egl_nvscic2c_8_prod 0108
INTER_CHIP egl_nvscic2c_8_cons 1008
INTER_CHIP egl_nvscic2c_9_prod 0109
INTER_CHIP egl_nvscic2c_9_cons 1009