# # Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. # # Format of NvSciIpc Config file # # First column should specify the backend. All possible backend types # are listed below: # INTER_THREAD, INTER_PROCESS, INTER_VM, INTER_CHIP # # For INTER_THREAD/PROCESS backend type, format will be: # # # For INTER_THREAD and INTER_PROCESS, two endpoints name should be different. # You can use different suffix with basename for them. denotes # "number of frames" and denotes "frame size" # # For INTER_VM/CHIP backend type, format will be: # # # For INTER_CHIP optional backend info is derive with below rule: # # Both should be written as two digit decimal number. # eg: device_id = 5, xfer_role = producer # backend info: 0105 # # For INTER_VM backend type, BACKEND_INFO1 denotes ivc queue number # # This is NvSciIpc CFG file for x86 machine, so only 3 backends are supported # as of now : INTER_PROCESS, INTER_THREAD and INTER_CHIP INTER_PROCESS ipc_test_0 ipc_test_1 64 1536 INTER_PROCESS ipc_test_a_0 ipc_test_a_1 64 1536 INTER_PROCESS ipc_test_b_0 ipc_test_b_1 64 1536 INTER_PROCESS ipc_test_c_0 ipc_test_c_1 64 1536 INTER_PROCESS ipc_latency_0 ipc_latency_1 1 64 INTER_THREAD itc_test_0 itc_test_1 64 1536 INTER_THREAD nvscistream_itc_0 nvscistream_itc_1 64 1536 INTER_THREAD nvscibuf_itc_0 nvscibuf_itc_1 64 1536 INTER_PROCESS nvscistream_0 nvscistream_1 16 24576 INTER_PROCESS nvscistream_2 nvscistream_3 16 24576 INTER_PROCESS nvscistream_4 nvscistream_5 16 24576 INTER_PROCESS nvscistream_6 nvscistream_7 16 24576 INTER_PROCESS nvscisync_a_0 nvscisync_a_1 16 24576 INTER_PROCESS nvscisync_b_0 nvscisync_b_1 16 24576 INTER_PROCESS nvscisync_c_0 nvscisync_c_1 16 24576 INTER_PROCESS nvscisync_d_0 nvscisync_d_1 16 24576 INTER_PROCESS nvscibuf_ipc_A_B nvscibuf_ipc_B_A 16 24576 INTER_PROCESS nvscibuf_ipc_B_C nvscibuf_ipc_C_B 16 24576 INTER_PROCESS nvscibuf_ipc_A_D nvscibuf_ipc_D_A 16 24576 INTER_PROCESS nvscibuf_ipc_B_E nvscibuf_ipc_E_B 16 24576 INTER_PROCESS nvmap_sciipc_1 nvmap_sciipc_2 16 24576 INTER_PROCESS nvmap_sciipc_3 nvmap_sciipc_4 16 24576 INTER_CHIP nvscic2c_pcie_s0_c5_1 0000 INTER_CHIP nvscic2c_pcie_s0_c5_2 0000 INTER_CHIP nvscic2c_pcie_s0_c5_3 0000 INTER_CHIP nvscic2c_pcie_s0_c5_4 0000 INTER_CHIP nvscic2c_pcie_s0_c5_5 0000 INTER_CHIP nvscic2c_pcie_s0_c5_6 0000 INTER_CHIP nvscic2c_pcie_s0_c5_7 0000 INTER_CHIP nvscic2c_pcie_s0_c5_8 0000 INTER_CHIP nvscic2c_pcie_s0_c5_9 0000 INTER_CHIP nvscic2c_pcie_s0_c5_10 0000 INTER_CHIP nvscic2c_pcie_s0_c5_11 0000 INTER_CHIP nvscic2c_pcie_s0_c6_1 0000 INTER_CHIP nvscic2c_pcie_s0_c6_2 0000 INTER_CHIP nvscic2c_pcie_s0_c6_3 0000 INTER_CHIP nvscic2c_pcie_s0_c6_4 0000 INTER_CHIP nvscic2c_pcie_s0_c6_5 0000 INTER_CHIP nvscic2c_pcie_s0_c6_6 0000 INTER_CHIP nvscic2c_pcie_s0_c6_7 0000 INTER_CHIP nvscic2c_pcie_s0_c6_8 0000 INTER_CHIP nvscic2c_pcie_s0_c6_9 0000 INTER_CHIP nvscic2c_pcie_s0_c6_10 0000 INTER_CHIP nvscic2c_pcie_s0_c6_11 0000 INTER_CHIP egl_nvscic2c_5_prod 0105 INTER_CHIP egl_nvscic2c_5_cons 1005 INTER_CHIP egl_nvscic2c_6_prod 0106 INTER_CHIP egl_nvscic2c_6_cons 1006 INTER_CHIP egl_nvscic2c_7_prod 0107 INTER_CHIP egl_nvscic2c_7_cons 1007 INTER_CHIP egl_nvscic2c_8_prod 0108 INTER_CHIP egl_nvscic2c_8_cons 1008 INTER_CHIP egl_nvscic2c_9_prod 0109 INTER_CHIP egl_nvscic2c_9_cons 1009