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 * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *  * Neither the name of NVIDIA CORPORATION nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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#ifndef SPI__SPI_PORT_PRIV_H
#define SPI__SPI_PORT_PRIV_H
#define FSP__PORT__SPI_PORT_PRIV_H                      0

/**
 * @file spi/spi-port-priv.h
 * @brief provides context that is specific to the port layer.
 */

/* Compiler headers */

/* Early FSP headers */

/* HW headers */

/* Late FSP headers */

struct spi_hw_handle {
    const struct tegra_rst *rst;
    const struct tegra_clk *clk;
};

#endif
