/*
 * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */

#ifndef PROCESSOR__IRQS_HW_H
#define PROCESSOR__IRQS_HW_H
#define FSP__PROCESSOR__IRQS_HW_H                       1

/* Compiler headers */

/* Early FSP headers */
#include <soc-common/hw-const.h>

/* Hardware headers */
#include <arproc_interrupts.h>

/* Late FSP headers */


#define MAX_VIC_CONTROLLER      4

#include <vic/tegra-vic.h>

/*
 * VIC0 Interrupts
 */
#define NV_DCE_IRQ_HSP0_SI_0    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_0)
#define NV_DCE_IRQ_HSP0_SI_1    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_1)
#define NV_DCE_IRQ_HSP0_SI_2    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_2)
#define NV_DCE_IRQ_HSP0_SI_3    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_3)
#define NV_DCE_IRQ_HSP0_SI_4    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_4)
#define NV_DCE_IRQ_HSP0_SI_5    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_5)
#define NV_DCE_IRQ_HSP0_SI_6    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_6)
#define NV_DCE_IRQ_HSP0_SI_7    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_7)
#define NV_DCE_IRQ_HSP0_SI_8    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_8)
#define NV_DCE_IRQ_HSP0_SI_9    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_9)
#define NV_DCE_IRQ_HSP0_SI_10   TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_10)
#define NV_DCE_IRQ_HSP0_SI_11   TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_11)
#define NV_DCE_IRQ_HSP0_SI_12   TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_12)
#define NV_DCE_IRQ_HSP0_SI_13   TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_13)
#define NV_DCE_IRQ_HSP0_SI_14   TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_14)
#define NV_DCE_IRQ_HSP0_SI_15   TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP0_SI_15)
#define NV_DCE_IRQ_HSP1_SI_0    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_0)
#define NV_DCE_IRQ_HSP1_SI_1    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_1)
#define NV_DCE_IRQ_HSP1_SI_2    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_2)
#define NV_DCE_IRQ_HSP1_SI_3    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_3)
#define NV_DCE_IRQ_HSP1_SI_4    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_4)
#define NV_DCE_IRQ_HSP1_SI_5    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_5)
#define NV_DCE_IRQ_HSP1_SI_6    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_6)
#define NV_DCE_IRQ_HSP1_SI_7    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_7)
#define NV_DCE_IRQ_HSP1_SI_8    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_8)
#define NV_DCE_IRQ_HSP1_SI_9    TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_9)
#define NV_DCE_IRQ_HSP1_SI_10   TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_10)
#define NV_DCE_IRQ_HSP1_SI_11   TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_11)
#define NV_DCE_IRQ_HSP1_SI_12   TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_12)
#define NV_DCE_IRQ_HSP1_SI_13   TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_13)
#define NV_DCE_IRQ_HSP1_SI_14   TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_14)
#define NV_DCE_IRQ_HSP1_SI_15   TEGRA_INTERRUPT(0, NV_PROC_COMMON_VIC0_HSP1_SI_15)

/*
 * VIC1 Interrupts
 */
#define NV_DCE_IRQ_WDTIRQ        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_TKE_WDTIRQ)
#define NV_DCE_IRQ_WDTFIQ        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_TKE_WDTFIQ)
#define NV_DCE_IRQ_TIMER0        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_TKE_TIMER_INTR0)
#define NV_DCE_IRQ_TIMER1        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_TKE_TIMER_INTR1)
#define NV_DCE_IRQ_TIMER2        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_TKE_TIMER_INTR2)
#define NV_DCE_IRQ_TIMER3        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_TKE_TIMER_INTR3)
#define NV_DCE_IRQ_DMA0          TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_DMA_INTR0)
#define NV_DCE_IRQ_DMA1          TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_DMA_INTR1)
#define NV_DCE_IRQ_DMA2          TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_DMA_INTR2)
#define NV_DCE_IRQ_DMA3          TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_DMA_INTR3)
#define NV_DCE_IRQ_DMA4          TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_DMA_INTR4)
#define NV_DCE_IRQ_DMA5          TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_DMA_INTR5)
#define NV_DCE_IRQ_DMA6          TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_DMA_INTR6)
#define NV_DCE_IRQ_DMA7          TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_DMA_INTR7)
#define NV_DCE_IRQ_PMU           TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_CPU_PMUIRQ)
#define NV_DCE_IRQ_FPUINT        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_CPU_FPUINT)
#define NV_DCE_IRQ_CTIIRQ        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_CPU_CTIIRQ)
#define NV_DCE_IRQ_NOC_SECURE    TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_NIC_SECURE_INTR)
#define NV_DCE_IRQ_ACTMON        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_CENTRAL_ACTMON_INTR)
#define NV_DCE_IRQ_GTE           TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_GTE_INTR)
#define NV_DCE_IRQ_MISC0         TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_MISC_IRQ0_INTR)
#define NV_DCE_IRQ_MISC1         TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_MISC_IRQ1_INTR)
#define NV_DCE_IRQ_RSVD22        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_RSVD22)
#define NV_DCE_IRQ_RSVD23        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_RSVD23)
#define NV_DCE_IRQ_RSVD24        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_RSVD24)
#define NV_DCE_IRQ_RSVD25        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_RSVD25)
#define NV_DCE_IRQ_RSVD26        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_RSVD26)
#define NV_DCE_IRQ_RSVD27        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_RSVD27)
#define NV_DCE_IRQ_RSVD28        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_RSVD28)
#define NV_DCE_IRQ_RSVD29        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_RSVD29)
#define NV_DCE_IRQ_RSVD30        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_RSVD30)
#define NV_DCE_IRQ_RSVD31        TEGRA_INTERRUPT(1, NV_PROC_COMMON_VIC1_RSVD31)

/*
 * VIC2 Interrupts
 */
#define NV_DCE_IRQ_TOP0_HSP_DB   TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_TOP0_HSP_DB_INTR)
#define NV_DCE_IRQ_LIC_IRQ0      TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_LIC_IRQ0)
#define NV_DCE_IRQ_LIC_FIQ0      TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_LIC_FIQ0)
#define NV_DCE_IRQ_I2C0          TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C0_INTR)
#define NV_DCE_IRQ_I2C1          TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C1_INTR)
#define NV_DCE_IRQ_I2C3          TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C3_INTR)
#define NV_DCE_IRQ_I2C4          TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C4_INTR)
#define NV_DCE_IRQ_I2C6          TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C6_INTR)
#define NV_DCE_IRQ_I2C7          TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C7_INTR)
#define NV_DCE_IRQ_I2C8          TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C8_INTR)
#define NV_DCE_IRQ_I2C9          TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C9_INTR)
#define NV_DCE_IRQ_I2C10         TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C10_INTR)
#define NV_DCE_IRQ_I2C11         TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C11_INTR)
#define NV_DCE_IRQ_I2C12         TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C12_INTR)
#define NV_DCE_IRQ_I2C14         TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C14_INTR)
#define NV_DCE_IRQ_I2C15         TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C15_INTR)
#define NV_DCE_IRQ_I2C16         TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_I2C16_INTR)
#define NV_DCE_IRQ_NVDISPLAY     TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_NVDISPLAY_INTR)
#define NV_DCE_IRQ_DPAUX0        TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_DPAUX0_INTR)
#define NV_DCE_IRQ_DPAUX1        TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_DPAUX1_INTR)
#define NV_DCE_IRQ_DPAUX2        TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_DPAUX2_INTR)
#define NV_DCE_IRQ_DPAUX3        TEGRA_INTERRUPT(2, NV_PROC_DCE_VIC2_DPAUX3_INTR)

#endif  /* FSP_SOC_T234_DCE_PROCESSOR_IRQS_HW_H */
