/*
 * SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */

#ifndef SOC_COMMON__CLK_TEGRA_HW_H
#define SOC_COMMON__CLK_TEGRA_HW_H
#define FSP__SOC_COMMON__CLK_TEGRA_HW_H                 1

extern const struct tegra_clk tegra_clk_uart0_data;
extern const struct tegra_clk tegra_clk_uart5_data;

extern struct tegra_parent_clk tegra_parent_clk_pll_aon_data;
extern struct tegra_parent_clk tegra_parent_clk_pll_p_data;
extern struct tegra_parent_clk tegra_parent_clk_osc_undiv_data;

extern const struct tegra_rst tegra_rst_uart0_data;
extern const struct tegra_rst tegra_rst_uart5_data;
extern const struct tegra_rst tegra_rst_dce_gpcdma_data;

#define tegra_parent_clk_pll_aon tegra_parent_clk_pll_aon_data
#define tegra_parent_clk_pll_p tegra_parent_clk_pll_p_data
#define tegra_parent_clk_osc_undiv tegra_parent_clk_osc_undiv_data

#define tegra_clk_uart0 (&tegra_clk_uart0_data)
#define tegra_clk_uart5 (&tegra_clk_uart5_data)

#define tegra_rst_uart0 (&tegra_rst_uart0_data)
#define tegra_rst_uart5 (&tegra_rst_uart5_data)
#define tegra_rst_dce_gpcdma (&tegra_rst_dce_gpcdma_data)

#endif
