/*
* Copyright (c) 2023 NVIDIA CORPORATION.  All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.  Any use, reproduction, disclosure or
* distribution of this software and related documentation without an express
* license agreement from NVIDIA CORPORATION is strictly prohibited.
*/

/**
 * @file vic-irqs.h
 */

#ifndef HW_CONFIG__VIC_IRQS_H
#define HW_CONFIG__VIC_IRQS_H
#define FSP__HW_CONFIG__VIC_IRQS_H                      1

/* Compiler headers */

/* Early FSP headers */
#include <misc/ct-assert.h>
#include <soc-common/hw-const.h>

/* Hardware headers */

/* Late FSP headers */
#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, ...

/* Module-specific FSP headers */
#include <processor/irqs-hw.h>
#include <vic/tegra-vic.h>

/*
 * Compile-time check for FSP header files
 *   Each FSP header file contains a signature unique to that file, and the
 *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
 *   check for this signature.  If it does not exist, then the build will
 *   abort.
 *
 *   This is a trap for projects which have their own include files of the
 *   same names, but different contents.  This trap ensures that only the
 *   files from the FSP project, are built into the FSP source code.
 */
START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
CT_ASSERT(FSP__VIC__TEGRA_VIC_H, "Header file missing or invalid.")
END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")

#define NUM_VICS                        4

/* VIC0 interrupts */
#define INTERRUPT_HSP0_SI_0		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_0)
#define INTERRUPT_HSP0_SI_1		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_1)
#define INTERRUPT_HSP0_SI_2		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_2)
#define INTERRUPT_HSP0_SI_3		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_3)
#define INTERRUPT_HSP0_SI_4		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_4)
#define INTERRUPT_HSP0_SI_5		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_5)
#define INTERRUPT_HSP0_SI_6		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_6)
#define INTERRUPT_HSP0_SI_7		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_7)
#define INTERRUPT_HSP0_SI_8		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_8)
#define INTERRUPT_HSP0_SI_9		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_9)
#define INTERRUPT_HSP0_SI_10	    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_10)
#define INTERRUPT_HSP0_SI_11	    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_11)
#define INTERRUPT_HSP0_SI_12	    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_12)
#define INTERRUPT_HSP0_SI_13	    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_13)
#define INTERRUPT_HSP0_SI_14	    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_14)
#define INTERRUPT_HSP0_SI_15	    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP0_SI_15)
#define INTERRUPT_HSP1_SI_0		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_0)
#define INTERRUPT_HSP1_SI_1		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_1)
#define INTERRUPT_HSP1_SI_2		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_2)
#define INTERRUPT_HSP1_SI_3		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_3)
#define INTERRUPT_HSP1_SI_4		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_4)
#define INTERRUPT_HSP1_SI_5		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_5)
#define INTERRUPT_HSP1_SI_6		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_6)
#define INTERRUPT_HSP1_SI_7		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_7)
#define INTERRUPT_HSP1_SI_8		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_8)
#define INTERRUPT_HSP1_SI_9		    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_9)
#define INTERRUPT_HSP1_SI_10	    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_10)
#define INTERRUPT_HSP1_SI_11	    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_11)
#define INTERRUPT_HSP1_SI_12	    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_12)
#define INTERRUPT_HSP1_SI_13	    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_13)
#define INTERRUPT_HSP1_SI_14	    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_14)
#define INTERRUPT_HSP1_SI_15	    TEGRA_INTERRUPT(0, NV_BPMP_INTERRUPT_HSP1_SI_15)

/* VIC1 interrupts */
#define INTERRUPT_TKE_WDTIRQ		    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_TKE_WDTIRQ)
#define INTERRUPT_TKE_WDTFIQ		    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_TKE_WDTFIQ)
#define INTERRUPT_TKE_TIMER_INTR0		TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_TKE_TIMER_INTR0)
#define INTERRUPT_TKE_TIMER_INTR1		TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_TKE_TIMER_INTR1)
#define INTERRUPT_TKE_TIMER_INTR2		TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_TKE_TIMER_INTR2)
#define INTERRUPT_TKE_TIMER_INTR3		TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_TKE_TIMER_INTR3)
#define INTERRUPT_DMA_INTR0			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_DMA_INTR0)
#define INTERRUPT_DMA_INTR1			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_DMA_INTR1)
#define INTERRUPT_DMA_INTR2			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_DMA_INTR2)
#define INTERRUPT_DMA_INTR3			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_DMA_INTR3)
#define INTERRUPT_DMA_INTR4			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_DMA_INTR4)
#define INTERRUPT_DMA_INTR5			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_DMA_INTR5)
#define INTERRUPT_DMA_INTR6			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_DMA_INTR6)
#define INTERRUPT_DMA_INTR7			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_DMA_INTR7)
#define INTERRUPT_CPU_PMUIRQ		    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_CPU_PMUIRQ)
#define INTERRUPT_CPU_FPUINT		    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_CPU_FPUINT)
#define INTERRUPT_CPU_CTIIRQ		    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_CPU_CTIIRQ)
#define INTERRUPT_NIC_SECURE_INTR		TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_NIC_SECURE_INTR)
#define INTERRUPT_CENTRAL_ACTMON_INTR	TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_CENTRAL_ACTMON_INTR)
#define INTERRUPT_GTE_INTR			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_GTE_INTR)
#define INTERRUPT_MISC_IRQ0_INTR		TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_MISC_IRQ0_INTR)
#define INTERRUPT_MISC_IRQ1_INTR		TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_MISC_IRQ1_INTR)
#define INTERRUPT_RSVD22			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_RSVD22)
#define INTERRUPT_RSVD23			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_RSVD23)
#define INTERRUPT_RSVD24			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_RSVD24)
#define INTERRUPT_RSVD25			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_RSVD25)
#define INTERRUPT_RSVD26			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_RSVD26)
#define INTERRUPT_RSVD27			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_RSVD27)
#define INTERRUPT_RSVD28			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_RSVD28)
#define INTERRUPT_RSVD29			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_RSVD29)
#define INTERRUPT_RSVD30			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_RSVD30)
#define INTERRUPT_RSVD31			    TEGRA_INTERRUPT(1, NV_BPMP_INTERRUPT_RSVD31)

/* VIC2 interrupts */
#define INTERRUPT_TOP0_HSP_DB_INTR		TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_TOP0_HSP_DB_INTR)
#define INTERRUPT_WAKE_TIER0_INTR		TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_WAKE_TIER0_INTR)
#define INTERRUPT_WAKE_TIER1_INTR		TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_WAKE_TIER1_INTR)
#define INTERRUPT_WAKE_TIER2_INTR		TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_WAKE_TIER2_INTR)
#define INTERRUPT_LIC_IRQ0			    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_LIC_IRQ0)
#define INTERRUPT_LIC_FIQ0			    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_LIC_FIQ0)
#define INTERRUPT_PSC_INTR			    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_PSC_INTR)
#define INTERRUPT_OESP_INTR			    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_OESP_INTR)
#define INTERRUPT_SB_INTR			    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_SB_INTR)
#define INTERRUPT_GPMU_INTR			    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_GPMU_INTR)
#define INTERRUPT_CPU_PCSM_ASSIST_INTR  TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_CPU_PCSM_ASSIST_INTR)
#define INTERRUPT_CPU_RGC_ASSIST_INTR	TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_CPU_RGC_ASSIST_INTR)
#define INTERRUPT_CPU_NDIV_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_CPU_NDIV_INTR)
#define INTERRUPT_H1XSNC_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_H1XSNC_INTR)
#define INTERRUPT_DFD_0_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_DFD_0_INTR)
#define INTERRUPT_I2C5_INTR			    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_I2C5_INTR)
#define INTERRUPT_UART0_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_UART0_INTR)
#define INTERRUPT_UART4_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_UART4_INTR)
#define INTERRUPT_UART5_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_UART5_INTR)
#define INTERRUPT_UART8_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_UART8_INTR)
#define INTERRUPT_UART9_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_UART9_INTR)
#define INTERRUPT_UART10_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_UART10_INTR)
#define INTERRUPT_QSPI0_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_QSPI0_INTR)
#define INTERRUPT_QSPI2_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_QSPI2_INTR)
#define INTERRUPT_QSPI3_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_QSPI3_INTR)
#define INTERRUPT_QSPI5_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_QSPI5_INTR)
#define INTERRUPT_NVTHERM_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_NVTHERM_INTR)
#define INTERRUPT_MSS_SEQ_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_MSS_SEQ_INTR)
#define INTERRUPT_SDMMC1_INTR		    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_SDMMC1_INTR)
#define INTERRUPT_SDMMC1_SYS_INTR		TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_SDMMC1_SYS_INTR)
#define INTERRUPT_BME_INTR			    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_BME_INTR)
#define INTERRUPT_UFS_INTR			    TEGRA_INTERRUPT(2, NV_PROC_BPMP_VIC2_UFS_INTR)

/* VIC3 interrupts */
#define INTERRUPT_CAR_INTR			    TEGRA_INTERRUPT(3, NV_PROC_BPMP_VIC3_CAR_INTR)
#define INTERRUPT_IH2BPMP_ERR_INTR		TEGRA_INTERRUPT(3, NV_PROC_BPMP_VIC3_IH2BPMP_ERR_INTR)

#endif /* PROCESSOR__IRQS_HW_H */
