//
// Copyright (c) 2021 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARUART_H_INC
#define ARUART_H_INC
#define NV_MOBILE_ARUART_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARUART_H_SCRREG_NOMENCLATURE INFERRED


// Register UART_THR_DLAB_0_0
#define UART_THR_DLAB_0_0                       MK_ADDR_CONST(0x0)
#define UART_THR_DLAB_0_0_SECURE                        0x0
#define UART_THR_DLAB_0_0_DUAL                  0x0
#define UART_THR_DLAB_0_0_SCR                   0
#define UART_THR_DLAB_0_0_SCRREG                        0
#define UART_THR_DLAB_0_0_WORD_COUNT                    0x1
#define UART_THR_DLAB_0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define UART_THR_DLAB_0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_READ_MASK                     MK_MASK_CONST(0xff)
#define UART_THR_DLAB_0_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define UART_THR_DLAB_0_0_THR_A_SHIFT                   MK_SHIFT_CONST(0)
#define UART_THR_DLAB_0_0_THR_A_FIELD                   MK_FIELD_CONST(0xff, UART_THR_DLAB_0_0_THR_A_SHIFT)
#define UART_THR_DLAB_0_0_THR_A_RANGE                   7:0
#define UART_THR_DLAB_0_0_THR_A_MSB                     MK_SHIFT_CONST(7)
#define UART_THR_DLAB_0_0_THR_A_LSB                     MK_SHIFT_CONST(0)
#define UART_THR_DLAB_0_0_THR_A_WOFFSET                 0x0
#define UART_THR_DLAB_0_0_THR_A_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_THR_A_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define UART_THR_DLAB_0_0_THR_A_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_THR_A_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_THR_A_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_THR_A_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define UART_THR_DLAB_0_0_RBR_A_SHIFT                   MK_SHIFT_CONST(0)
#define UART_THR_DLAB_0_0_RBR_A_FIELD                   MK_FIELD_CONST(0xff, UART_THR_DLAB_0_0_RBR_A_SHIFT)
#define UART_THR_DLAB_0_0_RBR_A_RANGE                   7:0
#define UART_THR_DLAB_0_0_RBR_A_MSB                     MK_SHIFT_CONST(7)
#define UART_THR_DLAB_0_0_RBR_A_LSB                     MK_SHIFT_CONST(0)
#define UART_THR_DLAB_0_0_RBR_A_WOFFSET                 0x0
#define UART_THR_DLAB_0_0_RBR_A_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_RBR_A_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define UART_THR_DLAB_0_0_RBR_A_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_RBR_A_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_RBR_A_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_RBR_A_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define UART_THR_DLAB_0_0_DLL_A_SHIFT                   MK_SHIFT_CONST(0)
#define UART_THR_DLAB_0_0_DLL_A_FIELD                   MK_FIELD_CONST(0xff, UART_THR_DLAB_0_0_DLL_A_SHIFT)
#define UART_THR_DLAB_0_0_DLL_A_RANGE                   7:0
#define UART_THR_DLAB_0_0_DLL_A_MSB                     MK_SHIFT_CONST(7)
#define UART_THR_DLAB_0_0_DLL_A_LSB                     MK_SHIFT_CONST(0)
#define UART_THR_DLAB_0_0_DLL_A_WOFFSET                 0x0
#define UART_THR_DLAB_0_0_DLL_A_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_DLL_A_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define UART_THR_DLAB_0_0_DLL_A_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_DLL_A_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_DLL_A_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_THR_DLAB_0_0_DLL_A_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register UART_IER_DLAB_0_0
#define UART_IER_DLAB_0_0                       MK_ADDR_CONST(0x4)
#define UART_IER_DLAB_0_0_SECURE                        0x0
#define UART_IER_DLAB_0_0_DUAL                  0x0
#define UART_IER_DLAB_0_0_SCR                   0
#define UART_IER_DLAB_0_0_SCRREG                        0
#define UART_IER_DLAB_0_0_WORD_COUNT                    0x1
#define UART_IER_DLAB_0_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_RESET_MASK                    MK_MASK_CONST(0x3f)
#define UART_IER_DLAB_0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_READ_MASK                     MK_MASK_CONST(0x3f)
#define UART_IER_DLAB_0_0_WRITE_MASK                    MK_MASK_CONST(0x3f)
#define UART_IER_DLAB_0_0_IE_EORD_SHIFT                 MK_SHIFT_CONST(5)
#define UART_IER_DLAB_0_0_IE_EORD_FIELD                 MK_FIELD_CONST(0x1, UART_IER_DLAB_0_0_IE_EORD_SHIFT)
#define UART_IER_DLAB_0_0_IE_EORD_RANGE                 5:5
#define UART_IER_DLAB_0_0_IE_EORD_MSB                   MK_SHIFT_CONST(5)
#define UART_IER_DLAB_0_0_IE_EORD_LSB                   MK_SHIFT_CONST(5)
#define UART_IER_DLAB_0_0_IE_EORD_WOFFSET                       0x0
#define UART_IER_DLAB_0_0_IE_EORD_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_EORD_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define UART_IER_DLAB_0_0_IE_EORD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_EORD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_EORD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_EORD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define UART_IER_DLAB_0_0_IE_EORD_DISABLE                       MK_ENUM_CONST(0)
#define UART_IER_DLAB_0_0_IE_EORD_ENABLE                        MK_ENUM_CONST(1)

#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SHIFT                   MK_SHIFT_CONST(4)
#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_FIELD                   MK_FIELD_CONST(0x1, UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SHIFT)
#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_RANGE                   4:4
#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_MSB                     MK_SHIFT_CONST(4)
#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_LSB                     MK_SHIFT_CONST(4)
#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_WOFFSET                 0x0
#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_DISABLE                 MK_ENUM_CONST(0)
#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_ENABLE                  MK_ENUM_CONST(1)

#define UART_IER_DLAB_0_0_IE_MSI_SHIFT                  MK_SHIFT_CONST(3)
#define UART_IER_DLAB_0_0_IE_MSI_FIELD                  MK_FIELD_CONST(0x1, UART_IER_DLAB_0_0_IE_MSI_SHIFT)
#define UART_IER_DLAB_0_0_IE_MSI_RANGE                  3:3
#define UART_IER_DLAB_0_0_IE_MSI_MSB                    MK_SHIFT_CONST(3)
#define UART_IER_DLAB_0_0_IE_MSI_LSB                    MK_SHIFT_CONST(3)
#define UART_IER_DLAB_0_0_IE_MSI_WOFFSET                        0x0
#define UART_IER_DLAB_0_0_IE_MSI_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_MSI_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define UART_IER_DLAB_0_0_IE_MSI_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_MSI_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_MSI_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_MSI_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define UART_IER_DLAB_0_0_IE_MSI_DISABLE                        MK_ENUM_CONST(0)
#define UART_IER_DLAB_0_0_IE_MSI_ENABLE                 MK_ENUM_CONST(1)

#define UART_IER_DLAB_0_0_IE_RXS_SHIFT                  MK_SHIFT_CONST(2)
#define UART_IER_DLAB_0_0_IE_RXS_FIELD                  MK_FIELD_CONST(0x1, UART_IER_DLAB_0_0_IE_RXS_SHIFT)
#define UART_IER_DLAB_0_0_IE_RXS_RANGE                  2:2
#define UART_IER_DLAB_0_0_IE_RXS_MSB                    MK_SHIFT_CONST(2)
#define UART_IER_DLAB_0_0_IE_RXS_LSB                    MK_SHIFT_CONST(2)
#define UART_IER_DLAB_0_0_IE_RXS_WOFFSET                        0x0
#define UART_IER_DLAB_0_0_IE_RXS_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_RXS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define UART_IER_DLAB_0_0_IE_RXS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_RXS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_RXS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_RXS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define UART_IER_DLAB_0_0_IE_RXS_DISABLE                        MK_ENUM_CONST(0)
#define UART_IER_DLAB_0_0_IE_RXS_ENABLE                 MK_ENUM_CONST(1)

#define UART_IER_DLAB_0_0_IE_THR_SHIFT                  MK_SHIFT_CONST(1)
#define UART_IER_DLAB_0_0_IE_THR_FIELD                  MK_FIELD_CONST(0x1, UART_IER_DLAB_0_0_IE_THR_SHIFT)
#define UART_IER_DLAB_0_0_IE_THR_RANGE                  1:1
#define UART_IER_DLAB_0_0_IE_THR_MSB                    MK_SHIFT_CONST(1)
#define UART_IER_DLAB_0_0_IE_THR_LSB                    MK_SHIFT_CONST(1)
#define UART_IER_DLAB_0_0_IE_THR_WOFFSET                        0x0
#define UART_IER_DLAB_0_0_IE_THR_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_THR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define UART_IER_DLAB_0_0_IE_THR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_THR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_THR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_THR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define UART_IER_DLAB_0_0_IE_THR_DISABLE                        MK_ENUM_CONST(0)
#define UART_IER_DLAB_0_0_IE_THR_ENABLE                 MK_ENUM_CONST(1)

#define UART_IER_DLAB_0_0_IE_RHR_SHIFT                  MK_SHIFT_CONST(0)
#define UART_IER_DLAB_0_0_IE_RHR_FIELD                  MK_FIELD_CONST(0x1, UART_IER_DLAB_0_0_IE_RHR_SHIFT)
#define UART_IER_DLAB_0_0_IE_RHR_RANGE                  0:0
#define UART_IER_DLAB_0_0_IE_RHR_MSB                    MK_SHIFT_CONST(0)
#define UART_IER_DLAB_0_0_IE_RHR_LSB                    MK_SHIFT_CONST(0)
#define UART_IER_DLAB_0_0_IE_RHR_WOFFSET                        0x0
#define UART_IER_DLAB_0_0_IE_RHR_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_RHR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define UART_IER_DLAB_0_0_IE_RHR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_RHR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_RHR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define UART_IER_DLAB_0_0_IE_RHR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define UART_IER_DLAB_0_0_IE_RHR_DISABLE                        MK_ENUM_CONST(0)
#define UART_IER_DLAB_0_0_IE_RHR_ENABLE                 MK_ENUM_CONST(1)


// Register UART_IIR_FCR_0
#define UART_IIR_FCR_0                  MK_ADDR_CONST(0x8)
#define UART_IIR_FCR_0_SECURE                   0x0
#define UART_IIR_FCR_0_DUAL                     0x0
#define UART_IIR_FCR_0_SCR                      0
#define UART_IIR_FCR_0_SCRREG                   0
#define UART_IIR_FCR_0_WORD_COUNT                       0x1
#define UART_IIR_FCR_0_RESET_VAL                        MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define UART_IIR_FCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_READ_MASK                        MK_MASK_CONST(0xcf)
#define UART_IIR_FCR_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define UART_IIR_FCR_0_EN_FIFO_SHIFT                    MK_SHIFT_CONST(6)
#define UART_IIR_FCR_0_EN_FIFO_FIELD                    MK_FIELD_CONST(0x3, UART_IIR_FCR_0_EN_FIFO_SHIFT)
#define UART_IIR_FCR_0_EN_FIFO_RANGE                    7:6
#define UART_IIR_FCR_0_EN_FIFO_MSB                      MK_SHIFT_CONST(7)
#define UART_IIR_FCR_0_EN_FIFO_LSB                      MK_SHIFT_CONST(6)
#define UART_IIR_FCR_0_EN_FIFO_WOFFSET                  0x0
#define UART_IIR_FCR_0_EN_FIFO_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_EN_FIFO_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define UART_IIR_FCR_0_EN_FIFO_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_EN_FIFO_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_EN_FIFO_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_EN_FIFO_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_EN_FIFO_MODE_16550                       MK_ENUM_CONST(1)
#define UART_IIR_FCR_0_EN_FIFO_MODE_16450                       MK_ENUM_CONST(0)

#define UART_IIR_FCR_0_IS_PRI2_SHIFT                    MK_SHIFT_CONST(3)
#define UART_IIR_FCR_0_IS_PRI2_FIELD                    MK_FIELD_CONST(0x1, UART_IIR_FCR_0_IS_PRI2_SHIFT)
#define UART_IIR_FCR_0_IS_PRI2_RANGE                    3:3
#define UART_IIR_FCR_0_IS_PRI2_MSB                      MK_SHIFT_CONST(3)
#define UART_IIR_FCR_0_IS_PRI2_LSB                      MK_SHIFT_CONST(3)
#define UART_IIR_FCR_0_IS_PRI2_WOFFSET                  0x0
#define UART_IIR_FCR_0_IS_PRI2_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_PRI2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_IS_PRI2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_PRI2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_PRI2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_PRI2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_IS_PRI2_DISABLE                  MK_ENUM_CONST(0)
#define UART_IIR_FCR_0_IS_PRI2_ENABLE                   MK_ENUM_CONST(1)

#define UART_IIR_FCR_0_IS_PRI1_SHIFT                    MK_SHIFT_CONST(2)
#define UART_IIR_FCR_0_IS_PRI1_FIELD                    MK_FIELD_CONST(0x1, UART_IIR_FCR_0_IS_PRI1_SHIFT)
#define UART_IIR_FCR_0_IS_PRI1_RANGE                    2:2
#define UART_IIR_FCR_0_IS_PRI1_MSB                      MK_SHIFT_CONST(2)
#define UART_IIR_FCR_0_IS_PRI1_LSB                      MK_SHIFT_CONST(2)
#define UART_IIR_FCR_0_IS_PRI1_WOFFSET                  0x0
#define UART_IIR_FCR_0_IS_PRI1_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_PRI1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_IS_PRI1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_PRI1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_PRI1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_PRI1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_IS_PRI1_DISABLE                  MK_ENUM_CONST(0)
#define UART_IIR_FCR_0_IS_PRI1_ENABLE                   MK_ENUM_CONST(1)

#define UART_IIR_FCR_0_IS_PRI0_SHIFT                    MK_SHIFT_CONST(1)
#define UART_IIR_FCR_0_IS_PRI0_FIELD                    MK_FIELD_CONST(0x1, UART_IIR_FCR_0_IS_PRI0_SHIFT)
#define UART_IIR_FCR_0_IS_PRI0_RANGE                    1:1
#define UART_IIR_FCR_0_IS_PRI0_MSB                      MK_SHIFT_CONST(1)
#define UART_IIR_FCR_0_IS_PRI0_LSB                      MK_SHIFT_CONST(1)
#define UART_IIR_FCR_0_IS_PRI0_WOFFSET                  0x0
#define UART_IIR_FCR_0_IS_PRI0_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_PRI0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_IS_PRI0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_PRI0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_PRI0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_PRI0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_IS_PRI0_DISABLE                  MK_ENUM_CONST(0)
#define UART_IIR_FCR_0_IS_PRI0_ENABLE                   MK_ENUM_CONST(1)

#define UART_IIR_FCR_0_IS_STA_SHIFT                     MK_SHIFT_CONST(0)
#define UART_IIR_FCR_0_IS_STA_FIELD                     MK_FIELD_CONST(0x1, UART_IIR_FCR_0_IS_STA_SHIFT)
#define UART_IIR_FCR_0_IS_STA_RANGE                     0:0
#define UART_IIR_FCR_0_IS_STA_MSB                       MK_SHIFT_CONST(0)
#define UART_IIR_FCR_0_IS_STA_LSB                       MK_SHIFT_CONST(0)
#define UART_IIR_FCR_0_IS_STA_WOFFSET                   0x0
#define UART_IIR_FCR_0_IS_STA_DEFAULT                   MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_IS_STA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_IS_STA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_STA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_STA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_IS_STA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_IS_STA_INTR_PEND                 MK_ENUM_CONST(0)
#define UART_IIR_FCR_0_IS_STA_NO_INTR_PEND                      MK_ENUM_CONST(1)

#define UART_IIR_FCR_0_RX_TRIG_SHIFT                    MK_SHIFT_CONST(6)
#define UART_IIR_FCR_0_RX_TRIG_FIELD                    MK_FIELD_CONST(0x3, UART_IIR_FCR_0_RX_TRIG_SHIFT)
#define UART_IIR_FCR_0_RX_TRIG_RANGE                    7:6
#define UART_IIR_FCR_0_RX_TRIG_MSB                      MK_SHIFT_CONST(7)
#define UART_IIR_FCR_0_RX_TRIG_LSB                      MK_SHIFT_CONST(6)
#define UART_IIR_FCR_0_RX_TRIG_WOFFSET                  0x0
#define UART_IIR_FCR_0_RX_TRIG_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_RX_TRIG_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define UART_IIR_FCR_0_RX_TRIG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_RX_TRIG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_RX_TRIG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_RX_TRIG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_1                     MK_ENUM_CONST(0)
#define UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_4                     MK_ENUM_CONST(1)
#define UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_8                     MK_ENUM_CONST(2)
#define UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_16                    MK_ENUM_CONST(3)

#define UART_IIR_FCR_0_TX_TRIG_SHIFT                    MK_SHIFT_CONST(4)
#define UART_IIR_FCR_0_TX_TRIG_FIELD                    MK_FIELD_CONST(0x3, UART_IIR_FCR_0_TX_TRIG_SHIFT)
#define UART_IIR_FCR_0_TX_TRIG_RANGE                    5:4
#define UART_IIR_FCR_0_TX_TRIG_MSB                      MK_SHIFT_CONST(5)
#define UART_IIR_FCR_0_TX_TRIG_LSB                      MK_SHIFT_CONST(4)
#define UART_IIR_FCR_0_TX_TRIG_WOFFSET                  0x0
#define UART_IIR_FCR_0_TX_TRIG_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_TX_TRIG_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define UART_IIR_FCR_0_TX_TRIG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_TX_TRIG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_TX_TRIG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_TX_TRIG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_16                    MK_ENUM_CONST(0)
#define UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_8                     MK_ENUM_CONST(1)
#define UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_4                     MK_ENUM_CONST(2)
#define UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_1                     MK_ENUM_CONST(3)

#define UART_IIR_FCR_0_DMA_SHIFT                        MK_SHIFT_CONST(3)
#define UART_IIR_FCR_0_DMA_FIELD                        MK_FIELD_CONST(0x1, UART_IIR_FCR_0_DMA_SHIFT)
#define UART_IIR_FCR_0_DMA_RANGE                        3:3
#define UART_IIR_FCR_0_DMA_MSB                  MK_SHIFT_CONST(3)
#define UART_IIR_FCR_0_DMA_LSB                  MK_SHIFT_CONST(3)
#define UART_IIR_FCR_0_DMA_WOFFSET                      0x0
#define UART_IIR_FCR_0_DMA_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_DMA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_DMA_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_DMA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_DMA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_DMA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_DMA_NO_CHANGE                    MK_ENUM_CONST(0)
#define UART_IIR_FCR_0_DMA_CHANGE                       MK_ENUM_CONST(1)

#define UART_IIR_FCR_0_TX_CLR_SHIFT                     MK_SHIFT_CONST(2)
#define UART_IIR_FCR_0_TX_CLR_FIELD                     MK_FIELD_CONST(0x1, UART_IIR_FCR_0_TX_CLR_SHIFT)
#define UART_IIR_FCR_0_TX_CLR_RANGE                     2:2
#define UART_IIR_FCR_0_TX_CLR_MSB                       MK_SHIFT_CONST(2)
#define UART_IIR_FCR_0_TX_CLR_LSB                       MK_SHIFT_CONST(2)
#define UART_IIR_FCR_0_TX_CLR_WOFFSET                   0x0
#define UART_IIR_FCR_0_TX_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_TX_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_TX_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_TX_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_TX_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_TX_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_TX_CLR_NO_CLEAR                  MK_ENUM_CONST(0)
#define UART_IIR_FCR_0_TX_CLR_CLEAR                     MK_ENUM_CONST(1)

#define UART_IIR_FCR_0_RX_CLR_SHIFT                     MK_SHIFT_CONST(1)
#define UART_IIR_FCR_0_RX_CLR_FIELD                     MK_FIELD_CONST(0x1, UART_IIR_FCR_0_RX_CLR_SHIFT)
#define UART_IIR_FCR_0_RX_CLR_RANGE                     1:1
#define UART_IIR_FCR_0_RX_CLR_MSB                       MK_SHIFT_CONST(1)
#define UART_IIR_FCR_0_RX_CLR_LSB                       MK_SHIFT_CONST(1)
#define UART_IIR_FCR_0_RX_CLR_WOFFSET                   0x0
#define UART_IIR_FCR_0_RX_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_RX_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_RX_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_RX_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_RX_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_RX_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_RX_CLR_NO_CLEAR                  MK_ENUM_CONST(0)
#define UART_IIR_FCR_0_RX_CLR_CLEAR                     MK_ENUM_CONST(1)

#define UART_IIR_FCR_0_FCR_EN_FIFO_SHIFT                        MK_SHIFT_CONST(0)
#define UART_IIR_FCR_0_FCR_EN_FIFO_FIELD                        MK_FIELD_CONST(0x1, UART_IIR_FCR_0_FCR_EN_FIFO_SHIFT)
#define UART_IIR_FCR_0_FCR_EN_FIFO_RANGE                        0:0
#define UART_IIR_FCR_0_FCR_EN_FIFO_MSB                  MK_SHIFT_CONST(0)
#define UART_IIR_FCR_0_FCR_EN_FIFO_LSB                  MK_SHIFT_CONST(0)
#define UART_IIR_FCR_0_FCR_EN_FIFO_WOFFSET                      0x0
#define UART_IIR_FCR_0_FCR_EN_FIFO_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_FCR_EN_FIFO_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_FCR_EN_FIFO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_FCR_EN_FIFO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_FCR_EN_FIFO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define UART_IIR_FCR_0_FCR_EN_FIFO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define UART_IIR_FCR_0_FCR_EN_FIFO_DISABLE                      MK_ENUM_CONST(0)
#define UART_IIR_FCR_0_FCR_EN_FIFO_ENABLE                       MK_ENUM_CONST(1)


// Register UART_LCR_0
#define UART_LCR_0                      MK_ADDR_CONST(0xc)
#define UART_LCR_0_SECURE                       0x0
#define UART_LCR_0_DUAL                         0x0
#define UART_LCR_0_SCR                  0
#define UART_LCR_0_SCRREG                       0
#define UART_LCR_0_WORD_COUNT                   0x1
#define UART_LCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define UART_LCR_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define UART_LCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define UART_LCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_LCR_0_READ_MASK                    MK_MASK_CONST(0xff)
#define UART_LCR_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define UART_LCR_0_DLAB_SHIFT                   MK_SHIFT_CONST(7)
#define UART_LCR_0_DLAB_FIELD                   MK_FIELD_CONST(0x1, UART_LCR_0_DLAB_SHIFT)
#define UART_LCR_0_DLAB_RANGE                   7:7
#define UART_LCR_0_DLAB_MSB                     MK_SHIFT_CONST(7)
#define UART_LCR_0_DLAB_LSB                     MK_SHIFT_CONST(7)
#define UART_LCR_0_DLAB_WOFFSET                 0x0
#define UART_LCR_0_DLAB_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_LCR_0_DLAB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_LCR_0_DLAB_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_LCR_0_DLAB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_LCR_0_DLAB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_LCR_0_DLAB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_LCR_0_DLAB_DISABLE                 MK_ENUM_CONST(0)
#define UART_LCR_0_DLAB_ENABLE                  MK_ENUM_CONST(1)

#define UART_LCR_0_SET_B_SHIFT                  MK_SHIFT_CONST(6)
#define UART_LCR_0_SET_B_FIELD                  MK_FIELD_CONST(0x1, UART_LCR_0_SET_B_SHIFT)
#define UART_LCR_0_SET_B_RANGE                  6:6
#define UART_LCR_0_SET_B_MSB                    MK_SHIFT_CONST(6)
#define UART_LCR_0_SET_B_LSB                    MK_SHIFT_CONST(6)
#define UART_LCR_0_SET_B_WOFFSET                        0x0
#define UART_LCR_0_SET_B_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_LCR_0_SET_B_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define UART_LCR_0_SET_B_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define UART_LCR_0_SET_B_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define UART_LCR_0_SET_B_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define UART_LCR_0_SET_B_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define UART_LCR_0_SET_B_NO_BREAK                       MK_ENUM_CONST(0)
#define UART_LCR_0_SET_B_BREAK                  MK_ENUM_CONST(1)

#define UART_LCR_0_SET_P_SHIFT                  MK_SHIFT_CONST(5)
#define UART_LCR_0_SET_P_FIELD                  MK_FIELD_CONST(0x1, UART_LCR_0_SET_P_SHIFT)
#define UART_LCR_0_SET_P_RANGE                  5:5
#define UART_LCR_0_SET_P_MSB                    MK_SHIFT_CONST(5)
#define UART_LCR_0_SET_P_LSB                    MK_SHIFT_CONST(5)
#define UART_LCR_0_SET_P_WOFFSET                        0x0
#define UART_LCR_0_SET_P_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_LCR_0_SET_P_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define UART_LCR_0_SET_P_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define UART_LCR_0_SET_P_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define UART_LCR_0_SET_P_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define UART_LCR_0_SET_P_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define UART_LCR_0_SET_P_NO_PARITY                      MK_ENUM_CONST(0)
#define UART_LCR_0_SET_P_PARITY                 MK_ENUM_CONST(1)

#define UART_LCR_0_EVEN_SHIFT                   MK_SHIFT_CONST(4)
#define UART_LCR_0_EVEN_FIELD                   MK_FIELD_CONST(0x1, UART_LCR_0_EVEN_SHIFT)
#define UART_LCR_0_EVEN_RANGE                   4:4
#define UART_LCR_0_EVEN_MSB                     MK_SHIFT_CONST(4)
#define UART_LCR_0_EVEN_LSB                     MK_SHIFT_CONST(4)
#define UART_LCR_0_EVEN_WOFFSET                 0x0
#define UART_LCR_0_EVEN_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_LCR_0_EVEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_LCR_0_EVEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_LCR_0_EVEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_LCR_0_EVEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_LCR_0_EVEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_LCR_0_EVEN_DISABLE                 MK_ENUM_CONST(0)
#define UART_LCR_0_EVEN_ENABLE                  MK_ENUM_CONST(1)

#define UART_LCR_0_PAR_SHIFT                    MK_SHIFT_CONST(3)
#define UART_LCR_0_PAR_FIELD                    MK_FIELD_CONST(0x1, UART_LCR_0_PAR_SHIFT)
#define UART_LCR_0_PAR_RANGE                    3:3
#define UART_LCR_0_PAR_MSB                      MK_SHIFT_CONST(3)
#define UART_LCR_0_PAR_LSB                      MK_SHIFT_CONST(3)
#define UART_LCR_0_PAR_WOFFSET                  0x0
#define UART_LCR_0_PAR_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_LCR_0_PAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_LCR_0_PAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_LCR_0_PAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_LCR_0_PAR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_LCR_0_PAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_LCR_0_PAR_NO_PARITY                        MK_ENUM_CONST(0)
#define UART_LCR_0_PAR_PARITY                   MK_ENUM_CONST(1)

#define UART_LCR_0_STOP_SHIFT                   MK_SHIFT_CONST(2)
#define UART_LCR_0_STOP_FIELD                   MK_FIELD_CONST(0x1, UART_LCR_0_STOP_SHIFT)
#define UART_LCR_0_STOP_RANGE                   2:2
#define UART_LCR_0_STOP_MSB                     MK_SHIFT_CONST(2)
#define UART_LCR_0_STOP_LSB                     MK_SHIFT_CONST(2)
#define UART_LCR_0_STOP_WOFFSET                 0x0
#define UART_LCR_0_STOP_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_LCR_0_STOP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_LCR_0_STOP_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_LCR_0_STOP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_LCR_0_STOP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_LCR_0_STOP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_LCR_0_STOP_DISABLE                 MK_ENUM_CONST(0)
#define UART_LCR_0_STOP_ENABLE                  MK_ENUM_CONST(1)

#define UART_LCR_0_WD_SIZE_SHIFT                        MK_SHIFT_CONST(0)
#define UART_LCR_0_WD_SIZE_FIELD                        MK_FIELD_CONST(0x3, UART_LCR_0_WD_SIZE_SHIFT)
#define UART_LCR_0_WD_SIZE_RANGE                        1:0
#define UART_LCR_0_WD_SIZE_MSB                  MK_SHIFT_CONST(1)
#define UART_LCR_0_WD_SIZE_LSB                  MK_SHIFT_CONST(0)
#define UART_LCR_0_WD_SIZE_WOFFSET                      0x0
#define UART_LCR_0_WD_SIZE_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_LCR_0_WD_SIZE_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define UART_LCR_0_WD_SIZE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_LCR_0_WD_SIZE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_LCR_0_WD_SIZE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define UART_LCR_0_WD_SIZE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define UART_LCR_0_WD_SIZE_WORD_LENGTH_5                        MK_ENUM_CONST(0)
#define UART_LCR_0_WD_SIZE_WORD_LENGTH_6                        MK_ENUM_CONST(1)
#define UART_LCR_0_WD_SIZE_WORD_LENGTH_7                        MK_ENUM_CONST(2)
#define UART_LCR_0_WD_SIZE_WORD_LENGTH_8                        MK_ENUM_CONST(3)


// Register UART_MCR_0
#define UART_MCR_0                      MK_ADDR_CONST(0x10)
#define UART_MCR_0_SECURE                       0x0
#define UART_MCR_0_DUAL                         0x0
#define UART_MCR_0_SCR                  0
#define UART_MCR_0_SCRREG                       0
#define UART_MCR_0_WORD_COUNT                   0x1
#define UART_MCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define UART_MCR_0_RESET_MASK                   MK_MASK_CONST(0x7ff)
#define UART_MCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define UART_MCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_MCR_0_READ_MASK                    MK_MASK_CONST(0x7ff)
#define UART_MCR_0_WRITE_MASK                   MK_MASK_CONST(0x7ff)
#define UART_MCR_0_OLD_SIR_DECODE_SHIFT                 MK_SHIFT_CONST(10)
#define UART_MCR_0_OLD_SIR_DECODE_FIELD                 MK_FIELD_CONST(0x1, UART_MCR_0_OLD_SIR_DECODE_SHIFT)
#define UART_MCR_0_OLD_SIR_DECODE_RANGE                 10:10
#define UART_MCR_0_OLD_SIR_DECODE_MSB                   MK_SHIFT_CONST(10)
#define UART_MCR_0_OLD_SIR_DECODE_LSB                   MK_SHIFT_CONST(10)
#define UART_MCR_0_OLD_SIR_DECODE_WOFFSET                       0x0
#define UART_MCR_0_OLD_SIR_DECODE_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_MCR_0_OLD_SIR_DECODE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define UART_MCR_0_OLD_SIR_DECODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define UART_MCR_0_OLD_SIR_DECODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define UART_MCR_0_OLD_SIR_DECODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define UART_MCR_0_OLD_SIR_DECODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define UART_MCR_0_OLD_SIR_DECODE_DISABLE                       MK_ENUM_CONST(0)
#define UART_MCR_0_OLD_SIR_DECODE_ENABLE                        MK_ENUM_CONST(1)

#define UART_MCR_0_RI_POLARITY_SHIFT                    MK_SHIFT_CONST(8)
#define UART_MCR_0_RI_POLARITY_FIELD                    MK_FIELD_CONST(0x3, UART_MCR_0_RI_POLARITY_SHIFT)
#define UART_MCR_0_RI_POLARITY_RANGE                    9:8
#define UART_MCR_0_RI_POLARITY_MSB                      MK_SHIFT_CONST(9)
#define UART_MCR_0_RI_POLARITY_LSB                      MK_SHIFT_CONST(8)
#define UART_MCR_0_RI_POLARITY_WOFFSET                  0x0
#define UART_MCR_0_RI_POLARITY_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_MCR_0_RI_POLARITY_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define UART_MCR_0_RI_POLARITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_MCR_0_RI_POLARITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_MCR_0_RI_POLARITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_MCR_0_RI_POLARITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_MCR_0_RI_POLARITY_LOW_TO_HIGH                      MK_ENUM_CONST(0)
#define UART_MCR_0_RI_POLARITY_HIGH_TO_LOW                      MK_ENUM_CONST(1)
#define UART_MCR_0_RI_POLARITY_BOTH_EDGES                       MK_ENUM_CONST(2)
#define UART_MCR_0_RI_POLARITY_RSVD                     MK_ENUM_CONST(3)

#define UART_MCR_0_DEL_QUAL_CTS_EN_SHIFT                        MK_SHIFT_CONST(7)
#define UART_MCR_0_DEL_QUAL_CTS_EN_FIELD                        MK_FIELD_CONST(0x1, UART_MCR_0_DEL_QUAL_CTS_EN_SHIFT)
#define UART_MCR_0_DEL_QUAL_CTS_EN_RANGE                        7:7
#define UART_MCR_0_DEL_QUAL_CTS_EN_MSB                  MK_SHIFT_CONST(7)
#define UART_MCR_0_DEL_QUAL_CTS_EN_LSB                  MK_SHIFT_CONST(7)
#define UART_MCR_0_DEL_QUAL_CTS_EN_WOFFSET                      0x0
#define UART_MCR_0_DEL_QUAL_CTS_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_MCR_0_DEL_QUAL_CTS_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define UART_MCR_0_DEL_QUAL_CTS_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_MCR_0_DEL_QUAL_CTS_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_MCR_0_DEL_QUAL_CTS_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define UART_MCR_0_DEL_QUAL_CTS_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define UART_MCR_0_DEL_QUAL_CTS_EN_DISABLE                      MK_ENUM_CONST(0)
#define UART_MCR_0_DEL_QUAL_CTS_EN_ENABLE                       MK_ENUM_CONST(1)

#define UART_MCR_0_RTS_EN_SHIFT                 MK_SHIFT_CONST(6)
#define UART_MCR_0_RTS_EN_FIELD                 MK_FIELD_CONST(0x1, UART_MCR_0_RTS_EN_SHIFT)
#define UART_MCR_0_RTS_EN_RANGE                 6:6
#define UART_MCR_0_RTS_EN_MSB                   MK_SHIFT_CONST(6)
#define UART_MCR_0_RTS_EN_LSB                   MK_SHIFT_CONST(6)
#define UART_MCR_0_RTS_EN_WOFFSET                       0x0
#define UART_MCR_0_RTS_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_MCR_0_RTS_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define UART_MCR_0_RTS_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define UART_MCR_0_RTS_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define UART_MCR_0_RTS_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define UART_MCR_0_RTS_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define UART_MCR_0_RTS_EN_DISABLE                       MK_ENUM_CONST(0)
#define UART_MCR_0_RTS_EN_ENABLE                        MK_ENUM_CONST(1)

#define UART_MCR_0_CTS_EN_SHIFT                 MK_SHIFT_CONST(5)
#define UART_MCR_0_CTS_EN_FIELD                 MK_FIELD_CONST(0x1, UART_MCR_0_CTS_EN_SHIFT)
#define UART_MCR_0_CTS_EN_RANGE                 5:5
#define UART_MCR_0_CTS_EN_MSB                   MK_SHIFT_CONST(5)
#define UART_MCR_0_CTS_EN_LSB                   MK_SHIFT_CONST(5)
#define UART_MCR_0_CTS_EN_WOFFSET                       0x0
#define UART_MCR_0_CTS_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_MCR_0_CTS_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define UART_MCR_0_CTS_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define UART_MCR_0_CTS_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define UART_MCR_0_CTS_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define UART_MCR_0_CTS_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define UART_MCR_0_CTS_EN_DISABLE                       MK_ENUM_CONST(0)
#define UART_MCR_0_CTS_EN_ENABLE                        MK_ENUM_CONST(1)

#define UART_MCR_0_LOOPBK_SHIFT                 MK_SHIFT_CONST(4)
#define UART_MCR_0_LOOPBK_FIELD                 MK_FIELD_CONST(0x1, UART_MCR_0_LOOPBK_SHIFT)
#define UART_MCR_0_LOOPBK_RANGE                 4:4
#define UART_MCR_0_LOOPBK_MSB                   MK_SHIFT_CONST(4)
#define UART_MCR_0_LOOPBK_LSB                   MK_SHIFT_CONST(4)
#define UART_MCR_0_LOOPBK_WOFFSET                       0x0
#define UART_MCR_0_LOOPBK_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_MCR_0_LOOPBK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define UART_MCR_0_LOOPBK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define UART_MCR_0_LOOPBK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define UART_MCR_0_LOOPBK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define UART_MCR_0_LOOPBK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define UART_MCR_0_LOOPBK_DISABLE                       MK_ENUM_CONST(0)
#define UART_MCR_0_LOOPBK_ENABLE                        MK_ENUM_CONST(1)

#define UART_MCR_0_OUT2_SHIFT                   MK_SHIFT_CONST(3)
#define UART_MCR_0_OUT2_FIELD                   MK_FIELD_CONST(0x1, UART_MCR_0_OUT2_SHIFT)
#define UART_MCR_0_OUT2_RANGE                   3:3
#define UART_MCR_0_OUT2_MSB                     MK_SHIFT_CONST(3)
#define UART_MCR_0_OUT2_LSB                     MK_SHIFT_CONST(3)
#define UART_MCR_0_OUT2_WOFFSET                 0x0
#define UART_MCR_0_OUT2_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_MCR_0_OUT2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_MCR_0_OUT2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_MCR_0_OUT2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_MCR_0_OUT2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_MCR_0_OUT2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_MCR_0_OUT2_DISABLE                 MK_ENUM_CONST(0)
#define UART_MCR_0_OUT2_ENABLE                  MK_ENUM_CONST(1)

#define UART_MCR_0_OUT1_SHIFT                   MK_SHIFT_CONST(2)
#define UART_MCR_0_OUT1_FIELD                   MK_FIELD_CONST(0x1, UART_MCR_0_OUT1_SHIFT)
#define UART_MCR_0_OUT1_RANGE                   2:2
#define UART_MCR_0_OUT1_MSB                     MK_SHIFT_CONST(2)
#define UART_MCR_0_OUT1_LSB                     MK_SHIFT_CONST(2)
#define UART_MCR_0_OUT1_WOFFSET                 0x0
#define UART_MCR_0_OUT1_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_MCR_0_OUT1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_MCR_0_OUT1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_MCR_0_OUT1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_MCR_0_OUT1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_MCR_0_OUT1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_MCR_0_OUT1_DISABLE                 MK_ENUM_CONST(0)
#define UART_MCR_0_OUT1_ENABLE                  MK_ENUM_CONST(1)

#define UART_MCR_0_RTS_SHIFT                    MK_SHIFT_CONST(1)
#define UART_MCR_0_RTS_FIELD                    MK_FIELD_CONST(0x1, UART_MCR_0_RTS_SHIFT)
#define UART_MCR_0_RTS_RANGE                    1:1
#define UART_MCR_0_RTS_MSB                      MK_SHIFT_CONST(1)
#define UART_MCR_0_RTS_LSB                      MK_SHIFT_CONST(1)
#define UART_MCR_0_RTS_WOFFSET                  0x0
#define UART_MCR_0_RTS_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_MCR_0_RTS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_MCR_0_RTS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_MCR_0_RTS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_MCR_0_RTS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_MCR_0_RTS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_MCR_0_RTS_FORCE_RTS_HI                     MK_ENUM_CONST(0)
#define UART_MCR_0_RTS_FORCE_RTS_LOW                    MK_ENUM_CONST(1)

#define UART_MCR_0_DTR_SHIFT                    MK_SHIFT_CONST(0)
#define UART_MCR_0_DTR_FIELD                    MK_FIELD_CONST(0x1, UART_MCR_0_DTR_SHIFT)
#define UART_MCR_0_DTR_RANGE                    0:0
#define UART_MCR_0_DTR_MSB                      MK_SHIFT_CONST(0)
#define UART_MCR_0_DTR_LSB                      MK_SHIFT_CONST(0)
#define UART_MCR_0_DTR_WOFFSET                  0x0
#define UART_MCR_0_DTR_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_MCR_0_DTR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_MCR_0_DTR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_MCR_0_DTR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_MCR_0_DTR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_MCR_0_DTR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_MCR_0_DTR_FORCE_DTR_HI                     MK_ENUM_CONST(0)
#define UART_MCR_0_DTR_FORCE_DTR_LOW                    MK_ENUM_CONST(1)


// Register UART_LSR_0
#define UART_LSR_0                      MK_ADDR_CONST(0x14)
#define UART_LSR_0_SECURE                       0x0
#define UART_LSR_0_DUAL                         0x0
#define UART_LSR_0_SCR                  0
#define UART_LSR_0_SCRREG                       0
#define UART_LSR_0_WORD_COUNT                   0x1
#define UART_LSR_0_RESET_VAL                    MK_MASK_CONST(0x260)
#define UART_LSR_0_RESET_MASK                   MK_MASK_CONST(0x3ff)
#define UART_LSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define UART_LSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_LSR_0_READ_MASK                    MK_MASK_CONST(0x3ff)
#define UART_LSR_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define UART_LSR_0_RX_FIFO_EMPTY_SHIFT                  MK_SHIFT_CONST(9)
#define UART_LSR_0_RX_FIFO_EMPTY_FIELD                  MK_FIELD_CONST(0x1, UART_LSR_0_RX_FIFO_EMPTY_SHIFT)
#define UART_LSR_0_RX_FIFO_EMPTY_RANGE                  9:9
#define UART_LSR_0_RX_FIFO_EMPTY_MSB                    MK_SHIFT_CONST(9)
#define UART_LSR_0_RX_FIFO_EMPTY_LSB                    MK_SHIFT_CONST(9)
#define UART_LSR_0_RX_FIFO_EMPTY_WOFFSET                        0x0
#define UART_LSR_0_RX_FIFO_EMPTY_DEFAULT                        MK_MASK_CONST(0x1)
#define UART_LSR_0_RX_FIFO_EMPTY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define UART_LSR_0_RX_FIFO_EMPTY_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define UART_LSR_0_RX_FIFO_EMPTY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define UART_LSR_0_RX_FIFO_EMPTY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define UART_LSR_0_RX_FIFO_EMPTY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define UART_LSR_0_RX_FIFO_EMPTY_NOT_EMPTY                      MK_ENUM_CONST(0)
#define UART_LSR_0_RX_FIFO_EMPTY_EMPTY                  MK_ENUM_CONST(1)

#define UART_LSR_0_TX_FIFO_FULL_SHIFT                   MK_SHIFT_CONST(8)
#define UART_LSR_0_TX_FIFO_FULL_FIELD                   MK_FIELD_CONST(0x1, UART_LSR_0_TX_FIFO_FULL_SHIFT)
#define UART_LSR_0_TX_FIFO_FULL_RANGE                   8:8
#define UART_LSR_0_TX_FIFO_FULL_MSB                     MK_SHIFT_CONST(8)
#define UART_LSR_0_TX_FIFO_FULL_LSB                     MK_SHIFT_CONST(8)
#define UART_LSR_0_TX_FIFO_FULL_WOFFSET                 0x0
#define UART_LSR_0_TX_FIFO_FULL_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_LSR_0_TX_FIFO_FULL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_LSR_0_TX_FIFO_FULL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_LSR_0_TX_FIFO_FULL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_LSR_0_TX_FIFO_FULL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_LSR_0_TX_FIFO_FULL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_LSR_0_TX_FIFO_FULL_NOT_FULL                        MK_ENUM_CONST(0)
#define UART_LSR_0_TX_FIFO_FULL_FULL                    MK_ENUM_CONST(1)

#define UART_LSR_0_FIFOE_SHIFT                  MK_SHIFT_CONST(7)
#define UART_LSR_0_FIFOE_FIELD                  MK_FIELD_CONST(0x1, UART_LSR_0_FIFOE_SHIFT)
#define UART_LSR_0_FIFOE_RANGE                  7:7
#define UART_LSR_0_FIFOE_MSB                    MK_SHIFT_CONST(7)
#define UART_LSR_0_FIFOE_LSB                    MK_SHIFT_CONST(7)
#define UART_LSR_0_FIFOE_WOFFSET                        0x0
#define UART_LSR_0_FIFOE_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_LSR_0_FIFOE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define UART_LSR_0_FIFOE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define UART_LSR_0_FIFOE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define UART_LSR_0_FIFOE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define UART_LSR_0_FIFOE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define UART_LSR_0_FIFOE_NO_ERR                 MK_ENUM_CONST(0)
#define UART_LSR_0_FIFOE_ERR                    MK_ENUM_CONST(1)

#define UART_LSR_0_TMTY_SHIFT                   MK_SHIFT_CONST(6)
#define UART_LSR_0_TMTY_FIELD                   MK_FIELD_CONST(0x1, UART_LSR_0_TMTY_SHIFT)
#define UART_LSR_0_TMTY_RANGE                   6:6
#define UART_LSR_0_TMTY_MSB                     MK_SHIFT_CONST(6)
#define UART_LSR_0_TMTY_LSB                     MK_SHIFT_CONST(6)
#define UART_LSR_0_TMTY_WOFFSET                 0x0
#define UART_LSR_0_TMTY_DEFAULT                 MK_MASK_CONST(0x1)
#define UART_LSR_0_TMTY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_LSR_0_TMTY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_LSR_0_TMTY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_LSR_0_TMTY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_LSR_0_TMTY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_LSR_0_TMTY_NO_EMPTY                        MK_ENUM_CONST(0)
#define UART_LSR_0_TMTY_EMPTY                   MK_ENUM_CONST(1)

#define UART_LSR_0_THRE_SHIFT                   MK_SHIFT_CONST(5)
#define UART_LSR_0_THRE_FIELD                   MK_FIELD_CONST(0x1, UART_LSR_0_THRE_SHIFT)
#define UART_LSR_0_THRE_RANGE                   5:5
#define UART_LSR_0_THRE_MSB                     MK_SHIFT_CONST(5)
#define UART_LSR_0_THRE_LSB                     MK_SHIFT_CONST(5)
#define UART_LSR_0_THRE_WOFFSET                 0x0
#define UART_LSR_0_THRE_DEFAULT                 MK_MASK_CONST(0x1)
#define UART_LSR_0_THRE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_LSR_0_THRE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_LSR_0_THRE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_LSR_0_THRE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_LSR_0_THRE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_LSR_0_THRE_FULL                    MK_ENUM_CONST(0)
#define UART_LSR_0_THRE_EMPTY                   MK_ENUM_CONST(1)

#define UART_LSR_0_BRK_SHIFT                    MK_SHIFT_CONST(4)
#define UART_LSR_0_BRK_FIELD                    MK_FIELD_CONST(0x1, UART_LSR_0_BRK_SHIFT)
#define UART_LSR_0_BRK_RANGE                    4:4
#define UART_LSR_0_BRK_MSB                      MK_SHIFT_CONST(4)
#define UART_LSR_0_BRK_LSB                      MK_SHIFT_CONST(4)
#define UART_LSR_0_BRK_WOFFSET                  0x0
#define UART_LSR_0_BRK_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_LSR_0_BRK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_LSR_0_BRK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_LSR_0_BRK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_LSR_0_BRK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_LSR_0_BRK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_LSR_0_BRK_NO_BREAK                 MK_ENUM_CONST(0)
#define UART_LSR_0_BRK_BREAK                    MK_ENUM_CONST(1)

#define UART_LSR_0_FERR_SHIFT                   MK_SHIFT_CONST(3)
#define UART_LSR_0_FERR_FIELD                   MK_FIELD_CONST(0x1, UART_LSR_0_FERR_SHIFT)
#define UART_LSR_0_FERR_RANGE                   3:3
#define UART_LSR_0_FERR_MSB                     MK_SHIFT_CONST(3)
#define UART_LSR_0_FERR_LSB                     MK_SHIFT_CONST(3)
#define UART_LSR_0_FERR_WOFFSET                 0x0
#define UART_LSR_0_FERR_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_LSR_0_FERR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_LSR_0_FERR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_LSR_0_FERR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_LSR_0_FERR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_LSR_0_FERR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_LSR_0_FERR_NO_FRAME_ERR                    MK_ENUM_CONST(0)
#define UART_LSR_0_FERR_FRAME_ERR                       MK_ENUM_CONST(1)

#define UART_LSR_0_PERR_SHIFT                   MK_SHIFT_CONST(2)
#define UART_LSR_0_PERR_FIELD                   MK_FIELD_CONST(0x1, UART_LSR_0_PERR_SHIFT)
#define UART_LSR_0_PERR_RANGE                   2:2
#define UART_LSR_0_PERR_MSB                     MK_SHIFT_CONST(2)
#define UART_LSR_0_PERR_LSB                     MK_SHIFT_CONST(2)
#define UART_LSR_0_PERR_WOFFSET                 0x0
#define UART_LSR_0_PERR_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_LSR_0_PERR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_LSR_0_PERR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_LSR_0_PERR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_LSR_0_PERR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_LSR_0_PERR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_LSR_0_PERR_NO_PARITY_ERR                   MK_ENUM_CONST(0)
#define UART_LSR_0_PERR_PARITY_ERR                      MK_ENUM_CONST(1)

#define UART_LSR_0_OVRF_SHIFT                   MK_SHIFT_CONST(1)
#define UART_LSR_0_OVRF_FIELD                   MK_FIELD_CONST(0x1, UART_LSR_0_OVRF_SHIFT)
#define UART_LSR_0_OVRF_RANGE                   1:1
#define UART_LSR_0_OVRF_MSB                     MK_SHIFT_CONST(1)
#define UART_LSR_0_OVRF_LSB                     MK_SHIFT_CONST(1)
#define UART_LSR_0_OVRF_WOFFSET                 0x0
#define UART_LSR_0_OVRF_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_LSR_0_OVRF_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_LSR_0_OVRF_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_LSR_0_OVRF_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_LSR_0_OVRF_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_LSR_0_OVRF_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_LSR_0_OVRF_NO_OVERRUN_ERROR                        MK_ENUM_CONST(0)
#define UART_LSR_0_OVRF_OVERRUN_ERROR                   MK_ENUM_CONST(1)

#define UART_LSR_0_RDR_SHIFT                    MK_SHIFT_CONST(0)
#define UART_LSR_0_RDR_FIELD                    MK_FIELD_CONST(0x1, UART_LSR_0_RDR_SHIFT)
#define UART_LSR_0_RDR_RANGE                    0:0
#define UART_LSR_0_RDR_MSB                      MK_SHIFT_CONST(0)
#define UART_LSR_0_RDR_LSB                      MK_SHIFT_CONST(0)
#define UART_LSR_0_RDR_WOFFSET                  0x0
#define UART_LSR_0_RDR_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_LSR_0_RDR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_LSR_0_RDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_LSR_0_RDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_LSR_0_RDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_LSR_0_RDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_LSR_0_RDR_NO_DATA_IN_FIFO                  MK_ENUM_CONST(0)
#define UART_LSR_0_RDR_DATA_IN_FIFO                     MK_ENUM_CONST(1)


// Register UART_MSR_0
#define UART_MSR_0                      MK_ADDR_CONST(0x18)
#define UART_MSR_0_SECURE                       0x0
#define UART_MSR_0_DUAL                         0x0
#define UART_MSR_0_SCR                  0
#define UART_MSR_0_SCRREG                       0
#define UART_MSR_0_WORD_COUNT                   0x1
#define UART_MSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define UART_MSR_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define UART_MSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define UART_MSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_MSR_0_READ_MASK                    MK_MASK_CONST(0xff)
#define UART_MSR_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define UART_MSR_0_CD_SHIFT                     MK_SHIFT_CONST(7)
#define UART_MSR_0_CD_FIELD                     MK_FIELD_CONST(0x1, UART_MSR_0_CD_SHIFT)
#define UART_MSR_0_CD_RANGE                     7:7
#define UART_MSR_0_CD_MSB                       MK_SHIFT_CONST(7)
#define UART_MSR_0_CD_LSB                       MK_SHIFT_CONST(7)
#define UART_MSR_0_CD_WOFFSET                   0x0
#define UART_MSR_0_CD_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_MSR_0_CD_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define UART_MSR_0_CD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_MSR_0_CD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define UART_MSR_0_CD_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define UART_MSR_0_CD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define UART_MSR_0_CD_DISABLE                   MK_ENUM_CONST(0)
#define UART_MSR_0_CD_ENABLE                    MK_ENUM_CONST(1)

#define UART_MSR_0_RI_SHIFT                     MK_SHIFT_CONST(6)
#define UART_MSR_0_RI_FIELD                     MK_FIELD_CONST(0x1, UART_MSR_0_RI_SHIFT)
#define UART_MSR_0_RI_RANGE                     6:6
#define UART_MSR_0_RI_MSB                       MK_SHIFT_CONST(6)
#define UART_MSR_0_RI_LSB                       MK_SHIFT_CONST(6)
#define UART_MSR_0_RI_WOFFSET                   0x0
#define UART_MSR_0_RI_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_MSR_0_RI_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define UART_MSR_0_RI_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_MSR_0_RI_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define UART_MSR_0_RI_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define UART_MSR_0_RI_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define UART_MSR_0_RI_DISABLE                   MK_ENUM_CONST(0)
#define UART_MSR_0_RI_ENABLE                    MK_ENUM_CONST(1)

#define UART_MSR_0_DSR_SHIFT                    MK_SHIFT_CONST(5)
#define UART_MSR_0_DSR_FIELD                    MK_FIELD_CONST(0x1, UART_MSR_0_DSR_SHIFT)
#define UART_MSR_0_DSR_RANGE                    5:5
#define UART_MSR_0_DSR_MSB                      MK_SHIFT_CONST(5)
#define UART_MSR_0_DSR_LSB                      MK_SHIFT_CONST(5)
#define UART_MSR_0_DSR_WOFFSET                  0x0
#define UART_MSR_0_DSR_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_MSR_0_DSR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_MSR_0_DSR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_MSR_0_DSR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_MSR_0_DSR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_MSR_0_DSR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_MSR_0_DSR_DISABLE                  MK_ENUM_CONST(0)
#define UART_MSR_0_DSR_ENABLE                   MK_ENUM_CONST(1)

#define UART_MSR_0_CTS_SHIFT                    MK_SHIFT_CONST(4)
#define UART_MSR_0_CTS_FIELD                    MK_FIELD_CONST(0x1, UART_MSR_0_CTS_SHIFT)
#define UART_MSR_0_CTS_RANGE                    4:4
#define UART_MSR_0_CTS_MSB                      MK_SHIFT_CONST(4)
#define UART_MSR_0_CTS_LSB                      MK_SHIFT_CONST(4)
#define UART_MSR_0_CTS_WOFFSET                  0x0
#define UART_MSR_0_CTS_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_MSR_0_CTS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_MSR_0_CTS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_MSR_0_CTS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_MSR_0_CTS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_MSR_0_CTS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_MSR_0_CTS_DISABLE                  MK_ENUM_CONST(0)
#define UART_MSR_0_CTS_ENABLE                   MK_ENUM_CONST(1)

#define UART_MSR_0_DCD_SHIFT                    MK_SHIFT_CONST(3)
#define UART_MSR_0_DCD_FIELD                    MK_FIELD_CONST(0x1, UART_MSR_0_DCD_SHIFT)
#define UART_MSR_0_DCD_RANGE                    3:3
#define UART_MSR_0_DCD_MSB                      MK_SHIFT_CONST(3)
#define UART_MSR_0_DCD_LSB                      MK_SHIFT_CONST(3)
#define UART_MSR_0_DCD_WOFFSET                  0x0
#define UART_MSR_0_DCD_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_MSR_0_DCD_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_MSR_0_DCD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_MSR_0_DCD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_MSR_0_DCD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_MSR_0_DCD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_MSR_0_DCD_DISABLE                  MK_ENUM_CONST(0)
#define UART_MSR_0_DCD_ENABLE                   MK_ENUM_CONST(1)

#define UART_MSR_0_DRI_SHIFT                    MK_SHIFT_CONST(2)
#define UART_MSR_0_DRI_FIELD                    MK_FIELD_CONST(0x1, UART_MSR_0_DRI_SHIFT)
#define UART_MSR_0_DRI_RANGE                    2:2
#define UART_MSR_0_DRI_MSB                      MK_SHIFT_CONST(2)
#define UART_MSR_0_DRI_LSB                      MK_SHIFT_CONST(2)
#define UART_MSR_0_DRI_WOFFSET                  0x0
#define UART_MSR_0_DRI_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_MSR_0_DRI_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_MSR_0_DRI_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_MSR_0_DRI_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_MSR_0_DRI_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_MSR_0_DRI_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_MSR_0_DRI_DISABLE                  MK_ENUM_CONST(0)
#define UART_MSR_0_DRI_ENABLE                   MK_ENUM_CONST(1)

#define UART_MSR_0_DDSR_SHIFT                   MK_SHIFT_CONST(1)
#define UART_MSR_0_DDSR_FIELD                   MK_FIELD_CONST(0x1, UART_MSR_0_DDSR_SHIFT)
#define UART_MSR_0_DDSR_RANGE                   1:1
#define UART_MSR_0_DDSR_MSB                     MK_SHIFT_CONST(1)
#define UART_MSR_0_DDSR_LSB                     MK_SHIFT_CONST(1)
#define UART_MSR_0_DDSR_WOFFSET                 0x0
#define UART_MSR_0_DDSR_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_MSR_0_DDSR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_MSR_0_DDSR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_MSR_0_DDSR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_MSR_0_DDSR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_MSR_0_DDSR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_MSR_0_DDSR_DISABLE                 MK_ENUM_CONST(0)
#define UART_MSR_0_DDSR_ENABLE                  MK_ENUM_CONST(1)

#define UART_MSR_0_DCTS_SHIFT                   MK_SHIFT_CONST(0)
#define UART_MSR_0_DCTS_FIELD                   MK_FIELD_CONST(0x1, UART_MSR_0_DCTS_SHIFT)
#define UART_MSR_0_DCTS_RANGE                   0:0
#define UART_MSR_0_DCTS_MSB                     MK_SHIFT_CONST(0)
#define UART_MSR_0_DCTS_LSB                     MK_SHIFT_CONST(0)
#define UART_MSR_0_DCTS_WOFFSET                 0x0
#define UART_MSR_0_DCTS_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_MSR_0_DCTS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_MSR_0_DCTS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_MSR_0_DCTS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_MSR_0_DCTS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_MSR_0_DCTS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_MSR_0_DCTS_DISABLE                 MK_ENUM_CONST(0)
#define UART_MSR_0_DCTS_ENABLE                  MK_ENUM_CONST(1)


// Register UART_SPR_0
#define UART_SPR_0                      MK_ADDR_CONST(0x1c)
#define UART_SPR_0_SECURE                       0x0
#define UART_SPR_0_DUAL                         0x0
#define UART_SPR_0_SCR                  0
#define UART_SPR_0_SCRREG                       0
#define UART_SPR_0_WORD_COUNT                   0x1
#define UART_SPR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define UART_SPR_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define UART_SPR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define UART_SPR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_SPR_0_READ_MASK                    MK_MASK_CONST(0xff)
#define UART_SPR_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define UART_SPR_0_SPR_A_SHIFT                  MK_SHIFT_CONST(0)
#define UART_SPR_0_SPR_A_FIELD                  MK_FIELD_CONST(0xff, UART_SPR_0_SPR_A_SHIFT)
#define UART_SPR_0_SPR_A_RANGE                  7:0
#define UART_SPR_0_SPR_A_MSB                    MK_SHIFT_CONST(7)
#define UART_SPR_0_SPR_A_LSB                    MK_SHIFT_CONST(0)
#define UART_SPR_0_SPR_A_WOFFSET                        0x0
#define UART_SPR_0_SPR_A_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_SPR_0_SPR_A_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define UART_SPR_0_SPR_A_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define UART_SPR_0_SPR_A_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define UART_SPR_0_SPR_A_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define UART_SPR_0_SPR_A_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register UART_IRDA_CSR_0
#define UART_IRDA_CSR_0                 MK_ADDR_CONST(0x20)
#define UART_IRDA_CSR_0_SECURE                  0x0
#define UART_IRDA_CSR_0_DUAL                    0x0
#define UART_IRDA_CSR_0_SCR                     0
#define UART_IRDA_CSR_0_SCRREG                  0
#define UART_IRDA_CSR_0_WORD_COUNT                      0x1
#define UART_IRDA_CSR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_RESET_MASK                      MK_MASK_CONST(0xcf)
#define UART_IRDA_CSR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_READ_MASK                       MK_MASK_CONST(0xcf)
#define UART_IRDA_CSR_0_WRITE_MASK                      MK_MASK_CONST(0xcf)
#define UART_IRDA_CSR_0_SIR_A_SHIFT                     MK_SHIFT_CONST(7)
#define UART_IRDA_CSR_0_SIR_A_FIELD                     MK_FIELD_CONST(0x1, UART_IRDA_CSR_0_SIR_A_SHIFT)
#define UART_IRDA_CSR_0_SIR_A_RANGE                     7:7
#define UART_IRDA_CSR_0_SIR_A_MSB                       MK_SHIFT_CONST(7)
#define UART_IRDA_CSR_0_SIR_A_LSB                       MK_SHIFT_CONST(7)
#define UART_IRDA_CSR_0_SIR_A_WOFFSET                   0x0
#define UART_IRDA_CSR_0_SIR_A_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_SIR_A_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define UART_IRDA_CSR_0_SIR_A_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_SIR_A_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_SIR_A_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_SIR_A_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define UART_IRDA_CSR_0_SIR_A_DISABLE                   MK_ENUM_CONST(0)
#define UART_IRDA_CSR_0_SIR_A_ENABLE                    MK_ENUM_CONST(1)

#define UART_IRDA_CSR_0_PWT_A_SHIFT                     MK_SHIFT_CONST(6)
#define UART_IRDA_CSR_0_PWT_A_FIELD                     MK_FIELD_CONST(0x1, UART_IRDA_CSR_0_PWT_A_SHIFT)
#define UART_IRDA_CSR_0_PWT_A_RANGE                     6:6
#define UART_IRDA_CSR_0_PWT_A_MSB                       MK_SHIFT_CONST(6)
#define UART_IRDA_CSR_0_PWT_A_LSB                       MK_SHIFT_CONST(6)
#define UART_IRDA_CSR_0_PWT_A_WOFFSET                   0x0
#define UART_IRDA_CSR_0_PWT_A_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_PWT_A_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define UART_IRDA_CSR_0_PWT_A_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_PWT_A_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_PWT_A_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_PWT_A_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define UART_IRDA_CSR_0_PWT_A_BAUD_PULSE_3_14                   MK_ENUM_CONST(0)
#define UART_IRDA_CSR_0_PWT_A_BAUD_PULSE_4_14                   MK_ENUM_CONST(1)

#define UART_IRDA_CSR_0_INVERT_RTS_SHIFT                        MK_SHIFT_CONST(3)
#define UART_IRDA_CSR_0_INVERT_RTS_FIELD                        MK_FIELD_CONST(0x1, UART_IRDA_CSR_0_INVERT_RTS_SHIFT)
#define UART_IRDA_CSR_0_INVERT_RTS_RANGE                        3:3
#define UART_IRDA_CSR_0_INVERT_RTS_MSB                  MK_SHIFT_CONST(3)
#define UART_IRDA_CSR_0_INVERT_RTS_LSB                  MK_SHIFT_CONST(3)
#define UART_IRDA_CSR_0_INVERT_RTS_WOFFSET                      0x0
#define UART_IRDA_CSR_0_INVERT_RTS_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_RTS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define UART_IRDA_CSR_0_INVERT_RTS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_RTS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_RTS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_RTS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define UART_IRDA_CSR_0_INVERT_RTS_DISABLE                      MK_ENUM_CONST(0)
#define UART_IRDA_CSR_0_INVERT_RTS_ENABLE                       MK_ENUM_CONST(1)

#define UART_IRDA_CSR_0_INVERT_CTS_SHIFT                        MK_SHIFT_CONST(2)
#define UART_IRDA_CSR_0_INVERT_CTS_FIELD                        MK_FIELD_CONST(0x1, UART_IRDA_CSR_0_INVERT_CTS_SHIFT)
#define UART_IRDA_CSR_0_INVERT_CTS_RANGE                        2:2
#define UART_IRDA_CSR_0_INVERT_CTS_MSB                  MK_SHIFT_CONST(2)
#define UART_IRDA_CSR_0_INVERT_CTS_LSB                  MK_SHIFT_CONST(2)
#define UART_IRDA_CSR_0_INVERT_CTS_WOFFSET                      0x0
#define UART_IRDA_CSR_0_INVERT_CTS_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_CTS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define UART_IRDA_CSR_0_INVERT_CTS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_CTS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_CTS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_CTS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define UART_IRDA_CSR_0_INVERT_CTS_DISABLE                      MK_ENUM_CONST(0)
#define UART_IRDA_CSR_0_INVERT_CTS_ENABLE                       MK_ENUM_CONST(1)

#define UART_IRDA_CSR_0_INVERT_TXD_SHIFT                        MK_SHIFT_CONST(1)
#define UART_IRDA_CSR_0_INVERT_TXD_FIELD                        MK_FIELD_CONST(0x1, UART_IRDA_CSR_0_INVERT_TXD_SHIFT)
#define UART_IRDA_CSR_0_INVERT_TXD_RANGE                        1:1
#define UART_IRDA_CSR_0_INVERT_TXD_MSB                  MK_SHIFT_CONST(1)
#define UART_IRDA_CSR_0_INVERT_TXD_LSB                  MK_SHIFT_CONST(1)
#define UART_IRDA_CSR_0_INVERT_TXD_WOFFSET                      0x0
#define UART_IRDA_CSR_0_INVERT_TXD_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_TXD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define UART_IRDA_CSR_0_INVERT_TXD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_TXD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_TXD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_TXD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define UART_IRDA_CSR_0_INVERT_TXD_DISABLE                      MK_ENUM_CONST(0)
#define UART_IRDA_CSR_0_INVERT_TXD_ENABLE                       MK_ENUM_CONST(1)

#define UART_IRDA_CSR_0_INVERT_RXD_SHIFT                        MK_SHIFT_CONST(0)
#define UART_IRDA_CSR_0_INVERT_RXD_FIELD                        MK_FIELD_CONST(0x1, UART_IRDA_CSR_0_INVERT_RXD_SHIFT)
#define UART_IRDA_CSR_0_INVERT_RXD_RANGE                        0:0
#define UART_IRDA_CSR_0_INVERT_RXD_MSB                  MK_SHIFT_CONST(0)
#define UART_IRDA_CSR_0_INVERT_RXD_LSB                  MK_SHIFT_CONST(0)
#define UART_IRDA_CSR_0_INVERT_RXD_WOFFSET                      0x0
#define UART_IRDA_CSR_0_INVERT_RXD_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_RXD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define UART_IRDA_CSR_0_INVERT_RXD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_RXD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_RXD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define UART_IRDA_CSR_0_INVERT_RXD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define UART_IRDA_CSR_0_INVERT_RXD_DISABLE                      MK_ENUM_CONST(0)
#define UART_IRDA_CSR_0_INVERT_RXD_ENABLE                       MK_ENUM_CONST(1)


// Register UART_RX_FIFO_CFG_0
#define UART_RX_FIFO_CFG_0                      MK_ADDR_CONST(0x24)
#define UART_RX_FIFO_CFG_0_SECURE                       0x0
#define UART_RX_FIFO_CFG_0_DUAL                         0x0
#define UART_RX_FIFO_CFG_0_SCR                  0
#define UART_RX_FIFO_CFG_0_SCRREG                       0
#define UART_RX_FIFO_CFG_0_WORD_COUNT                   0x1
#define UART_RX_FIFO_CFG_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define UART_RX_FIFO_CFG_0_RESET_MASK                   MK_MASK_CONST(0xbf)
#define UART_RX_FIFO_CFG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define UART_RX_FIFO_CFG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_RX_FIFO_CFG_0_READ_MASK                    MK_MASK_CONST(0xbf)
#define UART_RX_FIFO_CFG_0_WRITE_MASK                   MK_MASK_CONST(0xbf)
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_SHIFT                        MK_SHIFT_CONST(7)
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_FIELD                        MK_FIELD_CONST(0x1, UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_SHIFT)
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_RANGE                        7:7
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_MSB                  MK_SHIFT_CONST(7)
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_LSB                  MK_SHIFT_CONST(7)
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_WOFFSET                      0x0
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_DISABLE                      MK_ENUM_CONST(0)
#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_ENABLE                       MK_ENUM_CONST(1)

#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_SHIFT                   MK_SHIFT_CONST(0)
#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_FIELD                   MK_FIELD_CONST(0x3f, UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_SHIFT)
#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_RANGE                   5:0
#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_MSB                     MK_SHIFT_CONST(5)
#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_LSB                     MK_SHIFT_CONST(0)
#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_WOFFSET                 0x0
#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_DEFAULT                 MK_MASK_CONST(0x1)
#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register UART_MIE_0
#define UART_MIE_0                      MK_ADDR_CONST(0x28)
#define UART_MIE_0_SECURE                       0x0
#define UART_MIE_0_DUAL                         0x0
#define UART_MIE_0_SCR                  0
#define UART_MIE_0_SCRREG                       0
#define UART_MIE_0_WORD_COUNT                   0x1
#define UART_MIE_0_RESET_VAL                    MK_MASK_CONST(0xf)
#define UART_MIE_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define UART_MIE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define UART_MIE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_MIE_0_READ_MASK                    MK_MASK_CONST(0xf)
#define UART_MIE_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define UART_MIE_0_DCD_INT_EN_SHIFT                     MK_SHIFT_CONST(3)
#define UART_MIE_0_DCD_INT_EN_FIELD                     MK_FIELD_CONST(0x1, UART_MIE_0_DCD_INT_EN_SHIFT)
#define UART_MIE_0_DCD_INT_EN_RANGE                     3:3
#define UART_MIE_0_DCD_INT_EN_MSB                       MK_SHIFT_CONST(3)
#define UART_MIE_0_DCD_INT_EN_LSB                       MK_SHIFT_CONST(3)
#define UART_MIE_0_DCD_INT_EN_WOFFSET                   0x0
#define UART_MIE_0_DCD_INT_EN_DEFAULT                   MK_MASK_CONST(0x1)
#define UART_MIE_0_DCD_INT_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define UART_MIE_0_DCD_INT_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_MIE_0_DCD_INT_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define UART_MIE_0_DCD_INT_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define UART_MIE_0_DCD_INT_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define UART_MIE_0_DCD_INT_EN_DISABLE                   MK_ENUM_CONST(0)
#define UART_MIE_0_DCD_INT_EN_ENABLE                    MK_ENUM_CONST(1)

#define UART_MIE_0_DRI_INT_EN_SHIFT                     MK_SHIFT_CONST(2)
#define UART_MIE_0_DRI_INT_EN_FIELD                     MK_FIELD_CONST(0x1, UART_MIE_0_DRI_INT_EN_SHIFT)
#define UART_MIE_0_DRI_INT_EN_RANGE                     2:2
#define UART_MIE_0_DRI_INT_EN_MSB                       MK_SHIFT_CONST(2)
#define UART_MIE_0_DRI_INT_EN_LSB                       MK_SHIFT_CONST(2)
#define UART_MIE_0_DRI_INT_EN_WOFFSET                   0x0
#define UART_MIE_0_DRI_INT_EN_DEFAULT                   MK_MASK_CONST(0x1)
#define UART_MIE_0_DRI_INT_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define UART_MIE_0_DRI_INT_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_MIE_0_DRI_INT_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define UART_MIE_0_DRI_INT_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define UART_MIE_0_DRI_INT_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define UART_MIE_0_DRI_INT_EN_DISABLE                   MK_ENUM_CONST(0)
#define UART_MIE_0_DRI_INT_EN_ENABLE                    MK_ENUM_CONST(1)

#define UART_MIE_0_DDSR_INT_EN_SHIFT                    MK_SHIFT_CONST(1)
#define UART_MIE_0_DDSR_INT_EN_FIELD                    MK_FIELD_CONST(0x1, UART_MIE_0_DDSR_INT_EN_SHIFT)
#define UART_MIE_0_DDSR_INT_EN_RANGE                    1:1
#define UART_MIE_0_DDSR_INT_EN_MSB                      MK_SHIFT_CONST(1)
#define UART_MIE_0_DDSR_INT_EN_LSB                      MK_SHIFT_CONST(1)
#define UART_MIE_0_DDSR_INT_EN_WOFFSET                  0x0
#define UART_MIE_0_DDSR_INT_EN_DEFAULT                  MK_MASK_CONST(0x1)
#define UART_MIE_0_DDSR_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_MIE_0_DDSR_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_MIE_0_DDSR_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_MIE_0_DDSR_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_MIE_0_DDSR_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_MIE_0_DDSR_INT_EN_DISABLE                  MK_ENUM_CONST(0)
#define UART_MIE_0_DDSR_INT_EN_ENABLE                   MK_ENUM_CONST(1)

#define UART_MIE_0_DCTS_INT_EN_SHIFT                    MK_SHIFT_CONST(0)
#define UART_MIE_0_DCTS_INT_EN_FIELD                    MK_FIELD_CONST(0x1, UART_MIE_0_DCTS_INT_EN_SHIFT)
#define UART_MIE_0_DCTS_INT_EN_RANGE                    0:0
#define UART_MIE_0_DCTS_INT_EN_MSB                      MK_SHIFT_CONST(0)
#define UART_MIE_0_DCTS_INT_EN_LSB                      MK_SHIFT_CONST(0)
#define UART_MIE_0_DCTS_INT_EN_WOFFSET                  0x0
#define UART_MIE_0_DCTS_INT_EN_DEFAULT                  MK_MASK_CONST(0x1)
#define UART_MIE_0_DCTS_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define UART_MIE_0_DCTS_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_MIE_0_DCTS_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_MIE_0_DCTS_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_MIE_0_DCTS_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define UART_MIE_0_DCTS_INT_EN_DISABLE                  MK_ENUM_CONST(0)
#define UART_MIE_0_DCTS_INT_EN_ENABLE                   MK_ENUM_CONST(1)


// Register UART_VENDOR_STATUS_0_0
#define UART_VENDOR_STATUS_0_0                  MK_ADDR_CONST(0x2c)
#define UART_VENDOR_STATUS_0_0_SECURE                   0x0
#define UART_VENDOR_STATUS_0_0_DUAL                     0x0
#define UART_VENDOR_STATUS_0_0_SCR                      0
#define UART_VENDOR_STATUS_0_0_SCRREG                   0
#define UART_VENDOR_STATUS_0_0_WORD_COUNT                       0x1
#define UART_VENDOR_STATUS_0_0_RESET_VAL                        MK_MASK_CONST(0x3)
#define UART_VENDOR_STATUS_0_0_RESET_MASK                       MK_MASK_CONST(0x3f3f000f)
#define UART_VENDOR_STATUS_0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_READ_MASK                        MK_MASK_CONST(0x3f3f000f)
#define UART_VENDOR_STATUS_0_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_SHIFT                    MK_SHIFT_CONST(24)
#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_FIELD                    MK_FIELD_CONST(0x3f, UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_SHIFT)
#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_RANGE                    29:24
#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_MSB                      MK_SHIFT_CONST(29)
#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_LSB                      MK_SHIFT_CONST(24)
#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_WOFFSET                  0x0
#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_SHIFT                    MK_SHIFT_CONST(16)
#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_FIELD                    MK_FIELD_CONST(0x3f, UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_SHIFT)
#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_RANGE                    21:16
#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_MSB                      MK_SHIFT_CONST(21)
#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_LSB                      MK_SHIFT_CONST(16)
#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_WOFFSET                  0x0
#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_SHIFT                 MK_SHIFT_CONST(3)
#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_FIELD                 MK_FIELD_CONST(0x1, UART_VENDOR_STATUS_0_0_TX_OVERRUN_SHIFT)
#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_RANGE                 3:3
#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_MSB                   MK_SHIFT_CONST(3)
#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_LSB                   MK_SHIFT_CONST(3)
#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_WOFFSET                       0x0
#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_DEFAULT                       MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_NO_OVERRUN                    MK_ENUM_CONST(0)
#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_OVERRUN                       MK_ENUM_CONST(1)

#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_SHIFT                        MK_SHIFT_CONST(2)
#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_FIELD                        MK_FIELD_CONST(0x1, UART_VENDOR_STATUS_0_0_RX_UNDERRUN_SHIFT)
#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_RANGE                        2:2
#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_MSB                  MK_SHIFT_CONST(2)
#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_LSB                  MK_SHIFT_CONST(2)
#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_WOFFSET                      0x0
#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_NO_UNDERRUN                  MK_ENUM_CONST(0)
#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_UNDERRUN                     MK_ENUM_CONST(1)

#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_SHIFT                       MK_SHIFT_CONST(1)
#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_FIELD                       MK_FIELD_CONST(0x1, UART_VENDOR_STATUS_0_0_UART_RX_IDLE_SHIFT)
#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_RANGE                       1:1
#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_MSB                 MK_SHIFT_CONST(1)
#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_LSB                 MK_SHIFT_CONST(1)
#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_WOFFSET                     0x0
#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_DEFAULT                     MK_MASK_CONST(0x1)
#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_BUSY                        MK_ENUM_CONST(0)
#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_IDLE                        MK_ENUM_CONST(1)

#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_SHIFT                       MK_SHIFT_CONST(0)
#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_FIELD                       MK_FIELD_CONST(0x1, UART_VENDOR_STATUS_0_0_UART_TX_IDLE_SHIFT)
#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_RANGE                       0:0
#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_MSB                 MK_SHIFT_CONST(0)
#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_LSB                 MK_SHIFT_CONST(0)
#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_WOFFSET                     0x0
#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_DEFAULT                     MK_MASK_CONST(0x1)
#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_BUSY                        MK_ENUM_CONST(0)
#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_IDLE                        MK_ENUM_CONST(1)


// Reserved address 0x30

// Reserved address 0x34

// Reserved address 0x38

// Register UART_ASR_0
#define UART_ASR_0                      MK_ADDR_CONST(0x3c)
#define UART_ASR_0_SECURE                       0x0
#define UART_ASR_0_DUAL                         0x0
#define UART_ASR_0_SCR                  0
#define UART_ASR_0_SCRREG                       0
#define UART_ASR_0_WORD_COUNT                   0x1
#define UART_ASR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define UART_ASR_0_RESET_MASK                   MK_MASK_CONST(0xc000ffff)
#define UART_ASR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define UART_ASR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_ASR_0_READ_MASK                    MK_MASK_CONST(0xc000ffff)
#define UART_ASR_0_WRITE_MASK                   MK_MASK_CONST(0xc000ffff)
#define UART_ASR_0_VALID_SHIFT                  MK_SHIFT_CONST(31)
#define UART_ASR_0_VALID_FIELD                  MK_FIELD_CONST(0x1, UART_ASR_0_VALID_SHIFT)
#define UART_ASR_0_VALID_RANGE                  31:31
#define UART_ASR_0_VALID_MSB                    MK_SHIFT_CONST(31)
#define UART_ASR_0_VALID_LSB                    MK_SHIFT_CONST(31)
#define UART_ASR_0_VALID_WOFFSET                        0x0
#define UART_ASR_0_VALID_DEFAULT                        MK_MASK_CONST(0x0)
#define UART_ASR_0_VALID_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define UART_ASR_0_VALID_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define UART_ASR_0_VALID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define UART_ASR_0_VALID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define UART_ASR_0_VALID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define UART_ASR_0_VALID_UN_SET                 MK_ENUM_CONST(0)
#define UART_ASR_0_VALID_SET                    MK_ENUM_CONST(1)

#define UART_ASR_0_BUSY_SHIFT                   MK_SHIFT_CONST(30)
#define UART_ASR_0_BUSY_FIELD                   MK_FIELD_CONST(0x1, UART_ASR_0_BUSY_SHIFT)
#define UART_ASR_0_BUSY_RANGE                   30:30
#define UART_ASR_0_BUSY_MSB                     MK_SHIFT_CONST(30)
#define UART_ASR_0_BUSY_LSB                     MK_SHIFT_CONST(30)
#define UART_ASR_0_BUSY_WOFFSET                 0x0
#define UART_ASR_0_BUSY_DEFAULT                 MK_MASK_CONST(0x0)
#define UART_ASR_0_BUSY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define UART_ASR_0_BUSY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_ASR_0_BUSY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define UART_ASR_0_BUSY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define UART_ASR_0_BUSY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define UART_ASR_0_BUSY_NO_BUSY                 MK_ENUM_CONST(0)
#define UART_ASR_0_BUSY_BUSY                    MK_ENUM_CONST(1)

#define UART_ASR_0_RX_RATE_SENSE_H_SHIFT                        MK_SHIFT_CONST(8)
#define UART_ASR_0_RX_RATE_SENSE_H_FIELD                        MK_FIELD_CONST(0xff, UART_ASR_0_RX_RATE_SENSE_H_SHIFT)
#define UART_ASR_0_RX_RATE_SENSE_H_RANGE                        15:8
#define UART_ASR_0_RX_RATE_SENSE_H_MSB                  MK_SHIFT_CONST(15)
#define UART_ASR_0_RX_RATE_SENSE_H_LSB                  MK_SHIFT_CONST(8)
#define UART_ASR_0_RX_RATE_SENSE_H_WOFFSET                      0x0
#define UART_ASR_0_RX_RATE_SENSE_H_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_ASR_0_RX_RATE_SENSE_H_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define UART_ASR_0_RX_RATE_SENSE_H_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_ASR_0_RX_RATE_SENSE_H_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_ASR_0_RX_RATE_SENSE_H_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define UART_ASR_0_RX_RATE_SENSE_H_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define UART_ASR_0_RX_RATE_SENSE_L_SHIFT                        MK_SHIFT_CONST(0)
#define UART_ASR_0_RX_RATE_SENSE_L_FIELD                        MK_FIELD_CONST(0xff, UART_ASR_0_RX_RATE_SENSE_L_SHIFT)
#define UART_ASR_0_RX_RATE_SENSE_L_RANGE                        7:0
#define UART_ASR_0_RX_RATE_SENSE_L_MSB                  MK_SHIFT_CONST(7)
#define UART_ASR_0_RX_RATE_SENSE_L_LSB                  MK_SHIFT_CONST(0)
#define UART_ASR_0_RX_RATE_SENSE_L_WOFFSET                      0x0
#define UART_ASR_0_RX_RATE_SENSE_L_DEFAULT                      MK_MASK_CONST(0x0)
#define UART_ASR_0_RX_RATE_SENSE_L_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define UART_ASR_0_RX_RATE_SENSE_L_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define UART_ASR_0_RX_RATE_SENSE_L_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define UART_ASR_0_RX_RATE_SENSE_L_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define UART_ASR_0_RX_RATE_SENSE_L_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARUART_REGS(_op_) \
_op_(UART_THR_DLAB_0_0) \
_op_(UART_IER_DLAB_0_0) \
_op_(UART_IIR_FCR_0) \
_op_(UART_LCR_0) \
_op_(UART_MCR_0) \
_op_(UART_LSR_0) \
_op_(UART_MSR_0) \
_op_(UART_SPR_0) \
_op_(UART_IRDA_CSR_0) \
_op_(UART_RX_FIFO_CFG_0) \
_op_(UART_MIE_0) \
_op_(UART_VENDOR_STATUS_0_0) \
_op_(UART_ASR_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_UART       0x00000000

//
// ARUART REGISTER BANKS
//

#define UART0_FIRST_REG 0x0000 // UART_THR_DLAB_0_0
#define UART0_LAST_REG 0x002c // UART_VENDOR_STATUS_0_0
#define UART1_FIRST_REG 0x003c // UART_ASR_0
#define UART1_LAST_REG 0x003c // UART_ASR_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARUART_H_INC
