//
// Copyright (c) 2021 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARHSP_DBELL_H_INC
#define ARHSP_DBELL_H_INC
#define NV_MOBILE_ARHSP_DBELL_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARHSP_DBELL_H_SCRREG_NOMENCLATURE EXACT


// Register HSP_DBELL_0_TRIGGER_0
#define HSP_DBELL_0_TRIGGER_0                   MK_ADDR_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_0_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_0_TRIGGER_0_SCR                       0
#define HSP_DBELL_0_TRIGGER_0_SCRREG                    0
#define HSP_DBELL_0_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_0_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_0_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_0_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_0_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define HSP_DBELL_0_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register HSP_DBELL_0_ENABLE_0
#define HSP_DBELL_0_ENABLE_0                    MK_ADDR_CONST(0x4)
#define HSP_DBELL_0_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_0_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_0_ENABLE_0_SCR                        DB_0_REG_0
#define HSP_DBELL_0_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_0_REG_0
#define HSP_DBELL_0_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_0_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_0_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_0_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_0_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_0_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_0_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_0_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_0_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_0_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_0_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_0_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_0_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_0_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_0_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_0_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_0_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_0_RAW_0
#define HSP_DBELL_0_RAW_0                       MK_ADDR_CONST(0x8)
#define HSP_DBELL_0_RAW_0_SECURE                        0x0
#define HSP_DBELL_0_RAW_0_DUAL                  0x0
#define HSP_DBELL_0_RAW_0_SCR                   DB_0_REG_0
#define HSP_DBELL_0_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_0_REG_0
#define HSP_DBELL_0_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_0_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
#define HSP_DBELL_0_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_0_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_0_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_0_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
#define HSP_DBELL_0_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
#define HSP_DBELL_0_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_0_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define HSP_DBELL_0_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
#define HSP_DBELL_0_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_0_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_0_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_0_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
#define HSP_DBELL_0_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
#define HSP_DBELL_0_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_0_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register HSP_DBELL_0_PENDING_0
#define HSP_DBELL_0_PENDING_0                   MK_ADDR_CONST(0xc)
#define HSP_DBELL_0_PENDING_0_SECURE                    0x0
#define HSP_DBELL_0_PENDING_0_DUAL                      0x0
#define HSP_DBELL_0_PENDING_0_SCR                       DB_0_REG_0
#define HSP_DBELL_0_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_0_REG_0
#define HSP_DBELL_0_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_0_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
#define HSP_DBELL_0_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_0_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_0_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_0_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
#define HSP_DBELL_0_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
#define HSP_DBELL_0_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_0_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define HSP_DBELL_0_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
#define HSP_DBELL_0_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_0_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_0_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_0_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
#define HSP_DBELL_0_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
#define HSP_DBELL_0_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_0_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x10

// Reserved address 0x14

// Reserved address 0x18

// Reserved address 0x1c

// Reserved address 0x20

// Register HSP_DBELL_0_ENABLE_SLICE1_0
#define HSP_DBELL_0_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x24)
#define HSP_DBELL_0_ENABLE_SLICE1_0_SECURE                      0x0
#define HSP_DBELL_0_ENABLE_SLICE1_0_DUAL                        0x0
#define HSP_DBELL_0_ENABLE_SLICE1_0_SCR                         DB_0_REG_0
#define HSP_DBELL_0_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_0_REG_0
#define HSP_DBELL_0_ENABLE_SLICE1_0_WORD_COUNT                  0x1
#define HSP_DBELL_0_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register HSP_DBELL_0_RAW_SLICE1_0
#define HSP_DBELL_0_RAW_SLICE1_0                        MK_ADDR_CONST(0x28)
#define HSP_DBELL_0_RAW_SLICE1_0_SECURE                         0x0
#define HSP_DBELL_0_RAW_SLICE1_0_DUAL                   0x0
#define HSP_DBELL_0_RAW_SLICE1_0_SCR                    DB_0_REG_0
#define HSP_DBELL_0_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_0_REG_0
#define HSP_DBELL_0_RAW_SLICE1_0_WORD_COUNT                     0x1
#define HSP_DBELL_0_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_0_RAW_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_RANGE                     31:16
#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_0_RAW_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_RANGE                     15:0
#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register HSP_DBELL_0_PENDING_SLICE1_0
#define HSP_DBELL_0_PENDING_SLICE1_0                    MK_ADDR_CONST(0x2c)
#define HSP_DBELL_0_PENDING_SLICE1_0_SECURE                     0x0
#define HSP_DBELL_0_PENDING_SLICE1_0_DUAL                       0x0
#define HSP_DBELL_0_PENDING_SLICE1_0_SCR                        DB_0_REG_0
#define HSP_DBELL_0_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_0_REG_0
#define HSP_DBELL_0_PENDING_SLICE1_0_WORD_COUNT                         0x1
#define HSP_DBELL_0_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_0_PENDING_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_RANGE                 31:16
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_0_PENDING_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_RANGE                 15:0
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_1_TRIGGER_0
#define HSP_DBELL_1_TRIGGER_0                   MK_ADDR_CONST(0x100)
#define HSP_DBELL_1_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_1_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_1_TRIGGER_0_SCR                       0
#define HSP_DBELL_1_TRIGGER_0_SCRREG                    0
#define HSP_DBELL_1_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_1_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_1_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_1_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_1_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define HSP_DBELL_1_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register HSP_DBELL_1_ENABLE_0
#define HSP_DBELL_1_ENABLE_0                    MK_ADDR_CONST(0x104)
#define HSP_DBELL_1_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_1_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_1_ENABLE_0_SCR                        DB_1_REG_0
#define HSP_DBELL_1_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_1_REG_0
#define HSP_DBELL_1_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_1_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_1_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_1_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_1_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_1_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_1_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_1_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_1_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_1_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_1_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_1_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_1_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_1_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_1_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_1_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_1_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_1_RAW_0
#define HSP_DBELL_1_RAW_0                       MK_ADDR_CONST(0x108)
#define HSP_DBELL_1_RAW_0_SECURE                        0x0
#define HSP_DBELL_1_RAW_0_DUAL                  0x0
#define HSP_DBELL_1_RAW_0_SCR                   DB_1_REG_0
#define HSP_DBELL_1_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_1_REG_0
#define HSP_DBELL_1_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_1_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
#define HSP_DBELL_1_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_1_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_1_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_1_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
#define HSP_DBELL_1_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
#define HSP_DBELL_1_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_1_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define HSP_DBELL_1_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
#define HSP_DBELL_1_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_1_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_1_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_1_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
#define HSP_DBELL_1_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
#define HSP_DBELL_1_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_1_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register HSP_DBELL_1_PENDING_0
#define HSP_DBELL_1_PENDING_0                   MK_ADDR_CONST(0x10c)
#define HSP_DBELL_1_PENDING_0_SECURE                    0x0
#define HSP_DBELL_1_PENDING_0_DUAL                      0x0
#define HSP_DBELL_1_PENDING_0_SCR                       DB_1_REG_0
#define HSP_DBELL_1_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_1_REG_0
#define HSP_DBELL_1_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_1_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
#define HSP_DBELL_1_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_1_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_1_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_1_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
#define HSP_DBELL_1_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
#define HSP_DBELL_1_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_1_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define HSP_DBELL_1_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
#define HSP_DBELL_1_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_1_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_1_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_1_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
#define HSP_DBELL_1_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
#define HSP_DBELL_1_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_1_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x110

// Reserved address 0x114

// Reserved address 0x118

// Reserved address 0x11c

// Reserved address 0x120

// Register HSP_DBELL_1_ENABLE_SLICE1_0
#define HSP_DBELL_1_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x124)
#define HSP_DBELL_1_ENABLE_SLICE1_0_SECURE                      0x0
#define HSP_DBELL_1_ENABLE_SLICE1_0_DUAL                        0x0
#define HSP_DBELL_1_ENABLE_SLICE1_0_SCR                         DB_1_REG_0
#define HSP_DBELL_1_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_1_REG_0
#define HSP_DBELL_1_ENABLE_SLICE1_0_WORD_COUNT                  0x1
#define HSP_DBELL_1_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register HSP_DBELL_1_RAW_SLICE1_0
#define HSP_DBELL_1_RAW_SLICE1_0                        MK_ADDR_CONST(0x128)
#define HSP_DBELL_1_RAW_SLICE1_0_SECURE                         0x0
#define HSP_DBELL_1_RAW_SLICE1_0_DUAL                   0x0
#define HSP_DBELL_1_RAW_SLICE1_0_SCR                    DB_1_REG_0
#define HSP_DBELL_1_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_1_REG_0
#define HSP_DBELL_1_RAW_SLICE1_0_WORD_COUNT                     0x1
#define HSP_DBELL_1_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_1_RAW_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_RANGE                     31:16
#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_1_RAW_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_RANGE                     15:0
#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register HSP_DBELL_1_PENDING_SLICE1_0
#define HSP_DBELL_1_PENDING_SLICE1_0                    MK_ADDR_CONST(0x12c)
#define HSP_DBELL_1_PENDING_SLICE1_0_SECURE                     0x0
#define HSP_DBELL_1_PENDING_SLICE1_0_DUAL                       0x0
#define HSP_DBELL_1_PENDING_SLICE1_0_SCR                        DB_1_REG_0
#define HSP_DBELL_1_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_1_REG_0
#define HSP_DBELL_1_PENDING_SLICE1_0_WORD_COUNT                         0x1
#define HSP_DBELL_1_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_1_PENDING_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_RANGE                 31:16
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_1_PENDING_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_RANGE                 15:0
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_2_TRIGGER_0
#define HSP_DBELL_2_TRIGGER_0                   MK_ADDR_CONST(0x200)
#define HSP_DBELL_2_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_2_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_2_TRIGGER_0_SCR                       0
#define HSP_DBELL_2_TRIGGER_0_SCRREG                    0
#define HSP_DBELL_2_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_2_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_2_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_2_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_2_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define HSP_DBELL_2_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register HSP_DBELL_2_ENABLE_0
#define HSP_DBELL_2_ENABLE_0                    MK_ADDR_CONST(0x204)
#define HSP_DBELL_2_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_2_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_2_ENABLE_0_SCR                        DB_2_REG_0
#define HSP_DBELL_2_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_2_REG_0
#define HSP_DBELL_2_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_2_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_2_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_2_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_2_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_2_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_2_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_2_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_2_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_2_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_2_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_2_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_2_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_2_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_2_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_2_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_2_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_2_RAW_0
#define HSP_DBELL_2_RAW_0                       MK_ADDR_CONST(0x208)
#define HSP_DBELL_2_RAW_0_SECURE                        0x0
#define HSP_DBELL_2_RAW_0_DUAL                  0x0
#define HSP_DBELL_2_RAW_0_SCR                   DB_2_REG_0
#define HSP_DBELL_2_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_2_REG_0
#define HSP_DBELL_2_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_2_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
#define HSP_DBELL_2_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_2_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_2_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_2_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
#define HSP_DBELL_2_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
#define HSP_DBELL_2_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_2_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define HSP_DBELL_2_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
#define HSP_DBELL_2_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_2_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_2_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_2_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
#define HSP_DBELL_2_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
#define HSP_DBELL_2_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_2_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register HSP_DBELL_2_PENDING_0
#define HSP_DBELL_2_PENDING_0                   MK_ADDR_CONST(0x20c)
#define HSP_DBELL_2_PENDING_0_SECURE                    0x0
#define HSP_DBELL_2_PENDING_0_DUAL                      0x0
#define HSP_DBELL_2_PENDING_0_SCR                       DB_2_REG_0
#define HSP_DBELL_2_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_2_REG_0
#define HSP_DBELL_2_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_2_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
#define HSP_DBELL_2_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_2_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_2_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_2_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
#define HSP_DBELL_2_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
#define HSP_DBELL_2_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_2_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define HSP_DBELL_2_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
#define HSP_DBELL_2_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_2_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_2_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_2_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
#define HSP_DBELL_2_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
#define HSP_DBELL_2_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_2_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x210

// Reserved address 0x214

// Reserved address 0x218

// Reserved address 0x21c

// Reserved address 0x220

// Register HSP_DBELL_2_ENABLE_SLICE1_0
#define HSP_DBELL_2_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x224)
#define HSP_DBELL_2_ENABLE_SLICE1_0_SECURE                      0x0
#define HSP_DBELL_2_ENABLE_SLICE1_0_DUAL                        0x0
#define HSP_DBELL_2_ENABLE_SLICE1_0_SCR                         DB_2_REG_0
#define HSP_DBELL_2_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_2_REG_0
#define HSP_DBELL_2_ENABLE_SLICE1_0_WORD_COUNT                  0x1
#define HSP_DBELL_2_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register HSP_DBELL_2_RAW_SLICE1_0
#define HSP_DBELL_2_RAW_SLICE1_0                        MK_ADDR_CONST(0x228)
#define HSP_DBELL_2_RAW_SLICE1_0_SECURE                         0x0
#define HSP_DBELL_2_RAW_SLICE1_0_DUAL                   0x0
#define HSP_DBELL_2_RAW_SLICE1_0_SCR                    DB_2_REG_0
#define HSP_DBELL_2_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_2_REG_0
#define HSP_DBELL_2_RAW_SLICE1_0_WORD_COUNT                     0x1
#define HSP_DBELL_2_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_2_RAW_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_RANGE                     31:16
#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_2_RAW_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_RANGE                     15:0
#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register HSP_DBELL_2_PENDING_SLICE1_0
#define HSP_DBELL_2_PENDING_SLICE1_0                    MK_ADDR_CONST(0x22c)
#define HSP_DBELL_2_PENDING_SLICE1_0_SECURE                     0x0
#define HSP_DBELL_2_PENDING_SLICE1_0_DUAL                       0x0
#define HSP_DBELL_2_PENDING_SLICE1_0_SCR                        DB_2_REG_0
#define HSP_DBELL_2_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_2_REG_0
#define HSP_DBELL_2_PENDING_SLICE1_0_WORD_COUNT                         0x1
#define HSP_DBELL_2_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_2_PENDING_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_RANGE                 31:16
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_2_PENDING_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_RANGE                 15:0
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_3_TRIGGER_0
#define HSP_DBELL_3_TRIGGER_0                   MK_ADDR_CONST(0x300)
#define HSP_DBELL_3_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_3_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_3_TRIGGER_0_SCR                       0
#define HSP_DBELL_3_TRIGGER_0_SCRREG                    0
#define HSP_DBELL_3_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_3_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_3_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_3_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_3_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define HSP_DBELL_3_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register HSP_DBELL_3_ENABLE_0
#define HSP_DBELL_3_ENABLE_0                    MK_ADDR_CONST(0x304)
#define HSP_DBELL_3_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_3_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_3_ENABLE_0_SCR                        DB_3_REG_0
#define HSP_DBELL_3_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_3_REG_0
#define HSP_DBELL_3_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_3_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_3_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_3_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_3_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_3_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_3_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_3_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_3_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_3_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_3_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_3_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_3_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_3_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_3_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_3_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_3_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_3_RAW_0
#define HSP_DBELL_3_RAW_0                       MK_ADDR_CONST(0x308)
#define HSP_DBELL_3_RAW_0_SECURE                        0x0
#define HSP_DBELL_3_RAW_0_DUAL                  0x0
#define HSP_DBELL_3_RAW_0_SCR                   DB_3_REG_0
#define HSP_DBELL_3_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_3_REG_0
#define HSP_DBELL_3_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_3_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
#define HSP_DBELL_3_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_3_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_3_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_3_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
#define HSP_DBELL_3_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
#define HSP_DBELL_3_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_3_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define HSP_DBELL_3_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
#define HSP_DBELL_3_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_3_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_3_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_3_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
#define HSP_DBELL_3_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
#define HSP_DBELL_3_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_3_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register HSP_DBELL_3_PENDING_0
#define HSP_DBELL_3_PENDING_0                   MK_ADDR_CONST(0x30c)
#define HSP_DBELL_3_PENDING_0_SECURE                    0x0
#define HSP_DBELL_3_PENDING_0_DUAL                      0x0
#define HSP_DBELL_3_PENDING_0_SCR                       DB_3_REG_0
#define HSP_DBELL_3_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_3_REG_0
#define HSP_DBELL_3_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_3_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
#define HSP_DBELL_3_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_3_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_3_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_3_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
#define HSP_DBELL_3_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
#define HSP_DBELL_3_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_3_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define HSP_DBELL_3_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
#define HSP_DBELL_3_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_3_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_3_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_3_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
#define HSP_DBELL_3_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
#define HSP_DBELL_3_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_3_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x310

// Reserved address 0x314

// Reserved address 0x318

// Reserved address 0x31c

// Reserved address 0x320

// Register HSP_DBELL_3_ENABLE_SLICE1_0
#define HSP_DBELL_3_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x324)
#define HSP_DBELL_3_ENABLE_SLICE1_0_SECURE                      0x0
#define HSP_DBELL_3_ENABLE_SLICE1_0_DUAL                        0x0
#define HSP_DBELL_3_ENABLE_SLICE1_0_SCR                         DB_3_REG_0
#define HSP_DBELL_3_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_3_REG_0
#define HSP_DBELL_3_ENABLE_SLICE1_0_WORD_COUNT                  0x1
#define HSP_DBELL_3_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register HSP_DBELL_3_RAW_SLICE1_0
#define HSP_DBELL_3_RAW_SLICE1_0                        MK_ADDR_CONST(0x328)
#define HSP_DBELL_3_RAW_SLICE1_0_SECURE                         0x0
#define HSP_DBELL_3_RAW_SLICE1_0_DUAL                   0x0
#define HSP_DBELL_3_RAW_SLICE1_0_SCR                    DB_3_REG_0
#define HSP_DBELL_3_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_3_REG_0
#define HSP_DBELL_3_RAW_SLICE1_0_WORD_COUNT                     0x1
#define HSP_DBELL_3_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_3_RAW_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_RANGE                     31:16
#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_3_RAW_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_RANGE                     15:0
#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register HSP_DBELL_3_PENDING_SLICE1_0
#define HSP_DBELL_3_PENDING_SLICE1_0                    MK_ADDR_CONST(0x32c)
#define HSP_DBELL_3_PENDING_SLICE1_0_SECURE                     0x0
#define HSP_DBELL_3_PENDING_SLICE1_0_DUAL                       0x0
#define HSP_DBELL_3_PENDING_SLICE1_0_SCR                        DB_3_REG_0
#define HSP_DBELL_3_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_3_REG_0
#define HSP_DBELL_3_PENDING_SLICE1_0_WORD_COUNT                         0x1
#define HSP_DBELL_3_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_3_PENDING_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_RANGE                 31:16
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_3_PENDING_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_RANGE                 15:0
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_4_TRIGGER_0
#define HSP_DBELL_4_TRIGGER_0                   MK_ADDR_CONST(0x400)
#define HSP_DBELL_4_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_4_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_4_TRIGGER_0_SCR                       0
#define HSP_DBELL_4_TRIGGER_0_SCRREG                    0
#define HSP_DBELL_4_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_4_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_4_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_4_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_4_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define HSP_DBELL_4_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register HSP_DBELL_4_ENABLE_0
#define HSP_DBELL_4_ENABLE_0                    MK_ADDR_CONST(0x404)
#define HSP_DBELL_4_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_4_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_4_ENABLE_0_SCR                        DB_4_REG_0
#define HSP_DBELL_4_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_4_REG_0
#define HSP_DBELL_4_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_4_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_4_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_4_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_4_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_4_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_4_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_4_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_4_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_4_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_4_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_4_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_4_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_4_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_4_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_4_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_4_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_4_RAW_0
#define HSP_DBELL_4_RAW_0                       MK_ADDR_CONST(0x408)
#define HSP_DBELL_4_RAW_0_SECURE                        0x0
#define HSP_DBELL_4_RAW_0_DUAL                  0x0
#define HSP_DBELL_4_RAW_0_SCR                   DB_4_REG_0
#define HSP_DBELL_4_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_4_REG_0
#define HSP_DBELL_4_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_4_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
#define HSP_DBELL_4_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_4_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_4_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_4_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
#define HSP_DBELL_4_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
#define HSP_DBELL_4_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_4_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define HSP_DBELL_4_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
#define HSP_DBELL_4_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_4_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_4_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_4_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
#define HSP_DBELL_4_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
#define HSP_DBELL_4_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_4_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register HSP_DBELL_4_PENDING_0
#define HSP_DBELL_4_PENDING_0                   MK_ADDR_CONST(0x40c)
#define HSP_DBELL_4_PENDING_0_SECURE                    0x0
#define HSP_DBELL_4_PENDING_0_DUAL                      0x0
#define HSP_DBELL_4_PENDING_0_SCR                       DB_4_REG_0
#define HSP_DBELL_4_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_4_REG_0
#define HSP_DBELL_4_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_4_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
#define HSP_DBELL_4_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_4_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_4_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_4_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
#define HSP_DBELL_4_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
#define HSP_DBELL_4_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_4_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define HSP_DBELL_4_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
#define HSP_DBELL_4_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_4_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_4_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_4_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
#define HSP_DBELL_4_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
#define HSP_DBELL_4_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_4_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x410

// Reserved address 0x414

// Reserved address 0x418

// Reserved address 0x41c

// Reserved address 0x420

// Register HSP_DBELL_4_ENABLE_SLICE1_0
#define HSP_DBELL_4_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x424)
#define HSP_DBELL_4_ENABLE_SLICE1_0_SECURE                      0x0
#define HSP_DBELL_4_ENABLE_SLICE1_0_DUAL                        0x0
#define HSP_DBELL_4_ENABLE_SLICE1_0_SCR                         DB_4_REG_0
#define HSP_DBELL_4_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_4_REG_0
#define HSP_DBELL_4_ENABLE_SLICE1_0_WORD_COUNT                  0x1
#define HSP_DBELL_4_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register HSP_DBELL_4_RAW_SLICE1_0
#define HSP_DBELL_4_RAW_SLICE1_0                        MK_ADDR_CONST(0x428)
#define HSP_DBELL_4_RAW_SLICE1_0_SECURE                         0x0
#define HSP_DBELL_4_RAW_SLICE1_0_DUAL                   0x0
#define HSP_DBELL_4_RAW_SLICE1_0_SCR                    DB_4_REG_0
#define HSP_DBELL_4_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_4_REG_0
#define HSP_DBELL_4_RAW_SLICE1_0_WORD_COUNT                     0x1
#define HSP_DBELL_4_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_4_RAW_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_RANGE                     31:16
#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_4_RAW_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_RANGE                     15:0
#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register HSP_DBELL_4_PENDING_SLICE1_0
#define HSP_DBELL_4_PENDING_SLICE1_0                    MK_ADDR_CONST(0x42c)
#define HSP_DBELL_4_PENDING_SLICE1_0_SECURE                     0x0
#define HSP_DBELL_4_PENDING_SLICE1_0_DUAL                       0x0
#define HSP_DBELL_4_PENDING_SLICE1_0_SCR                        DB_4_REG_0
#define HSP_DBELL_4_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_4_REG_0
#define HSP_DBELL_4_PENDING_SLICE1_0_WORD_COUNT                         0x1
#define HSP_DBELL_4_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_4_PENDING_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_RANGE                 31:16
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_4_PENDING_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_RANGE                 15:0
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_5_TRIGGER_0
#define HSP_DBELL_5_TRIGGER_0                   MK_ADDR_CONST(0x500)
#define HSP_DBELL_5_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_5_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_5_TRIGGER_0_SCR                       0
#define HSP_DBELL_5_TRIGGER_0_SCRREG                    0
#define HSP_DBELL_5_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_5_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_5_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_5_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_5_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define HSP_DBELL_5_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register HSP_DBELL_5_ENABLE_0
#define HSP_DBELL_5_ENABLE_0                    MK_ADDR_CONST(0x504)
#define HSP_DBELL_5_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_5_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_5_ENABLE_0_SCR                        DB_5_REG_0
#define HSP_DBELL_5_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_5_REG_0
#define HSP_DBELL_5_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_5_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_5_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_5_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_5_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_5_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_5_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_5_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_5_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_5_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_5_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_5_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_5_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_5_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_5_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_5_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_5_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_5_RAW_0
#define HSP_DBELL_5_RAW_0                       MK_ADDR_CONST(0x508)
#define HSP_DBELL_5_RAW_0_SECURE                        0x0
#define HSP_DBELL_5_RAW_0_DUAL                  0x0
#define HSP_DBELL_5_RAW_0_SCR                   DB_5_REG_0
#define HSP_DBELL_5_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_5_REG_0
#define HSP_DBELL_5_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_5_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
#define HSP_DBELL_5_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_5_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_5_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_5_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
#define HSP_DBELL_5_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
#define HSP_DBELL_5_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_5_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define HSP_DBELL_5_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
#define HSP_DBELL_5_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_5_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_5_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_5_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
#define HSP_DBELL_5_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
#define HSP_DBELL_5_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_5_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register HSP_DBELL_5_PENDING_0
#define HSP_DBELL_5_PENDING_0                   MK_ADDR_CONST(0x50c)
#define HSP_DBELL_5_PENDING_0_SECURE                    0x0
#define HSP_DBELL_5_PENDING_0_DUAL                      0x0
#define HSP_DBELL_5_PENDING_0_SCR                       DB_5_REG_0
#define HSP_DBELL_5_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_5_REG_0
#define HSP_DBELL_5_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_5_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
#define HSP_DBELL_5_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_5_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_5_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_5_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
#define HSP_DBELL_5_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
#define HSP_DBELL_5_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_5_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define HSP_DBELL_5_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
#define HSP_DBELL_5_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_5_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_5_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_5_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
#define HSP_DBELL_5_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
#define HSP_DBELL_5_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_5_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x510

// Reserved address 0x514

// Reserved address 0x518

// Reserved address 0x51c

// Reserved address 0x520

// Register HSP_DBELL_5_ENABLE_SLICE1_0
#define HSP_DBELL_5_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x524)
#define HSP_DBELL_5_ENABLE_SLICE1_0_SECURE                      0x0
#define HSP_DBELL_5_ENABLE_SLICE1_0_DUAL                        0x0
#define HSP_DBELL_5_ENABLE_SLICE1_0_SCR                         DB_5_REG_0
#define HSP_DBELL_5_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_5_REG_0
#define HSP_DBELL_5_ENABLE_SLICE1_0_WORD_COUNT                  0x1
#define HSP_DBELL_5_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register HSP_DBELL_5_RAW_SLICE1_0
#define HSP_DBELL_5_RAW_SLICE1_0                        MK_ADDR_CONST(0x528)
#define HSP_DBELL_5_RAW_SLICE1_0_SECURE                         0x0
#define HSP_DBELL_5_RAW_SLICE1_0_DUAL                   0x0
#define HSP_DBELL_5_RAW_SLICE1_0_SCR                    DB_5_REG_0
#define HSP_DBELL_5_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_5_REG_0
#define HSP_DBELL_5_RAW_SLICE1_0_WORD_COUNT                     0x1
#define HSP_DBELL_5_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_5_RAW_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_RANGE                     31:16
#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_5_RAW_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_RANGE                     15:0
#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register HSP_DBELL_5_PENDING_SLICE1_0
#define HSP_DBELL_5_PENDING_SLICE1_0                    MK_ADDR_CONST(0x52c)
#define HSP_DBELL_5_PENDING_SLICE1_0_SECURE                     0x0
#define HSP_DBELL_5_PENDING_SLICE1_0_DUAL                       0x0
#define HSP_DBELL_5_PENDING_SLICE1_0_SCR                        DB_5_REG_0
#define HSP_DBELL_5_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_5_REG_0
#define HSP_DBELL_5_PENDING_SLICE1_0_WORD_COUNT                         0x1
#define HSP_DBELL_5_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_5_PENDING_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_RANGE                 31:16
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_5_PENDING_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_RANGE                 15:0
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_6_TRIGGER_0
#define HSP_DBELL_6_TRIGGER_0                   MK_ADDR_CONST(0x600)
#define HSP_DBELL_6_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_6_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_6_TRIGGER_0_SCR                       0
#define HSP_DBELL_6_TRIGGER_0_SCRREG                    0
#define HSP_DBELL_6_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_6_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_6_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_6_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_6_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define HSP_DBELL_6_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register HSP_DBELL_6_ENABLE_0
#define HSP_DBELL_6_ENABLE_0                    MK_ADDR_CONST(0x604)
#define HSP_DBELL_6_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_6_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_6_ENABLE_0_SCR                        DB_6_REG_0
#define HSP_DBELL_6_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_6_REG_0
#define HSP_DBELL_6_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_6_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_6_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_6_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_6_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_6_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_6_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_6_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_6_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_6_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_6_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_6_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_6_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_6_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_6_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_6_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_6_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_6_RAW_0
#define HSP_DBELL_6_RAW_0                       MK_ADDR_CONST(0x608)
#define HSP_DBELL_6_RAW_0_SECURE                        0x0
#define HSP_DBELL_6_RAW_0_DUAL                  0x0
#define HSP_DBELL_6_RAW_0_SCR                   DB_6_REG_0
#define HSP_DBELL_6_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_6_REG_0
#define HSP_DBELL_6_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_6_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
#define HSP_DBELL_6_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_6_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_6_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_6_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
#define HSP_DBELL_6_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
#define HSP_DBELL_6_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_6_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define HSP_DBELL_6_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
#define HSP_DBELL_6_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_6_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_6_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_6_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
#define HSP_DBELL_6_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
#define HSP_DBELL_6_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_6_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register HSP_DBELL_6_PENDING_0
#define HSP_DBELL_6_PENDING_0                   MK_ADDR_CONST(0x60c)
#define HSP_DBELL_6_PENDING_0_SECURE                    0x0
#define HSP_DBELL_6_PENDING_0_DUAL                      0x0
#define HSP_DBELL_6_PENDING_0_SCR                       DB_6_REG_0
#define HSP_DBELL_6_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_6_REG_0
#define HSP_DBELL_6_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_6_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
#define HSP_DBELL_6_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_6_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_6_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_6_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
#define HSP_DBELL_6_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
#define HSP_DBELL_6_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_6_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define HSP_DBELL_6_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
#define HSP_DBELL_6_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_6_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_6_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_6_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
#define HSP_DBELL_6_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
#define HSP_DBELL_6_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_6_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x610

// Reserved address 0x614

// Reserved address 0x618

// Reserved address 0x61c

// Reserved address 0x620

// Register HSP_DBELL_6_ENABLE_SLICE1_0
#define HSP_DBELL_6_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x624)
#define HSP_DBELL_6_ENABLE_SLICE1_0_SECURE                      0x0
#define HSP_DBELL_6_ENABLE_SLICE1_0_DUAL                        0x0
#define HSP_DBELL_6_ENABLE_SLICE1_0_SCR                         DB_6_REG_0
#define HSP_DBELL_6_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_6_REG_0
#define HSP_DBELL_6_ENABLE_SLICE1_0_WORD_COUNT                  0x1
#define HSP_DBELL_6_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register HSP_DBELL_6_RAW_SLICE1_0
#define HSP_DBELL_6_RAW_SLICE1_0                        MK_ADDR_CONST(0x628)
#define HSP_DBELL_6_RAW_SLICE1_0_SECURE                         0x0
#define HSP_DBELL_6_RAW_SLICE1_0_DUAL                   0x0
#define HSP_DBELL_6_RAW_SLICE1_0_SCR                    DB_6_REG_0
#define HSP_DBELL_6_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_6_REG_0
#define HSP_DBELL_6_RAW_SLICE1_0_WORD_COUNT                     0x1
#define HSP_DBELL_6_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_6_RAW_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_RANGE                     31:16
#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_6_RAW_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_RANGE                     15:0
#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register HSP_DBELL_6_PENDING_SLICE1_0
#define HSP_DBELL_6_PENDING_SLICE1_0                    MK_ADDR_CONST(0x62c)
#define HSP_DBELL_6_PENDING_SLICE1_0_SECURE                     0x0
#define HSP_DBELL_6_PENDING_SLICE1_0_DUAL                       0x0
#define HSP_DBELL_6_PENDING_SLICE1_0_SCR                        DB_6_REG_0
#define HSP_DBELL_6_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_6_REG_0
#define HSP_DBELL_6_PENDING_SLICE1_0_WORD_COUNT                         0x1
#define HSP_DBELL_6_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_6_PENDING_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_RANGE                 31:16
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_6_PENDING_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_RANGE                 15:0
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_7_TRIGGER_0
#define HSP_DBELL_7_TRIGGER_0                   MK_ADDR_CONST(0x700)
#define HSP_DBELL_7_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_7_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_7_TRIGGER_0_SCR                       0
#define HSP_DBELL_7_TRIGGER_0_SCRREG                    0
#define HSP_DBELL_7_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_7_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_7_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_7_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_7_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define HSP_DBELL_7_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register HSP_DBELL_7_ENABLE_0
#define HSP_DBELL_7_ENABLE_0                    MK_ADDR_CONST(0x704)
#define HSP_DBELL_7_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_7_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_7_ENABLE_0_SCR                        DB_7_REG_0
#define HSP_DBELL_7_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_7_REG_0
#define HSP_DBELL_7_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_7_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_7_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_7_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_7_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_7_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_7_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_7_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_7_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_7_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_7_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_7_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_7_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_7_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_7_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_7_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_7_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_7_RAW_0
#define HSP_DBELL_7_RAW_0                       MK_ADDR_CONST(0x708)
#define HSP_DBELL_7_RAW_0_SECURE                        0x0
#define HSP_DBELL_7_RAW_0_DUAL                  0x0
#define HSP_DBELL_7_RAW_0_SCR                   DB_7_REG_0
#define HSP_DBELL_7_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_7_REG_0
#define HSP_DBELL_7_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_7_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
#define HSP_DBELL_7_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_7_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_7_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_7_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
#define HSP_DBELL_7_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
#define HSP_DBELL_7_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_7_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define HSP_DBELL_7_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
#define HSP_DBELL_7_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_7_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_7_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_7_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
#define HSP_DBELL_7_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
#define HSP_DBELL_7_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_7_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register HSP_DBELL_7_PENDING_0
#define HSP_DBELL_7_PENDING_0                   MK_ADDR_CONST(0x70c)
#define HSP_DBELL_7_PENDING_0_SECURE                    0x0
#define HSP_DBELL_7_PENDING_0_DUAL                      0x0
#define HSP_DBELL_7_PENDING_0_SCR                       DB_7_REG_0
#define HSP_DBELL_7_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_7_REG_0
#define HSP_DBELL_7_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_7_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
#define HSP_DBELL_7_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_7_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_7_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_7_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
#define HSP_DBELL_7_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
#define HSP_DBELL_7_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_7_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define HSP_DBELL_7_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
#define HSP_DBELL_7_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_7_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_7_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_7_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
#define HSP_DBELL_7_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
#define HSP_DBELL_7_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_7_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x710

// Reserved address 0x714

// Reserved address 0x718

// Reserved address 0x71c

// Reserved address 0x720

// Register HSP_DBELL_7_ENABLE_SLICE1_0
#define HSP_DBELL_7_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x724)
#define HSP_DBELL_7_ENABLE_SLICE1_0_SECURE                      0x0
#define HSP_DBELL_7_ENABLE_SLICE1_0_DUAL                        0x0
#define HSP_DBELL_7_ENABLE_SLICE1_0_SCR                         DB_7_REG_0
#define HSP_DBELL_7_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_7_REG_0
#define HSP_DBELL_7_ENABLE_SLICE1_0_WORD_COUNT                  0x1
#define HSP_DBELL_7_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register HSP_DBELL_7_RAW_SLICE1_0
#define HSP_DBELL_7_RAW_SLICE1_0                        MK_ADDR_CONST(0x728)
#define HSP_DBELL_7_RAW_SLICE1_0_SECURE                         0x0
#define HSP_DBELL_7_RAW_SLICE1_0_DUAL                   0x0
#define HSP_DBELL_7_RAW_SLICE1_0_SCR                    DB_7_REG_0
#define HSP_DBELL_7_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_7_REG_0
#define HSP_DBELL_7_RAW_SLICE1_0_WORD_COUNT                     0x1
#define HSP_DBELL_7_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_7_RAW_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_RANGE                     31:16
#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_7_RAW_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_RANGE                     15:0
#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register HSP_DBELL_7_PENDING_SLICE1_0
#define HSP_DBELL_7_PENDING_SLICE1_0                    MK_ADDR_CONST(0x72c)
#define HSP_DBELL_7_PENDING_SLICE1_0_SECURE                     0x0
#define HSP_DBELL_7_PENDING_SLICE1_0_DUAL                       0x0
#define HSP_DBELL_7_PENDING_SLICE1_0_SCR                        DB_7_REG_0
#define HSP_DBELL_7_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_7_REG_0
#define HSP_DBELL_7_PENDING_SLICE1_0_WORD_COUNT                         0x1
#define HSP_DBELL_7_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_7_PENDING_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_RANGE                 31:16
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_7_PENDING_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_RANGE                 15:0
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_8_TRIGGER_0
#define HSP_DBELL_8_TRIGGER_0                   MK_ADDR_CONST(0x800)
#define HSP_DBELL_8_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_8_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_8_TRIGGER_0_SCR                       0
#define HSP_DBELL_8_TRIGGER_0_SCRREG                    0
#define HSP_DBELL_8_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_8_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_8_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_8_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_8_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
#define HSP_DBELL_8_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_8_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_8_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_8_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
#define HSP_DBELL_8_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
#define HSP_DBELL_8_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_8_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_8_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_8_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_8_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define HSP_DBELL_8_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register HSP_DBELL_8_ENABLE_0
#define HSP_DBELL_8_ENABLE_0                    MK_ADDR_CONST(0x804)
#define HSP_DBELL_8_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_8_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_8_ENABLE_0_SCR                        DB_8_REG_0
#define HSP_DBELL_8_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_8_REG_0
#define HSP_DBELL_8_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_8_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_8_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_8_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_8_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_8_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_8_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_8_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_8_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_8_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_8_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_8_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_8_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_8_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_8_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_8_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_8_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_8_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_8_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_8_RAW_0
#define HSP_DBELL_8_RAW_0                       MK_ADDR_CONST(0x808)
#define HSP_DBELL_8_RAW_0_SECURE                        0x0
#define HSP_DBELL_8_RAW_0_DUAL                  0x0
#define HSP_DBELL_8_RAW_0_SCR                   DB_8_REG_0
#define HSP_DBELL_8_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_8_REG_0
#define HSP_DBELL_8_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_8_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
#define HSP_DBELL_8_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_8_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_8_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_8_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
#define HSP_DBELL_8_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
#define HSP_DBELL_8_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_8_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_8_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define HSP_DBELL_8_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
#define HSP_DBELL_8_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_8_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_8_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_8_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
#define HSP_DBELL_8_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
#define HSP_DBELL_8_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_8_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_8_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register HSP_DBELL_8_PENDING_0
#define HSP_DBELL_8_PENDING_0                   MK_ADDR_CONST(0x80c)
#define HSP_DBELL_8_PENDING_0_SECURE                    0x0
#define HSP_DBELL_8_PENDING_0_DUAL                      0x0
#define HSP_DBELL_8_PENDING_0_SCR                       DB_8_REG_0
#define HSP_DBELL_8_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_8_REG_0
#define HSP_DBELL_8_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_8_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
#define HSP_DBELL_8_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_8_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_8_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_8_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
#define HSP_DBELL_8_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
#define HSP_DBELL_8_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_8_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_8_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define HSP_DBELL_8_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
#define HSP_DBELL_8_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_8_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_8_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_8_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
#define HSP_DBELL_8_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
#define HSP_DBELL_8_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_8_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_8_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x810

// Reserved address 0x814

// Reserved address 0x818

// Reserved address 0x81c

// Reserved address 0x820

// Register HSP_DBELL_8_ENABLE_SLICE1_0
#define HSP_DBELL_8_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x824)
#define HSP_DBELL_8_ENABLE_SLICE1_0_SECURE                      0x0
#define HSP_DBELL_8_ENABLE_SLICE1_0_DUAL                        0x0
#define HSP_DBELL_8_ENABLE_SLICE1_0_SCR                         DB_8_REG_0
#define HSP_DBELL_8_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_8_REG_0
#define HSP_DBELL_8_ENABLE_SLICE1_0_WORD_COUNT                  0x1
#define HSP_DBELL_8_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register HSP_DBELL_8_RAW_SLICE1_0
#define HSP_DBELL_8_RAW_SLICE1_0                        MK_ADDR_CONST(0x828)
#define HSP_DBELL_8_RAW_SLICE1_0_SECURE                         0x0
#define HSP_DBELL_8_RAW_SLICE1_0_DUAL                   0x0
#define HSP_DBELL_8_RAW_SLICE1_0_SCR                    DB_8_REG_0
#define HSP_DBELL_8_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_8_REG_0
#define HSP_DBELL_8_RAW_SLICE1_0_WORD_COUNT                     0x1
#define HSP_DBELL_8_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_8_RAW_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_RANGE                     31:16
#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_8_RAW_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_RANGE                     15:0
#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register HSP_DBELL_8_PENDING_SLICE1_0
#define HSP_DBELL_8_PENDING_SLICE1_0                    MK_ADDR_CONST(0x82c)
#define HSP_DBELL_8_PENDING_SLICE1_0_SECURE                     0x0
#define HSP_DBELL_8_PENDING_SLICE1_0_DUAL                       0x0
#define HSP_DBELL_8_PENDING_SLICE1_0_SCR                        DB_8_REG_0
#define HSP_DBELL_8_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_8_REG_0
#define HSP_DBELL_8_PENDING_SLICE1_0_WORD_COUNT                         0x1
#define HSP_DBELL_8_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_8_PENDING_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_RANGE                 31:16
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_8_PENDING_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_RANGE                 15:0
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_9_TRIGGER_0
#define HSP_DBELL_9_TRIGGER_0                   MK_ADDR_CONST(0x900)
#define HSP_DBELL_9_TRIGGER_0_SECURE                    0x0
#define HSP_DBELL_9_TRIGGER_0_DUAL                      0x0
#define HSP_DBELL_9_TRIGGER_0_SCR                       0
#define HSP_DBELL_9_TRIGGER_0_SCRREG                    0
#define HSP_DBELL_9_TRIGGER_0_WORD_COUNT                        0x1
#define HSP_DBELL_9_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_9_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_9_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_9_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
#define HSP_DBELL_9_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_9_TRIGGER_0_DUMMY_SHIFT)
#define HSP_DBELL_9_TRIGGER_0_DUMMY_RANGE                       31:0
#define HSP_DBELL_9_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
#define HSP_DBELL_9_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
#define HSP_DBELL_9_TRIGGER_0_DUMMY_WOFFSET                     0x0
#define HSP_DBELL_9_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_9_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_9_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_9_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define HSP_DBELL_9_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register HSP_DBELL_9_ENABLE_0
#define HSP_DBELL_9_ENABLE_0                    MK_ADDR_CONST(0x904)
#define HSP_DBELL_9_ENABLE_0_SECURE                     0x0
#define HSP_DBELL_9_ENABLE_0_DUAL                       0x0
#define HSP_DBELL_9_ENABLE_0_SCR                        DB_9_REG_0
#define HSP_DBELL_9_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_9_REG_0
#define HSP_DBELL_9_ENABLE_0_WORD_COUNT                         0x1
#define HSP_DBELL_9_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_9_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_9_ENABLE_0_MAP1_SHIFT)
#define HSP_DBELL_9_ENABLE_0_MAP1_RANGE                 31:16
#define HSP_DBELL_9_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_9_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_9_ENABLE_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_9_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_9_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_9_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_9_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_9_ENABLE_0_MAP0_SHIFT)
#define HSP_DBELL_9_ENABLE_0_MAP0_RANGE                 15:0
#define HSP_DBELL_9_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_9_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_9_ENABLE_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_9_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_9_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_DBELL_9_RAW_0
#define HSP_DBELL_9_RAW_0                       MK_ADDR_CONST(0x908)
#define HSP_DBELL_9_RAW_0_SECURE                        0x0
#define HSP_DBELL_9_RAW_0_DUAL                  0x0
#define HSP_DBELL_9_RAW_0_SCR                   DB_9_REG_0
#define HSP_DBELL_9_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_9_REG_0
#define HSP_DBELL_9_RAW_0_WORD_COUNT                    0x1
#define HSP_DBELL_9_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
#define HSP_DBELL_9_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_9_RAW_0_MAP1_SHIFT)
#define HSP_DBELL_9_RAW_0_MAP1_RANGE                    31:16
#define HSP_DBELL_9_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
#define HSP_DBELL_9_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
#define HSP_DBELL_9_RAW_0_MAP1_WOFFSET                  0x0
#define HSP_DBELL_9_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_9_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define HSP_DBELL_9_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
#define HSP_DBELL_9_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_9_RAW_0_MAP0_SHIFT)
#define HSP_DBELL_9_RAW_0_MAP0_RANGE                    15:0
#define HSP_DBELL_9_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
#define HSP_DBELL_9_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
#define HSP_DBELL_9_RAW_0_MAP0_WOFFSET                  0x0
#define HSP_DBELL_9_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define HSP_DBELL_9_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register HSP_DBELL_9_PENDING_0
#define HSP_DBELL_9_PENDING_0                   MK_ADDR_CONST(0x90c)
#define HSP_DBELL_9_PENDING_0_SECURE                    0x0
#define HSP_DBELL_9_PENDING_0_DUAL                      0x0
#define HSP_DBELL_9_PENDING_0_SCR                       DB_9_REG_0
#define HSP_DBELL_9_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_9_REG_0
#define HSP_DBELL_9_PENDING_0_WORD_COUNT                        0x1
#define HSP_DBELL_9_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
#define HSP_DBELL_9_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_9_PENDING_0_MAP1_SHIFT)
#define HSP_DBELL_9_PENDING_0_MAP1_RANGE                        31:16
#define HSP_DBELL_9_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
#define HSP_DBELL_9_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
#define HSP_DBELL_9_PENDING_0_MAP1_WOFFSET                      0x0
#define HSP_DBELL_9_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_9_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define HSP_DBELL_9_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
#define HSP_DBELL_9_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_9_PENDING_0_MAP0_SHIFT)
#define HSP_DBELL_9_PENDING_0_MAP0_RANGE                        15:0
#define HSP_DBELL_9_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
#define HSP_DBELL_9_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
#define HSP_DBELL_9_PENDING_0_MAP0_WOFFSET                      0x0
#define HSP_DBELL_9_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
#define HSP_DBELL_9_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x910

// Reserved address 0x914

// Reserved address 0x918

// Reserved address 0x91c

// Reserved address 0x920

// Register HSP_DBELL_9_ENABLE_SLICE1_0
#define HSP_DBELL_9_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x924)
#define HSP_DBELL_9_ENABLE_SLICE1_0_SECURE                      0x0
#define HSP_DBELL_9_ENABLE_SLICE1_0_DUAL                        0x0
#define HSP_DBELL_9_ENABLE_SLICE1_0_SCR                         DB_9_REG_0
#define HSP_DBELL_9_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_9_REG_0
#define HSP_DBELL_9_ENABLE_SLICE1_0_WORD_COUNT                  0x1
#define HSP_DBELL_9_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register HSP_DBELL_9_RAW_SLICE1_0
#define HSP_DBELL_9_RAW_SLICE1_0                        MK_ADDR_CONST(0x928)
#define HSP_DBELL_9_RAW_SLICE1_0_SECURE                         0x0
#define HSP_DBELL_9_RAW_SLICE1_0_DUAL                   0x0
#define HSP_DBELL_9_RAW_SLICE1_0_SCR                    DB_9_REG_0
#define HSP_DBELL_9_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_9_REG_0
#define HSP_DBELL_9_RAW_SLICE1_0_WORD_COUNT                     0x1
#define HSP_DBELL_9_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_9_RAW_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_RANGE                     31:16
#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_9_RAW_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_RANGE                     15:0
#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register HSP_DBELL_9_PENDING_SLICE1_0
#define HSP_DBELL_9_PENDING_SLICE1_0                    MK_ADDR_CONST(0x92c)
#define HSP_DBELL_9_PENDING_SLICE1_0_SECURE                     0x0
#define HSP_DBELL_9_PENDING_SLICE1_0_DUAL                       0x0
#define HSP_DBELL_9_PENDING_SLICE1_0_SCR                        DB_9_REG_0
#define HSP_DBELL_9_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_9_REG_0
#define HSP_DBELL_9_PENDING_SLICE1_0_WORD_COUNT                         0x1
#define HSP_DBELL_9_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_9_PENDING_SLICE1_0_MAP1_SHIFT)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_RANGE                 31:16
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_9_PENDING_SLICE1_0_MAP0_SHIFT)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_RANGE                 15:0
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARHSP_DBELL_REGS(_op_) \
_op_(HSP_DBELL_0_TRIGGER_0) \
_op_(HSP_DBELL_0_ENABLE_0) \
_op_(HSP_DBELL_0_RAW_0) \
_op_(HSP_DBELL_0_PENDING_0) \
_op_(HSP_DBELL_0_ENABLE_SLICE1_0) \
_op_(HSP_DBELL_0_RAW_SLICE1_0) \
_op_(HSP_DBELL_0_PENDING_SLICE1_0) \
_op_(HSP_DBELL_1_TRIGGER_0) \
_op_(HSP_DBELL_1_ENABLE_0) \
_op_(HSP_DBELL_1_RAW_0) \
_op_(HSP_DBELL_1_PENDING_0) \
_op_(HSP_DBELL_1_ENABLE_SLICE1_0) \
_op_(HSP_DBELL_1_RAW_SLICE1_0) \
_op_(HSP_DBELL_1_PENDING_SLICE1_0) \
_op_(HSP_DBELL_2_TRIGGER_0) \
_op_(HSP_DBELL_2_ENABLE_0) \
_op_(HSP_DBELL_2_RAW_0) \
_op_(HSP_DBELL_2_PENDING_0) \
_op_(HSP_DBELL_2_ENABLE_SLICE1_0) \
_op_(HSP_DBELL_2_RAW_SLICE1_0) \
_op_(HSP_DBELL_2_PENDING_SLICE1_0) \
_op_(HSP_DBELL_3_TRIGGER_0) \
_op_(HSP_DBELL_3_ENABLE_0) \
_op_(HSP_DBELL_3_RAW_0) \
_op_(HSP_DBELL_3_PENDING_0) \
_op_(HSP_DBELL_3_ENABLE_SLICE1_0) \
_op_(HSP_DBELL_3_RAW_SLICE1_0) \
_op_(HSP_DBELL_3_PENDING_SLICE1_0) \
_op_(HSP_DBELL_4_TRIGGER_0) \
_op_(HSP_DBELL_4_ENABLE_0) \
_op_(HSP_DBELL_4_RAW_0) \
_op_(HSP_DBELL_4_PENDING_0) \
_op_(HSP_DBELL_4_ENABLE_SLICE1_0) \
_op_(HSP_DBELL_4_RAW_SLICE1_0) \
_op_(HSP_DBELL_4_PENDING_SLICE1_0) \
_op_(HSP_DBELL_5_TRIGGER_0) \
_op_(HSP_DBELL_5_ENABLE_0) \
_op_(HSP_DBELL_5_RAW_0) \
_op_(HSP_DBELL_5_PENDING_0) \
_op_(HSP_DBELL_5_ENABLE_SLICE1_0) \
_op_(HSP_DBELL_5_RAW_SLICE1_0) \
_op_(HSP_DBELL_5_PENDING_SLICE1_0) \
_op_(HSP_DBELL_6_TRIGGER_0) \
_op_(HSP_DBELL_6_ENABLE_0) \
_op_(HSP_DBELL_6_RAW_0) \
_op_(HSP_DBELL_6_PENDING_0) \
_op_(HSP_DBELL_6_ENABLE_SLICE1_0) \
_op_(HSP_DBELL_6_RAW_SLICE1_0) \
_op_(HSP_DBELL_6_PENDING_SLICE1_0) \
_op_(HSP_DBELL_7_TRIGGER_0) \
_op_(HSP_DBELL_7_ENABLE_0) \
_op_(HSP_DBELL_7_RAW_0) \
_op_(HSP_DBELL_7_PENDING_0) \
_op_(HSP_DBELL_7_ENABLE_SLICE1_0) \
_op_(HSP_DBELL_7_RAW_SLICE1_0) \
_op_(HSP_DBELL_7_PENDING_SLICE1_0) \
_op_(HSP_DBELL_8_TRIGGER_0) \
_op_(HSP_DBELL_8_ENABLE_0) \
_op_(HSP_DBELL_8_RAW_0) \
_op_(HSP_DBELL_8_PENDING_0) \
_op_(HSP_DBELL_8_ENABLE_SLICE1_0) \
_op_(HSP_DBELL_8_RAW_SLICE1_0) \
_op_(HSP_DBELL_8_PENDING_SLICE1_0) \
_op_(HSP_DBELL_9_TRIGGER_0) \
_op_(HSP_DBELL_9_ENABLE_0) \
_op_(HSP_DBELL_9_RAW_0) \
_op_(HSP_DBELL_9_PENDING_0) \
_op_(HSP_DBELL_9_ENABLE_SLICE1_0) \
_op_(HSP_DBELL_9_RAW_SLICE1_0) \
_op_(HSP_DBELL_9_PENDING_SLICE1_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_HSP        0x00000000

//
// ARHSP_DBELL REGISTER BANKS
//

#define HSP0_FIRST_REG 0x0000 // HSP_DBELL_0_TRIGGER_0
#define HSP0_LAST_REG 0x000c // HSP_DBELL_0_PENDING_0
#define HSP1_FIRST_REG 0x0024 // HSP_DBELL_0_ENABLE_SLICE1_0
#define HSP1_LAST_REG 0x002c // HSP_DBELL_0_PENDING_SLICE1_0
#define HSP2_FIRST_REG 0x0100 // HSP_DBELL_1_TRIGGER_0
#define HSP2_LAST_REG 0x010c // HSP_DBELL_1_PENDING_0
#define HSP3_FIRST_REG 0x0124 // HSP_DBELL_1_ENABLE_SLICE1_0
#define HSP3_LAST_REG 0x012c // HSP_DBELL_1_PENDING_SLICE1_0
#define HSP4_FIRST_REG 0x0200 // HSP_DBELL_2_TRIGGER_0
#define HSP4_LAST_REG 0x020c // HSP_DBELL_2_PENDING_0
#define HSP5_FIRST_REG 0x0224 // HSP_DBELL_2_ENABLE_SLICE1_0
#define HSP5_LAST_REG 0x022c // HSP_DBELL_2_PENDING_SLICE1_0
#define HSP6_FIRST_REG 0x0300 // HSP_DBELL_3_TRIGGER_0
#define HSP6_LAST_REG 0x030c // HSP_DBELL_3_PENDING_0
#define HSP7_FIRST_REG 0x0324 // HSP_DBELL_3_ENABLE_SLICE1_0
#define HSP7_LAST_REG 0x032c // HSP_DBELL_3_PENDING_SLICE1_0
#define HSP8_FIRST_REG 0x0400 // HSP_DBELL_4_TRIGGER_0
#define HSP8_LAST_REG 0x040c // HSP_DBELL_4_PENDING_0
#define HSP9_FIRST_REG 0x0424 // HSP_DBELL_4_ENABLE_SLICE1_0
#define HSP9_LAST_REG 0x042c // HSP_DBELL_4_PENDING_SLICE1_0
#define HSP10_FIRST_REG 0x0500 // HSP_DBELL_5_TRIGGER_0
#define HSP10_LAST_REG 0x050c // HSP_DBELL_5_PENDING_0
#define HSP11_FIRST_REG 0x0524 // HSP_DBELL_5_ENABLE_SLICE1_0
#define HSP11_LAST_REG 0x052c // HSP_DBELL_5_PENDING_SLICE1_0
#define HSP12_FIRST_REG 0x0600 // HSP_DBELL_6_TRIGGER_0
#define HSP12_LAST_REG 0x060c // HSP_DBELL_6_PENDING_0
#define HSP13_FIRST_REG 0x0624 // HSP_DBELL_6_ENABLE_SLICE1_0
#define HSP13_LAST_REG 0x062c // HSP_DBELL_6_PENDING_SLICE1_0
#define HSP14_FIRST_REG 0x0700 // HSP_DBELL_7_TRIGGER_0
#define HSP14_LAST_REG 0x070c // HSP_DBELL_7_PENDING_0
#define HSP15_FIRST_REG 0x0724 // HSP_DBELL_7_ENABLE_SLICE1_0
#define HSP15_LAST_REG 0x072c // HSP_DBELL_7_PENDING_SLICE1_0
#define HSP16_FIRST_REG 0x0800 // HSP_DBELL_8_TRIGGER_0
#define HSP16_LAST_REG 0x080c // HSP_DBELL_8_PENDING_0
#define HSP17_FIRST_REG 0x0824 // HSP_DBELL_8_ENABLE_SLICE1_0
#define HSP17_LAST_REG 0x082c // HSP_DBELL_8_PENDING_SLICE1_0
#define HSP18_FIRST_REG 0x0900 // HSP_DBELL_9_TRIGGER_0
#define HSP18_LAST_REG 0x090c // HSP_DBELL_9_PENDING_0
#define HSP19_FIRST_REG 0x0924 // HSP_DBELL_9_ENABLE_SLICE1_0
#define HSP19_LAST_REG 0x092c // HSP_DBELL_9_PENDING_SLICE1_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARHSP_DBELL_H_INC
