//
// Copyright (c) 2021 NVIDIA Corporation.
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARTKE_TOP_H_INC
#define ARTKE_TOP_H_INC
#define NV_MOBILE_ARTKE_TOP_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARTKE_TOP_H_SCRREG_NOMENCLATURE EXACT


// Register TKE_TOP_SHARED_TKETSC0_0
#define TKE_TOP_SHARED_TKETSC0_0                        MK_ADDR_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC0_0_SECURE                         0x0
#define TKE_TOP_SHARED_TKETSC0_0_DUAL                   0x0
#define TKE_TOP_SHARED_TKETSC0_0_SCR                    TKESCR_0
#define TKE_TOP_SHARED_TKETSC0_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKETSC0_0_WORD_COUNT                     0x1
#define TKE_TOP_SHARED_TKETSC0_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC0_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKETSC0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC0_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKETSC0_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC0_0_CV_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKETSC0_0_CV_FIELD                       MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKETSC0_0_CV_SHIFT)
#define TKE_TOP_SHARED_TKETSC0_0_CV_RANGE                       31:0
#define TKE_TOP_SHARED_TKETSC0_0_CV_MSB                 MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKETSC0_0_CV_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKETSC0_0_CV_WOFFSET                     0x0
#define TKE_TOP_SHARED_TKETSC0_0_CV_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC0_0_CV_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKETSC0_0_CV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC0_0_CV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC0_0_CV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC0_0_CV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKETSC1_0
#define TKE_TOP_SHARED_TKETSC1_0                        MK_ADDR_CONST(0x4)
#define TKE_TOP_SHARED_TKETSC1_0_SECURE                         0x0
#define TKE_TOP_SHARED_TKETSC1_0_DUAL                   0x0
#define TKE_TOP_SHARED_TKETSC1_0_SCR                    TKESCR_0
#define TKE_TOP_SHARED_TKETSC1_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKETSC1_0_WORD_COUNT                     0x1
#define TKE_TOP_SHARED_TKETSC1_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKETSC1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKETSC1_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC1_0_CV_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKETSC1_0_CV_FIELD                       MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKETSC1_0_CV_SHIFT)
#define TKE_TOP_SHARED_TKETSC1_0_CV_RANGE                       31:0
#define TKE_TOP_SHARED_TKETSC1_0_CV_MSB                 MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKETSC1_0_CV_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKETSC1_0_CV_WOFFSET                     0x0
#define TKE_TOP_SHARED_TKETSC1_0_CV_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC1_0_CV_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKETSC1_0_CV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC1_0_CV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC1_0_CV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKETSC1_0_CV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEUSEC_0
#define TKE_TOP_SHARED_TKEUSEC_0                        MK_ADDR_CONST(0x8)
#define TKE_TOP_SHARED_TKEUSEC_0_SECURE                         0x0
#define TKE_TOP_SHARED_TKEUSEC_0_DUAL                   0x0
#define TKE_TOP_SHARED_TKEUSEC_0_SCR                    TKESCR_0
#define TKE_TOP_SHARED_TKEUSEC_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEUSEC_0_WORD_COUNT                     0x1
#define TKE_TOP_SHARED_TKEUSEC_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEUSEC_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEUSEC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEUSEC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEUSEC_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEUSEC_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEUSEC_0_CV_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEUSEC_0_CV_FIELD                       MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEUSEC_0_CV_SHIFT)
#define TKE_TOP_SHARED_TKEUSEC_0_CV_RANGE                       31:0
#define TKE_TOP_SHARED_TKEUSEC_0_CV_MSB                 MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEUSEC_0_CV_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEUSEC_0_CV_WOFFSET                     0x0
#define TKE_TOP_SHARED_TKEUSEC_0_CV_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEUSEC_0_CV_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEUSEC_0_CV_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEUSEC_0_CV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEUSEC_0_CV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEUSEC_0_CV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEOSC_0
#define TKE_TOP_SHARED_TKEOSC_0                 MK_ADDR_CONST(0xc)
#define TKE_TOP_SHARED_TKEOSC_0_SECURE                  0x0
#define TKE_TOP_SHARED_TKEOSC_0_DUAL                    0x0
#define TKE_TOP_SHARED_TKEOSC_0_SCR                     TKESCR_0
#define TKE_TOP_SHARED_TKEOSC_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEOSC_0_WORD_COUNT                      0x1
#define TKE_TOP_SHARED_TKEOSC_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEOSC_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEOSC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEOSC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEOSC_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEOSC_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEOSC_0_CV_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEOSC_0_CV_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEOSC_0_CV_SHIFT)
#define TKE_TOP_SHARED_TKEOSC_0_CV_RANGE                        31:0
#define TKE_TOP_SHARED_TKEOSC_0_CV_MSB                  MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEOSC_0_CV_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEOSC_0_CV_WOFFSET                      0x0
#define TKE_TOP_SHARED_TKEOSC_0_CV_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEOSC_0_CV_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEOSC_0_CV_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEOSC_0_CV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEOSC_0_CV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEOSC_0_CV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKECR_0
#define TKE_TOP_SHARED_TKECR_0                  MK_ADDR_CONST(0x10)
#define TKE_TOP_SHARED_TKECR_0_SECURE                   0x0
#define TKE_TOP_SHARED_TKECR_0_DUAL                     0x0
#define TKE_TOP_SHARED_TKECR_0_SCR                      TKESCR_0
#define TKE_TOP_SHARED_TKECR_0_SCRREG                   TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKECR_0_WORD_COUNT                       0x1
#define TKE_TOP_SHARED_TKECR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_RESET_MASK                       MK_MASK_CONST(0xf)
#define TKE_TOP_SHARED_TKECR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_READ_MASK                        MK_MASK_CONST(0xf)
#define TKE_TOP_SHARED_TKECR_0_WRITE_MASK                       MK_MASK_CONST(0xf)
#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_SHARED_TKECR_0_TSC_DIS_SHIFT)
#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_RANGE                    0:0
#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_MSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_WOFFSET                  0x0
#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_SHIFT                   MK_SHIFT_CONST(1)
#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_SHARED_TKECR_0_USEC_DIS_SHIFT)
#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_RANGE                   1:1
#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_MSB                     MK_SHIFT_CONST(1)
#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_LSB                     MK_SHIFT_CONST(1)
#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_WOFFSET                 0x0
#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_SHIFT                    MK_SHIFT_CONST(2)
#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_SHARED_TKECR_0_OSC_DIS_SHIFT)
#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_RANGE                    2:2
#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_MSB                      MK_SHIFT_CONST(2)
#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_LSB                      MK_SHIFT_CONST(2)
#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_WOFFSET                  0x0
#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define TKE_TOP_SHARED_TKECR_0_HDBG_SHIFT                       MK_SHIFT_CONST(3)
#define TKE_TOP_SHARED_TKECR_0_HDBG_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_SHARED_TKECR_0_HDBG_SHIFT)
#define TKE_TOP_SHARED_TKECR_0_HDBG_RANGE                       3:3
#define TKE_TOP_SHARED_TKECR_0_HDBG_MSB                 MK_SHIFT_CONST(3)
#define TKE_TOP_SHARED_TKECR_0_HDBG_LSB                 MK_SHIFT_CONST(3)
#define TKE_TOP_SHARED_TKECR_0_HDBG_WOFFSET                     0x0
#define TKE_TOP_SHARED_TKECR_0_HDBG_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_HDBG_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKECR_0_HDBG_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_HDBG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKECR_0_HDBG_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKECR_0_HDBG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_CLK_OVR_ON_0
#define TKE_TOP_SHARED_CLK_OVR_ON_0                     MK_ADDR_CONST(0x14)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_SECURE                      0x0
#define TKE_TOP_SHARED_CLK_OVR_ON_0_DUAL                        0x0
#define TKE_TOP_SHARED_CLK_OVR_ON_0_SCR                         TKESCR_0
#define TKE_TOP_SHARED_CLK_OVR_ON_0_SCRREG                      TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_CLK_OVR_ON_0_WORD_COUNT                  0x1
#define TKE_TOP_SHARED_CLK_OVR_ON_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_READ_MASK                   MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_SHIFT)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_RANGE                   0:0
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_MSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_WOFFSET                 0x0
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_DISABLE                 MK_ENUM_CONST(0)
#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_ENABLE                  MK_ENUM_CONST(1)


// Register TKE_TOP_SHARED_TKEIE0_0
#define TKE_TOP_SHARED_TKEIE0_0                 MK_ADDR_CONST(0x100)
#define TKE_TOP_SHARED_TKEIE0_0_SECURE                  0x0
#define TKE_TOP_SHARED_TKEIE0_0_DUAL                    0x0
#define TKE_TOP_SHARED_TKEIE0_0_SCR                     TKESCR_0
#define TKE_TOP_SHARED_TKEIE0_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE0_0_WORD_COUNT                      0x1
#define TKE_TOP_SHARED_TKEIE0_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE0_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE0_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE0_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE0_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_RANGE                 31:0
#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_WOFFSET                       0x0
#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE1_0
#define TKE_TOP_SHARED_TKEIE1_0                 MK_ADDR_CONST(0x104)
#define TKE_TOP_SHARED_TKEIE1_0_SECURE                  0x0
#define TKE_TOP_SHARED_TKEIE1_0_DUAL                    0x0
#define TKE_TOP_SHARED_TKEIE1_0_SCR                     TKESCR_0
#define TKE_TOP_SHARED_TKEIE1_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE1_0_WORD_COUNT                      0x1
#define TKE_TOP_SHARED_TKEIE1_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE1_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE1_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE1_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE1_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_RANGE                 31:0
#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_WOFFSET                       0x0
#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE2_0
#define TKE_TOP_SHARED_TKEIE2_0                 MK_ADDR_CONST(0x108)
#define TKE_TOP_SHARED_TKEIE2_0_SECURE                  0x0
#define TKE_TOP_SHARED_TKEIE2_0_DUAL                    0x0
#define TKE_TOP_SHARED_TKEIE2_0_SCR                     TKESCR_0
#define TKE_TOP_SHARED_TKEIE2_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE2_0_WORD_COUNT                      0x1
#define TKE_TOP_SHARED_TKEIE2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE2_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE2_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE2_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE2_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_RANGE                 31:0
#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_WOFFSET                       0x0
#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE3_0
#define TKE_TOP_SHARED_TKEIE3_0                 MK_ADDR_CONST(0x10c)
#define TKE_TOP_SHARED_TKEIE3_0_SECURE                  0x0
#define TKE_TOP_SHARED_TKEIE3_0_DUAL                    0x0
#define TKE_TOP_SHARED_TKEIE3_0_SCR                     TKESCR_0
#define TKE_TOP_SHARED_TKEIE3_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE3_0_WORD_COUNT                      0x1
#define TKE_TOP_SHARED_TKEIE3_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE3_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE3_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE3_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE3_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_RANGE                 31:0
#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_WOFFSET                       0x0
#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE4_0
#define TKE_TOP_SHARED_TKEIE4_0                 MK_ADDR_CONST(0x110)
#define TKE_TOP_SHARED_TKEIE4_0_SECURE                  0x0
#define TKE_TOP_SHARED_TKEIE4_0_DUAL                    0x0
#define TKE_TOP_SHARED_TKEIE4_0_SCR                     TKESCR_0
#define TKE_TOP_SHARED_TKEIE4_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE4_0_WORD_COUNT                      0x1
#define TKE_TOP_SHARED_TKEIE4_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE4_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE4_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE4_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE4_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE4_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE4_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_RANGE                 31:0
#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_WOFFSET                       0x0
#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE5_0
#define TKE_TOP_SHARED_TKEIE5_0                 MK_ADDR_CONST(0x114)
#define TKE_TOP_SHARED_TKEIE5_0_SECURE                  0x0
#define TKE_TOP_SHARED_TKEIE5_0_DUAL                    0x0
#define TKE_TOP_SHARED_TKEIE5_0_SCR                     TKESCR_0
#define TKE_TOP_SHARED_TKEIE5_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE5_0_WORD_COUNT                      0x1
#define TKE_TOP_SHARED_TKEIE5_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE5_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE5_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE5_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE5_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE5_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE5_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_RANGE                 31:0
#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_WOFFSET                       0x0
#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE6_0
#define TKE_TOP_SHARED_TKEIE6_0                 MK_ADDR_CONST(0x118)
#define TKE_TOP_SHARED_TKEIE6_0_SECURE                  0x0
#define TKE_TOP_SHARED_TKEIE6_0_DUAL                    0x0
#define TKE_TOP_SHARED_TKEIE6_0_SCR                     TKESCR_0
#define TKE_TOP_SHARED_TKEIE6_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE6_0_WORD_COUNT                      0x1
#define TKE_TOP_SHARED_TKEIE6_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE6_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE6_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE6_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE6_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE6_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE6_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_RANGE                 31:0
#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_WOFFSET                       0x0
#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE7_0
#define TKE_TOP_SHARED_TKEIE7_0                 MK_ADDR_CONST(0x11c)
#define TKE_TOP_SHARED_TKEIE7_0_SECURE                  0x0
#define TKE_TOP_SHARED_TKEIE7_0_DUAL                    0x0
#define TKE_TOP_SHARED_TKEIE7_0_SCR                     TKESCR_0
#define TKE_TOP_SHARED_TKEIE7_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE7_0_WORD_COUNT                      0x1
#define TKE_TOP_SHARED_TKEIE7_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE7_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE7_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE7_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE7_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE7_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE7_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_RANGE                 31:0
#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_WOFFSET                       0x0
#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE8_0
#define TKE_TOP_SHARED_TKEIE8_0                 MK_ADDR_CONST(0x120)
#define TKE_TOP_SHARED_TKEIE8_0_SECURE                  0x0
#define TKE_TOP_SHARED_TKEIE8_0_DUAL                    0x0
#define TKE_TOP_SHARED_TKEIE8_0_SCR                     TKESCR_0
#define TKE_TOP_SHARED_TKEIE8_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE8_0_WORD_COUNT                      0x1
#define TKE_TOP_SHARED_TKEIE8_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE8_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE8_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE8_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE8_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE8_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE8_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_RANGE                 31:0
#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_WOFFSET                       0x0
#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE9_0
#define TKE_TOP_SHARED_TKEIE9_0                 MK_ADDR_CONST(0x124)
#define TKE_TOP_SHARED_TKEIE9_0_SECURE                  0x0
#define TKE_TOP_SHARED_TKEIE9_0_DUAL                    0x0
#define TKE_TOP_SHARED_TKEIE9_0_SCR                     TKESCR_0
#define TKE_TOP_SHARED_TKEIE9_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE9_0_WORD_COUNT                      0x1
#define TKE_TOP_SHARED_TKEIE9_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE9_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE9_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE9_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE9_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE9_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE9_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_RANGE                 31:0
#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_WOFFSET                       0x0
#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE10_0
#define TKE_TOP_SHARED_TKEIE10_0                        MK_ADDR_CONST(0x128)
#define TKE_TOP_SHARED_TKEIE10_0_SECURE                         0x0
#define TKE_TOP_SHARED_TKEIE10_0_DUAL                   0x0
#define TKE_TOP_SHARED_TKEIE10_0_SCR                    TKESCR_0
#define TKE_TOP_SHARED_TKEIE10_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE10_0_WORD_COUNT                     0x1
#define TKE_TOP_SHARED_TKEIE10_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE10_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE10_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE10_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE10_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE10_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE10_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_RANGE                        31:0
#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_MSB                  MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_WOFFSET                      0x0
#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE11_0
#define TKE_TOP_SHARED_TKEIE11_0                        MK_ADDR_CONST(0x12c)
#define TKE_TOP_SHARED_TKEIE11_0_SECURE                         0x0
#define TKE_TOP_SHARED_TKEIE11_0_DUAL                   0x0
#define TKE_TOP_SHARED_TKEIE11_0_SCR                    TKESCR_0
#define TKE_TOP_SHARED_TKEIE11_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE11_0_WORD_COUNT                     0x1
#define TKE_TOP_SHARED_TKEIE11_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE11_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE11_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE11_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE11_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE11_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE11_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_RANGE                        31:0
#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_MSB                  MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_WOFFSET                      0x0
#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE12_0
#define TKE_TOP_SHARED_TKEIE12_0                        MK_ADDR_CONST(0x130)
#define TKE_TOP_SHARED_TKEIE12_0_SECURE                         0x0
#define TKE_TOP_SHARED_TKEIE12_0_DUAL                   0x0
#define TKE_TOP_SHARED_TKEIE12_0_SCR                    TKESCR_0
#define TKE_TOP_SHARED_TKEIE12_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE12_0_WORD_COUNT                     0x1
#define TKE_TOP_SHARED_TKEIE12_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE12_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE12_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE12_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE12_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE12_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE12_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_RANGE                        31:0
#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_MSB                  MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_WOFFSET                      0x0
#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE13_0
#define TKE_TOP_SHARED_TKEIE13_0                        MK_ADDR_CONST(0x134)
#define TKE_TOP_SHARED_TKEIE13_0_SECURE                         0x0
#define TKE_TOP_SHARED_TKEIE13_0_DUAL                   0x0
#define TKE_TOP_SHARED_TKEIE13_0_SCR                    TKESCR_0
#define TKE_TOP_SHARED_TKEIE13_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE13_0_WORD_COUNT                     0x1
#define TKE_TOP_SHARED_TKEIE13_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE13_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE13_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE13_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE13_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE13_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE13_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_RANGE                        31:0
#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_MSB                  MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_WOFFSET                      0x0
#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE14_0
#define TKE_TOP_SHARED_TKEIE14_0                        MK_ADDR_CONST(0x138)
#define TKE_TOP_SHARED_TKEIE14_0_SECURE                         0x0
#define TKE_TOP_SHARED_TKEIE14_0_DUAL                   0x0
#define TKE_TOP_SHARED_TKEIE14_0_SCR                    TKESCR_0
#define TKE_TOP_SHARED_TKEIE14_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE14_0_WORD_COUNT                     0x1
#define TKE_TOP_SHARED_TKEIE14_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE14_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE14_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE14_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE14_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE14_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE14_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_RANGE                        31:0
#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_MSB                  MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_WOFFSET                      0x0
#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIE15_0
#define TKE_TOP_SHARED_TKEIE15_0                        MK_ADDR_CONST(0x13c)
#define TKE_TOP_SHARED_TKEIE15_0_SECURE                         0x0
#define TKE_TOP_SHARED_TKEIE15_0_DUAL                   0x0
#define TKE_TOP_SHARED_TKEIE15_0_SCR                    TKESCR_0
#define TKE_TOP_SHARED_TKEIE15_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIE15_0_WORD_COUNT                     0x1
#define TKE_TOP_SHARED_TKEIE15_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE15_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE15_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE15_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE15_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE15_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE15_0_EnableMap_SHIFT)
#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_RANGE                        31:0
#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_MSB                  MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_WOFFSET                      0x0
#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIV_0
#define TKE_TOP_SHARED_TKEIV_0                  MK_ADDR_CONST(0x200)
#define TKE_TOP_SHARED_TKEIV_0_SECURE                   0x0
#define TKE_TOP_SHARED_TKEIV_0_DUAL                     0x0
#define TKE_TOP_SHARED_TKEIV_0_SCR                      TKESCR_0
#define TKE_TOP_SHARED_TKEIV_0_SCRREG                   TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIV_0_WORD_COUNT                       0x1
#define TKE_TOP_SHARED_TKEIV_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIV_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define TKE_TOP_SHARED_TKEIV_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIV_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIV_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define TKE_TOP_SHARED_TKEIV_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIV_0_ValidMap_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIV_0_ValidMap_FIELD                   MK_FIELD_CONST(0xffff, TKE_TOP_SHARED_TKEIV_0_ValidMap_SHIFT)
#define TKE_TOP_SHARED_TKEIV_0_ValidMap_RANGE                   15:0
#define TKE_TOP_SHARED_TKEIV_0_ValidMap_MSB                     MK_SHIFT_CONST(15)
#define TKE_TOP_SHARED_TKEIV_0_ValidMap_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIV_0_ValidMap_WOFFSET                 0x0
#define TKE_TOP_SHARED_TKEIV_0_ValidMap_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIV_0_ValidMap_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define TKE_TOP_SHARED_TKEIV_0_ValidMap_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIV_0_ValidMap_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIV_0_ValidMap_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIV_0_ValidMap_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register TKE_TOP_SHARED_TKEIR_0
#define TKE_TOP_SHARED_TKEIR_0                  MK_ADDR_CONST(0x204)
#define TKE_TOP_SHARED_TKEIR_0_SECURE                   0x0
#define TKE_TOP_SHARED_TKEIR_0_DUAL                     0x0
#define TKE_TOP_SHARED_TKEIR_0_SCR                      TKESCR_0
#define TKE_TOP_SHARED_TKEIR_0_SCRREG                   TKE_TOP_SCR_TKESCR_0
#define TKE_TOP_SHARED_TKEIR_0_WORD_COUNT                       0x1
#define TKE_TOP_SHARED_TKEIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIR_0_RawMap_SHIFT                     MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIR_0_RawMap_FIELD                     MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIR_0_RawMap_SHIFT)
#define TKE_TOP_SHARED_TKEIR_0_RawMap_RANGE                     31:0
#define TKE_TOP_SHARED_TKEIR_0_RawMap_MSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_SHARED_TKEIR_0_RawMap_LSB                       MK_SHIFT_CONST(0)
#define TKE_TOP_SHARED_TKEIR_0_RawMap_WOFFSET                   0x0
#define TKE_TOP_SHARED_TKEIR_0_RawMap_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIR_0_RawMap_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define TKE_TOP_SHARED_TKEIR_0_RawMap_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIR_0_RawMap_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIR_0_RawMap_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define TKE_TOP_SHARED_TKEIR_0_RawMap_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR0_TMRCR_0
#define TKE_TOP_TIMER_TMR0_TMRCR_0                      MK_ADDR_CONST(0x10000)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR0_TMRCR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR0_TMRCR_0_SCR                  TMRSCR0_0
#define TKE_TOP_TIMER_TMR0_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR0_0
#define TKE_TOP_TIMER_TMR0_TMRCR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR0_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR0_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_RANGE                     31:31
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_WOFFSET                   0x0
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR0_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_RANGE                    30:30
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR0_TMRSR_0
#define TKE_TOP_TIMER_TMR0_TMRSR_0                      MK_ADDR_CONST(0x10004)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR0_TMRSR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR0_TMRSR_0_SCR                  TMRSCR0_0
#define TKE_TOP_TIMER_TMR0_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR0_0
#define TKE_TOP_TIMER_TMR0_TMRSR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR0_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_RANGE                       30:30
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR0_TMRCSSR_0
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0                    MK_ADDR_CONST(0x10008)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SCR                        TMRSCR0_0
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR0_0
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_RANGE                       1:0
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR0_TMRATR_0
#define TKE_TOP_TIMER_TMR0_TMRATR_0                     MK_ADDR_CONST(0x1000c)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR0_TMRATR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR0_TMRATR_0_SCR                         TMRSCR0_0
#define TKE_TOP_TIMER_TMR0_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR0_0
#define TKE_TOP_TIMER_TMR0_TMRATR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR0_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_RANGE                        29:0
#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_WOFFSET                      0x0
#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR1_TMRCR_0
#define TKE_TOP_TIMER_TMR1_TMRCR_0                      MK_ADDR_CONST(0x20000)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR1_TMRCR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR1_TMRCR_0_SCR                  TMRSCR1_0
#define TKE_TOP_TIMER_TMR1_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR1_0
#define TKE_TOP_TIMER_TMR1_TMRCR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR1_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR1_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_RANGE                     31:31
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_WOFFSET                   0x0
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR1_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_RANGE                    30:30
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR1_TMRSR_0
#define TKE_TOP_TIMER_TMR1_TMRSR_0                      MK_ADDR_CONST(0x20004)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR1_TMRSR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR1_TMRSR_0_SCR                  TMRSCR1_0
#define TKE_TOP_TIMER_TMR1_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR1_0
#define TKE_TOP_TIMER_TMR1_TMRSR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR1_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_RANGE                       30:30
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR1_TMRCSSR_0
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0                    MK_ADDR_CONST(0x20008)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SCR                        TMRSCR1_0
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR1_0
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_RANGE                       1:0
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR1_TMRATR_0
#define TKE_TOP_TIMER_TMR1_TMRATR_0                     MK_ADDR_CONST(0x2000c)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR1_TMRATR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR1_TMRATR_0_SCR                         TMRSCR1_0
#define TKE_TOP_TIMER_TMR1_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR1_0
#define TKE_TOP_TIMER_TMR1_TMRATR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR1_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_RANGE                        29:0
#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_WOFFSET                      0x0
#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR2_TMRCR_0
#define TKE_TOP_TIMER_TMR2_TMRCR_0                      MK_ADDR_CONST(0x30000)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR2_TMRCR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR2_TMRCR_0_SCR                  TMRSCR2_0
#define TKE_TOP_TIMER_TMR2_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR2_0
#define TKE_TOP_TIMER_TMR2_TMRCR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR2_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR2_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_RANGE                     31:31
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_WOFFSET                   0x0
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR2_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_RANGE                    30:30
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR2_TMRSR_0
#define TKE_TOP_TIMER_TMR2_TMRSR_0                      MK_ADDR_CONST(0x30004)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR2_TMRSR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR2_TMRSR_0_SCR                  TMRSCR2_0
#define TKE_TOP_TIMER_TMR2_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR2_0
#define TKE_TOP_TIMER_TMR2_TMRSR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR2_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_RANGE                       30:30
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR2_TMRCSSR_0
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0                    MK_ADDR_CONST(0x30008)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SCR                        TMRSCR2_0
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR2_0
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_RANGE                       1:0
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR2_TMRATR_0
#define TKE_TOP_TIMER_TMR2_TMRATR_0                     MK_ADDR_CONST(0x3000c)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR2_TMRATR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR2_TMRATR_0_SCR                         TMRSCR2_0
#define TKE_TOP_TIMER_TMR2_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR2_0
#define TKE_TOP_TIMER_TMR2_TMRATR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR2_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_RANGE                        29:0
#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_WOFFSET                      0x0
#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR3_TMRCR_0
#define TKE_TOP_TIMER_TMR3_TMRCR_0                      MK_ADDR_CONST(0x40000)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR3_TMRCR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR3_TMRCR_0_SCR                  TMRSCR3_0
#define TKE_TOP_TIMER_TMR3_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR3_0
#define TKE_TOP_TIMER_TMR3_TMRCR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR3_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR3_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_RANGE                     31:31
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_WOFFSET                   0x0
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR3_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_RANGE                    30:30
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR3_TMRSR_0
#define TKE_TOP_TIMER_TMR3_TMRSR_0                      MK_ADDR_CONST(0x40004)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR3_TMRSR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR3_TMRSR_0_SCR                  TMRSCR3_0
#define TKE_TOP_TIMER_TMR3_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR3_0
#define TKE_TOP_TIMER_TMR3_TMRSR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR3_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_RANGE                       30:30
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR3_TMRCSSR_0
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0                    MK_ADDR_CONST(0x40008)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SCR                        TMRSCR3_0
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR3_0
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_RANGE                       1:0
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR3_TMRATR_0
#define TKE_TOP_TIMER_TMR3_TMRATR_0                     MK_ADDR_CONST(0x4000c)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR3_TMRATR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR3_TMRATR_0_SCR                         TMRSCR3_0
#define TKE_TOP_TIMER_TMR3_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR3_0
#define TKE_TOP_TIMER_TMR3_TMRATR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR3_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_RANGE                        29:0
#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_WOFFSET                      0x0
#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR4_TMRCR_0
#define TKE_TOP_TIMER_TMR4_TMRCR_0                      MK_ADDR_CONST(0x50000)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR4_TMRCR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR4_TMRCR_0_SCR                  TMRSCR4_0
#define TKE_TOP_TIMER_TMR4_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR4_0
#define TKE_TOP_TIMER_TMR4_TMRCR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR4_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR4_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_RANGE                     31:31
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_WOFFSET                   0x0
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR4_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_RANGE                    30:30
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR4_TMRSR_0
#define TKE_TOP_TIMER_TMR4_TMRSR_0                      MK_ADDR_CONST(0x50004)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR4_TMRSR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR4_TMRSR_0_SCR                  TMRSCR4_0
#define TKE_TOP_TIMER_TMR4_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR4_0
#define TKE_TOP_TIMER_TMR4_TMRSR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR4_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_RANGE                       30:30
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR4_TMRCSSR_0
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0                    MK_ADDR_CONST(0x50008)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SCR                        TMRSCR4_0
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR4_0
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_RANGE                       1:0
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR4_TMRATR_0
#define TKE_TOP_TIMER_TMR4_TMRATR_0                     MK_ADDR_CONST(0x5000c)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR4_TMRATR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR4_TMRATR_0_SCR                         TMRSCR4_0
#define TKE_TOP_TIMER_TMR4_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR4_0
#define TKE_TOP_TIMER_TMR4_TMRATR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR4_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_RANGE                        29:0
#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_WOFFSET                      0x0
#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR5_TMRCR_0
#define TKE_TOP_TIMER_TMR5_TMRCR_0                      MK_ADDR_CONST(0x60000)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR5_TMRCR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR5_TMRCR_0_SCR                  TMRSCR5_0
#define TKE_TOP_TIMER_TMR5_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR5_0
#define TKE_TOP_TIMER_TMR5_TMRCR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR5_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR5_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_RANGE                     31:31
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_WOFFSET                   0x0
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR5_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_RANGE                    30:30
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR5_TMRSR_0
#define TKE_TOP_TIMER_TMR5_TMRSR_0                      MK_ADDR_CONST(0x60004)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR5_TMRSR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR5_TMRSR_0_SCR                  TMRSCR5_0
#define TKE_TOP_TIMER_TMR5_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR5_0
#define TKE_TOP_TIMER_TMR5_TMRSR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR5_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_RANGE                       30:30
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR5_TMRCSSR_0
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0                    MK_ADDR_CONST(0x60008)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SCR                        TMRSCR5_0
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR5_0
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_RANGE                       1:0
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR5_TMRATR_0
#define TKE_TOP_TIMER_TMR5_TMRATR_0                     MK_ADDR_CONST(0x6000c)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR5_TMRATR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR5_TMRATR_0_SCR                         TMRSCR5_0
#define TKE_TOP_TIMER_TMR5_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR5_0
#define TKE_TOP_TIMER_TMR5_TMRATR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR5_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_RANGE                        29:0
#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_WOFFSET                      0x0
#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR6_TMRCR_0
#define TKE_TOP_TIMER_TMR6_TMRCR_0                      MK_ADDR_CONST(0x70000)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR6_TMRCR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR6_TMRCR_0_SCR                  TMRSCR6_0
#define TKE_TOP_TIMER_TMR6_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR6_0
#define TKE_TOP_TIMER_TMR6_TMRCR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR6_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR6_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_RANGE                     31:31
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_WOFFSET                   0x0
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR6_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_RANGE                    30:30
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR6_TMRSR_0
#define TKE_TOP_TIMER_TMR6_TMRSR_0                      MK_ADDR_CONST(0x70004)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR6_TMRSR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR6_TMRSR_0_SCR                  TMRSCR6_0
#define TKE_TOP_TIMER_TMR6_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR6_0
#define TKE_TOP_TIMER_TMR6_TMRSR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR6_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_RANGE                       30:30
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR6_TMRCSSR_0
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0                    MK_ADDR_CONST(0x70008)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SCR                        TMRSCR6_0
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR6_0
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_RANGE                       1:0
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR6_TMRATR_0
#define TKE_TOP_TIMER_TMR6_TMRATR_0                     MK_ADDR_CONST(0x7000c)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR6_TMRATR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR6_TMRATR_0_SCR                         TMRSCR6_0
#define TKE_TOP_TIMER_TMR6_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR6_0
#define TKE_TOP_TIMER_TMR6_TMRATR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR6_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_RANGE                        29:0
#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_WOFFSET                      0x0
#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR7_TMRCR_0
#define TKE_TOP_TIMER_TMR7_TMRCR_0                      MK_ADDR_CONST(0x80000)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR7_TMRCR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR7_TMRCR_0_SCR                  TMRSCR7_0
#define TKE_TOP_TIMER_TMR7_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR7_0
#define TKE_TOP_TIMER_TMR7_TMRCR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR7_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR7_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_RANGE                     31:31
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_WOFFSET                   0x0
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR7_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_RANGE                    30:30
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR7_TMRSR_0
#define TKE_TOP_TIMER_TMR7_TMRSR_0                      MK_ADDR_CONST(0x80004)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR7_TMRSR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR7_TMRSR_0_SCR                  TMRSCR7_0
#define TKE_TOP_TIMER_TMR7_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR7_0
#define TKE_TOP_TIMER_TMR7_TMRSR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR7_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_RANGE                       30:30
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR7_TMRCSSR_0
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0                    MK_ADDR_CONST(0x80008)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SCR                        TMRSCR7_0
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR7_0
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_RANGE                       1:0
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR7_TMRATR_0
#define TKE_TOP_TIMER_TMR7_TMRATR_0                     MK_ADDR_CONST(0x8000c)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR7_TMRATR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR7_TMRATR_0_SCR                         TMRSCR7_0
#define TKE_TOP_TIMER_TMR7_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR7_0
#define TKE_TOP_TIMER_TMR7_TMRATR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR7_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_RANGE                        29:0
#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_WOFFSET                      0x0
#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR8_TMRCR_0
#define TKE_TOP_TIMER_TMR8_TMRCR_0                      MK_ADDR_CONST(0x90000)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR8_TMRCR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR8_TMRCR_0_SCR                  TMRSCR8_0
#define TKE_TOP_TIMER_TMR8_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR8_0
#define TKE_TOP_TIMER_TMR8_TMRCR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR8_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR8_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_RANGE                     31:31
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_WOFFSET                   0x0
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR8_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_RANGE                    30:30
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR8_TMRSR_0
#define TKE_TOP_TIMER_TMR8_TMRSR_0                      MK_ADDR_CONST(0x90004)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR8_TMRSR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR8_TMRSR_0_SCR                  TMRSCR8_0
#define TKE_TOP_TIMER_TMR8_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR8_0
#define TKE_TOP_TIMER_TMR8_TMRSR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR8_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_RANGE                       30:30
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR8_TMRCSSR_0
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0                    MK_ADDR_CONST(0x90008)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SCR                        TMRSCR8_0
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR8_0
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_RANGE                       1:0
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR8_TMRATR_0
#define TKE_TOP_TIMER_TMR8_TMRATR_0                     MK_ADDR_CONST(0x9000c)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR8_TMRATR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR8_TMRATR_0_SCR                         TMRSCR8_0
#define TKE_TOP_TIMER_TMR8_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR8_0
#define TKE_TOP_TIMER_TMR8_TMRATR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR8_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_RANGE                        29:0
#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_WOFFSET                      0x0
#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR9_TMRCR_0
#define TKE_TOP_TIMER_TMR9_TMRCR_0                      MK_ADDR_CONST(0xa0000)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR9_TMRCR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR9_TMRCR_0_SCR                  TMRSCR9_0
#define TKE_TOP_TIMER_TMR9_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR9_0
#define TKE_TOP_TIMER_TMR9_TMRCR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR9_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR9_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_RANGE                     31:31
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_WOFFSET                   0x0
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR9_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_RANGE                    30:30
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR9_TMRSR_0
#define TKE_TOP_TIMER_TMR9_TMRSR_0                      MK_ADDR_CONST(0xa0004)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_SECURE                       0x0
#define TKE_TOP_TIMER_TMR9_TMRSR_0_DUAL                         0x0
#define TKE_TOP_TIMER_TMR9_TMRSR_0_SCR                  TMRSCR9_0
#define TKE_TOP_TIMER_TMR9_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR9_0
#define TKE_TOP_TIMER_TMR9_TMRSR_0_WORD_COUNT                   0x1
#define TKE_TOP_TIMER_TMR9_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_RANGE                       30:30
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_RANGE                    28:0
#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR9_TMRCSSR_0
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0                    MK_ADDR_CONST(0xa0008)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SCR                        TMRSCR9_0
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR9_0
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_RANGE                       1:0
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR9_TMRATR_0
#define TKE_TOP_TIMER_TMR9_TMRATR_0                     MK_ADDR_CONST(0xa000c)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR9_TMRATR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR9_TMRATR_0_SCR                         TMRSCR9_0
#define TKE_TOP_TIMER_TMR9_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR9_0
#define TKE_TOP_TIMER_TMR9_TMRATR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR9_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_RANGE                        29:0
#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_WOFFSET                      0x0
#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR10_TMRCR_0
#define TKE_TOP_TIMER_TMR10_TMRCR_0                     MK_ADDR_CONST(0xb0000)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR10_TMRCR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR10_TMRCR_0_SCR                         TMRSCR10_0
#define TKE_TOP_TIMER_TMR10_TMRCR_0_SCRREG                      TKE_TOP_SCR_TMRSCR10_0
#define TKE_TOP_TIMER_TMR10_TMRCR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR10_TMRCR_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_RESET_MASK                  MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_READ_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_WRITE_MASK                  MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_SHIFT                    MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR10_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_RANGE                    31:31
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_MSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_LSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_SHIFT                   MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR10_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_RANGE                   30:30
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_MSB                     MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_LSB                     MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_DEFAULT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_DISABLE                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_ENABLE                  MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_RANGE                   28:0
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_MSB                     MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_MAX                     MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR10_TMRSR_0
#define TKE_TOP_TIMER_TMR10_TMRSR_0                     MK_ADDR_CONST(0xb0004)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR10_TMRSR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR10_TMRSR_0_SCR                         TMRSCR10_0
#define TKE_TOP_TIMER_TMR10_TMRSR_0_SCRREG                      TKE_TOP_SCR_TMRSCR10_0
#define TKE_TOP_TIMER_TMR10_TMRSR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR10_TMRSR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_RESET_MASK                  MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_READ_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_SHIFT                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_RANGE                      30:30
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_MSB                        MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_LSB                        MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_WOFFSET                    0x0
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_DISABLE                    MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_ENABLE                     MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_RANGE                   28:0
#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_MSB                     MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR10_TMRCSSR_0
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0                   MK_ADDR_CONST(0xb0008)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SECURE                    0x0
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_DUAL                      0x0
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SCR                       TMRSCR10_0
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SCRREG                    TKE_TOP_SCR_TMRSCR10_0
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_WORD_COUNT                        0x1
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_READ_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SHIFT                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_FIELD                      MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_RANGE                      1:0
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_MSB                        MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_LSB                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SRC_USECCNT                        MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR10_TMRATR_0
#define TKE_TOP_TIMER_TMR10_TMRATR_0                    MK_ADDR_CONST(0xb000c)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR10_TMRATR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR10_TMRATR_0_SCR                        TMRSCR10_0
#define TKE_TOP_TIMER_TMR10_TMRATR_0_SCRREG                     TKE_TOP_SCR_TMRSCR10_0
#define TKE_TOP_TIMER_TMR10_TMRATR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR10_TMRATR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_FIELD                       MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_RANGE                       29:0
#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_MSB                 MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_DEFAULT_MASK                        MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR11_TMRCR_0
#define TKE_TOP_TIMER_TMR11_TMRCR_0                     MK_ADDR_CONST(0xc0000)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR11_TMRCR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR11_TMRCR_0_SCR                         TMRSCR11_0
#define TKE_TOP_TIMER_TMR11_TMRCR_0_SCRREG                      TKE_TOP_SCR_TMRSCR11_0
#define TKE_TOP_TIMER_TMR11_TMRCR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR11_TMRCR_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_RESET_MASK                  MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_READ_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_WRITE_MASK                  MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_SHIFT                    MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR11_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_RANGE                    31:31
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_MSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_LSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_SHIFT                   MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR11_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_RANGE                   30:30
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_MSB                     MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_LSB                     MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_DEFAULT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_DISABLE                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_ENABLE                  MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_RANGE                   28:0
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_MSB                     MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_MAX                     MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR11_TMRSR_0
#define TKE_TOP_TIMER_TMR11_TMRSR_0                     MK_ADDR_CONST(0xc0004)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR11_TMRSR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR11_TMRSR_0_SCR                         TMRSCR11_0
#define TKE_TOP_TIMER_TMR11_TMRSR_0_SCRREG                      TKE_TOP_SCR_TMRSCR11_0
#define TKE_TOP_TIMER_TMR11_TMRSR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR11_TMRSR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_RESET_MASK                  MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_READ_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_SHIFT                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_RANGE                      30:30
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_MSB                        MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_LSB                        MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_WOFFSET                    0x0
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_DISABLE                    MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_ENABLE                     MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_RANGE                   28:0
#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_MSB                     MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR11_TMRCSSR_0
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0                   MK_ADDR_CONST(0xc0008)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SECURE                    0x0
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_DUAL                      0x0
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SCR                       TMRSCR11_0
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SCRREG                    TKE_TOP_SCR_TMRSCR11_0
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_WORD_COUNT                        0x1
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_READ_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SHIFT                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_FIELD                      MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_RANGE                      1:0
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_MSB                        MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_LSB                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SRC_USECCNT                        MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR11_TMRATR_0
#define TKE_TOP_TIMER_TMR11_TMRATR_0                    MK_ADDR_CONST(0xc000c)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR11_TMRATR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR11_TMRATR_0_SCR                        TMRSCR11_0
#define TKE_TOP_TIMER_TMR11_TMRATR_0_SCRREG                     TKE_TOP_SCR_TMRSCR11_0
#define TKE_TOP_TIMER_TMR11_TMRATR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR11_TMRATR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_FIELD                       MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_RANGE                       29:0
#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_MSB                 MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_DEFAULT_MASK                        MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR12_TMRCR_0
#define TKE_TOP_TIMER_TMR12_TMRCR_0                     MK_ADDR_CONST(0xd0000)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR12_TMRCR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR12_TMRCR_0_SCR                         TMRSCR12_0
#define TKE_TOP_TIMER_TMR12_TMRCR_0_SCRREG                      TKE_TOP_SCR_TMRSCR12_0
#define TKE_TOP_TIMER_TMR12_TMRCR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR12_TMRCR_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_RESET_MASK                  MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_READ_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_WRITE_MASK                  MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_SHIFT                    MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR12_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_RANGE                    31:31
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_MSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_LSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_SHIFT                   MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR12_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_RANGE                   30:30
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_MSB                     MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_LSB                     MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_DEFAULT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_DISABLE                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_ENABLE                  MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_RANGE                   28:0
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_MSB                     MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_MAX                     MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR12_TMRSR_0
#define TKE_TOP_TIMER_TMR12_TMRSR_0                     MK_ADDR_CONST(0xd0004)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR12_TMRSR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR12_TMRSR_0_SCR                         TMRSCR12_0
#define TKE_TOP_TIMER_TMR12_TMRSR_0_SCRREG                      TKE_TOP_SCR_TMRSCR12_0
#define TKE_TOP_TIMER_TMR12_TMRSR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR12_TMRSR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_RESET_MASK                  MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_READ_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_SHIFT                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_RANGE                      30:30
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_MSB                        MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_LSB                        MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_WOFFSET                    0x0
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_DISABLE                    MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_ENABLE                     MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_RANGE                   28:0
#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_MSB                     MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR12_TMRCSSR_0
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0                   MK_ADDR_CONST(0xd0008)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SECURE                    0x0
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_DUAL                      0x0
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SCR                       TMRSCR12_0
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SCRREG                    TKE_TOP_SCR_TMRSCR12_0
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_WORD_COUNT                        0x1
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_READ_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SHIFT                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_FIELD                      MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_RANGE                      1:0
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_MSB                        MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_LSB                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SRC_USECCNT                        MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR12_TMRATR_0
#define TKE_TOP_TIMER_TMR12_TMRATR_0                    MK_ADDR_CONST(0xd000c)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR12_TMRATR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR12_TMRATR_0_SCR                        TMRSCR12_0
#define TKE_TOP_TIMER_TMR12_TMRATR_0_SCRREG                     TKE_TOP_SCR_TMRSCR12_0
#define TKE_TOP_TIMER_TMR12_TMRATR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR12_TMRATR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_FIELD                       MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_RANGE                       29:0
#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_MSB                 MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_DEFAULT_MASK                        MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR13_TMRCR_0
#define TKE_TOP_TIMER_TMR13_TMRCR_0                     MK_ADDR_CONST(0xe0000)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR13_TMRCR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR13_TMRCR_0_SCR                         TMRSCR13_0
#define TKE_TOP_TIMER_TMR13_TMRCR_0_SCRREG                      TKE_TOP_SCR_TMRSCR13_0
#define TKE_TOP_TIMER_TMR13_TMRCR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR13_TMRCR_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_RESET_MASK                  MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_READ_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_WRITE_MASK                  MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_SHIFT                    MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR13_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_RANGE                    31:31
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_MSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_LSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_SHIFT                   MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR13_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_RANGE                   30:30
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_MSB                     MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_LSB                     MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_DEFAULT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_DISABLE                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_ENABLE                  MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_RANGE                   28:0
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_MSB                     MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_MAX                     MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR13_TMRSR_0
#define TKE_TOP_TIMER_TMR13_TMRSR_0                     MK_ADDR_CONST(0xe0004)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR13_TMRSR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR13_TMRSR_0_SCR                         TMRSCR13_0
#define TKE_TOP_TIMER_TMR13_TMRSR_0_SCRREG                      TKE_TOP_SCR_TMRSCR13_0
#define TKE_TOP_TIMER_TMR13_TMRSR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR13_TMRSR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_RESET_MASK                  MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_READ_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_SHIFT                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_RANGE                      30:30
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_MSB                        MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_LSB                        MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_WOFFSET                    0x0
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_DISABLE                    MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_ENABLE                     MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_RANGE                   28:0
#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_MSB                     MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR13_TMRCSSR_0
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0                   MK_ADDR_CONST(0xe0008)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SECURE                    0x0
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_DUAL                      0x0
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SCR                       TMRSCR13_0
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SCRREG                    TKE_TOP_SCR_TMRSCR13_0
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_WORD_COUNT                        0x1
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_READ_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SHIFT                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_FIELD                      MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_RANGE                      1:0
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_MSB                        MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_LSB                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SRC_USECCNT                        MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR13_TMRATR_0
#define TKE_TOP_TIMER_TMR13_TMRATR_0                    MK_ADDR_CONST(0xe000c)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR13_TMRATR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR13_TMRATR_0_SCR                        TMRSCR13_0
#define TKE_TOP_TIMER_TMR13_TMRATR_0_SCRREG                     TKE_TOP_SCR_TMRSCR13_0
#define TKE_TOP_TIMER_TMR13_TMRATR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR13_TMRATR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_FIELD                       MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_RANGE                       29:0
#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_MSB                 MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_DEFAULT_MASK                        MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR14_TMRCR_0
#define TKE_TOP_TIMER_TMR14_TMRCR_0                     MK_ADDR_CONST(0xf0000)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR14_TMRCR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR14_TMRCR_0_SCR                         TMRSCR14_0
#define TKE_TOP_TIMER_TMR14_TMRCR_0_SCRREG                      TKE_TOP_SCR_TMRSCR14_0
#define TKE_TOP_TIMER_TMR14_TMRCR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR14_TMRCR_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_RESET_MASK                  MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_READ_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_WRITE_MASK                  MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_SHIFT                    MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR14_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_RANGE                    31:31
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_MSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_LSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_SHIFT                   MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR14_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_RANGE                   30:30
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_MSB                     MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_LSB                     MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_DEFAULT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_DISABLE                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_ENABLE                  MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_RANGE                   28:0
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_MSB                     MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_MAX                     MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR14_TMRSR_0
#define TKE_TOP_TIMER_TMR14_TMRSR_0                     MK_ADDR_CONST(0xf0004)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR14_TMRSR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR14_TMRSR_0_SCR                         TMRSCR14_0
#define TKE_TOP_TIMER_TMR14_TMRSR_0_SCRREG                      TKE_TOP_SCR_TMRSCR14_0
#define TKE_TOP_TIMER_TMR14_TMRSR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR14_TMRSR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_RESET_MASK                  MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_READ_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_SHIFT                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_RANGE                      30:30
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_MSB                        MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_LSB                        MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_WOFFSET                    0x0
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_DISABLE                    MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_ENABLE                     MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_RANGE                   28:0
#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_MSB                     MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR14_TMRCSSR_0
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0                   MK_ADDR_CONST(0xf0008)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SECURE                    0x0
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_DUAL                      0x0
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SCR                       TMRSCR14_0
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SCRREG                    TKE_TOP_SCR_TMRSCR14_0
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_WORD_COUNT                        0x1
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_READ_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SHIFT                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_FIELD                      MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_RANGE                      1:0
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_MSB                        MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_LSB                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SRC_USECCNT                        MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR14_TMRATR_0
#define TKE_TOP_TIMER_TMR14_TMRATR_0                    MK_ADDR_CONST(0xf000c)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR14_TMRATR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR14_TMRATR_0_SCR                        TMRSCR14_0
#define TKE_TOP_TIMER_TMR14_TMRATR_0_SCRREG                     TKE_TOP_SCR_TMRSCR14_0
#define TKE_TOP_TIMER_TMR14_TMRATR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR14_TMRATR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_FIELD                       MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_RANGE                       29:0
#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_MSB                 MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_DEFAULT_MASK                        MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR15_TMRCR_0
#define TKE_TOP_TIMER_TMR15_TMRCR_0                     MK_ADDR_CONST(0x100000)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR15_TMRCR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR15_TMRCR_0_SCR                         TMRSCR15_0
#define TKE_TOP_TIMER_TMR15_TMRCR_0_SCRREG                      TKE_TOP_SCR_TMRSCR15_0
#define TKE_TOP_TIMER_TMR15_TMRCR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR15_TMRCR_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_RESET_MASK                  MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_READ_MASK                   MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_WRITE_MASK                  MK_MASK_CONST(0xdfffffff)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_SHIFT                    MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR15_TMRCR_0_EN_SHIFT)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_RANGE                    31:31
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_MSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_LSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_WOFFSET                  0x0
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_DISABLE                  MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_ENABLE                   MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_SHIFT                   MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR15_TMRCR_0_PER_SHIFT)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_RANGE                   30:30
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_MSB                     MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_LSB                     MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_DEFAULT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_DISABLE                 MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_ENABLE                  MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_SHIFT)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_RANGE                   28:0
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_MSB                     MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_MAX                     MK_ENUM_CONST(536870911)


// Register TKE_TOP_TIMER_TMR15_TMRSR_0
#define TKE_TOP_TIMER_TMR15_TMRSR_0                     MK_ADDR_CONST(0x100004)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_SECURE                      0x0
#define TKE_TOP_TIMER_TMR15_TMRSR_0_DUAL                        0x0
#define TKE_TOP_TIMER_TMR15_TMRSR_0_SCR                         TMRSCR15_0
#define TKE_TOP_TIMER_TMR15_TMRSR_0_SCRREG                      TKE_TOP_SCR_TMRSCR15_0
#define TKE_TOP_TIMER_TMR15_TMRSR_0_WORD_COUNT                  0x1
#define TKE_TOP_TIMER_TMR15_TMRSR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_RESET_MASK                  MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_READ_MASK                   MK_MASK_CONST(0x5fffffff)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_SHIFT                      MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_RANGE                      30:30
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_MSB                        MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_LSB                        MK_SHIFT_CONST(30)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_WOFFSET                    0x0
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_DISABLE                    MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_ENABLE                     MK_ENUM_CONST(1)

#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_SHIFT                   MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_SHIFT)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_RANGE                   28:0
#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_MSB                     MK_SHIFT_CONST(28)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_LSB                     MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_WOFFSET                 0x0
#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register TKE_TOP_TIMER_TMR15_TMRCSSR_0
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0                   MK_ADDR_CONST(0x100008)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SECURE                    0x0
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_DUAL                      0x0
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SCR                       TMRSCR15_0
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SCRREG                    TKE_TOP_SCR_TMRSCR15_0
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_WORD_COUNT                        0x1
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_READ_MASK                         MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SHIFT                      MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_FIELD                      MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_RANGE                      1:0
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_MSB                        MK_SHIFT_CONST(1)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_LSB                        MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SRC_USECCNT                        MK_ENUM_CONST(0)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 MK_ENUM_CONST(1)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    MK_ENUM_CONST(2)
#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   MK_ENUM_CONST(3)


// Register TKE_TOP_TIMER_TMR15_TMRATR_0
#define TKE_TOP_TIMER_TMR15_TMRATR_0                    MK_ADDR_CONST(0x10000c)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_SECURE                     0x0
#define TKE_TOP_TIMER_TMR15_TMRATR_0_DUAL                       0x0
#define TKE_TOP_TIMER_TMR15_TMRATR_0_SCR                        TMRSCR15_0
#define TKE_TOP_TIMER_TMR15_TMRATR_0_SCRREG                     TKE_TOP_SCR_TMRSCR15_0
#define TKE_TOP_TIMER_TMR15_TMRATR_0_WORD_COUNT                         0x1
#define TKE_TOP_TIMER_TMR15_TMRATR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_FIELD                       MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_SHIFT)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_RANGE                       29:0
#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_MSB                 MK_SHIFT_CONST(29)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_WOFFSET                     0x0
#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_DEFAULT_MASK                        MK_MASK_CONST(0x3fffffff)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT0_WDTCR_0
#define TKE_TOP_WDT0_WDTCR_0                    MK_ADDR_CONST(0x110000)
#define TKE_TOP_WDT0_WDTCR_0_SECURE                     0x0
#define TKE_TOP_WDT0_WDTCR_0_DUAL                       0x0
#define TKE_TOP_WDT0_WDTCR_0_SCR                        WDTSCR0_0
#define TKE_TOP_WDT0_WDTCR_0_SCRREG                     TKE_TOP_SCR_WDTSCR0_0
#define TKE_TOP_WDT0_WDTCR_0_WORD_COUNT                         0x1
#define TKE_TOP_WDT0_WDTCR_0_RESET_VAL                  MK_MASK_CONST(0x700000)
#define TKE_TOP_WDT0_WDTCR_0_RESET_MASK                         MK_MASK_CONST(0xf3ffffff)
#define TKE_TOP_WDT0_WDTCR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_READ_MASK                  MK_MASK_CONST(0xf3ffffff)
#define TKE_TOP_WDT0_WDTCR_0_WRITE_MASK                         MK_MASK_CONST(0xf3ffffff)
#define TKE_TOP_WDT0_WDTCR_0_TimerSource_SHIFT                  MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTCR_0_TimerSource_FIELD                  MK_FIELD_CONST(0xf, TKE_TOP_WDT0_WDTCR_0_TimerSource_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_TimerSource_RANGE                  3:0
#define TKE_TOP_WDT0_WDTCR_0_TimerSource_MSB                    MK_SHIFT_CONST(3)
#define TKE_TOP_WDT0_WDTCR_0_TimerSource_LSB                    MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTCR_0_TimerSource_WOFFSET                        0x0
#define TKE_TOP_WDT0_WDTCR_0_TimerSource_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_TimerSource_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define TKE_TOP_WDT0_WDTCR_0_TimerSource_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_TimerSource_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_TimerSource_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_TimerSource_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_TimerSource_TMR0                   MK_ENUM_CONST(0)

#define TKE_TOP_WDT0_WDTCR_0_Period_SHIFT                       MK_SHIFT_CONST(4)
#define TKE_TOP_WDT0_WDTCR_0_Period_FIELD                       MK_FIELD_CONST(0xff, TKE_TOP_WDT0_WDTCR_0_Period_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_Period_RANGE                       11:4
#define TKE_TOP_WDT0_WDTCR_0_Period_MSB                 MK_SHIFT_CONST(11)
#define TKE_TOP_WDT0_WDTCR_0_Period_LSB                 MK_SHIFT_CONST(4)
#define TKE_TOP_WDT0_WDTCR_0_Period_WOFFSET                     0x0
#define TKE_TOP_WDT0_WDTCR_0_Period_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_Period_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define TKE_TOP_WDT0_WDTCR_0_Period_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_Period_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_Period_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_Period_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_SHIFT                 MK_SHIFT_CONST(12)
#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_RANGE                 12:12
#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_MSB                   MK_SHIFT_CONST(12)
#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_LSB                   MK_SHIFT_CONST(12)
#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_WOFFSET                       0x0
#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_SHIFT                       MK_SHIFT_CONST(13)
#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_RANGE                       13:13
#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_MSB                 MK_SHIFT_CONST(13)
#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_LSB                 MK_SHIFT_CONST(13)
#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_WOFFSET                     0x0
#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_SHIFT                        MK_SHIFT_CONST(14)
#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_RANGE                        14:14
#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_MSB                  MK_SHIFT_CONST(14)
#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_LSB                  MK_SHIFT_CONST(14)
#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_WOFFSET                      0x0
#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_SHIFT                       MK_SHIFT_CONST(15)
#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_RANGE                       15:15
#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_MSB                 MK_SHIFT_CONST(15)
#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_LSB                 MK_SHIFT_CONST(15)
#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_WOFFSET                     0x0
#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_SHIFT                  MK_SHIFT_CONST(16)
#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_FIELD                  MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_RANGE                  16:16
#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_MSB                    MK_SHIFT_CONST(16)
#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_LSB                    MK_SHIFT_CONST(16)
#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_WOFFSET                        0x0
#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_DISABLE                        MK_ENUM_CONST(0)
#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_ENABLE                 MK_ENUM_CONST(1)

#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_SHIFT                      MK_SHIFT_CONST(17)
#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_RANGE                      17:17
#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_MSB                        MK_SHIFT_CONST(17)
#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_LSB                        MK_SHIFT_CONST(17)
#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_WOFFSET                    0x0
#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_SHIFT                      MK_SHIFT_CONST(18)
#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_RANGE                      18:18
#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_MSB                        MK_SHIFT_CONST(18)
#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_LSB                        MK_SHIFT_CONST(18)
#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_WOFFSET                    0x0
#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_SHIFT                   MK_SHIFT_CONST(19)
#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_RANGE                   19:19
#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_MSB                     MK_SHIFT_CONST(19)
#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_LSB                     MK_SHIFT_CONST(19)
#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_WOFFSET                 0x0
#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_SHIFT                       MK_SHIFT_CONST(20)
#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_RANGE                       22:20
#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_MSB                 MK_SHIFT_CONST(22)
#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_LSB                 MK_SHIFT_CONST(20)
#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_WOFFSET                     0x0
#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_DEFAULT                     MK_MASK_CONST(0x7)
#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_SHIFT                   MK_SHIFT_CONST(23)
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_FIELD                   MK_FIELD_CONST(0x3, TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_RANGE                   24:23
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_MSB                     MK_SHIFT_CONST(24)
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_LSB                     MK_SHIFT_CONST(23)
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_WOFFSET                 0x0
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_NOP                     MK_ENUM_CONST(0)
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_JUMP_TO_4                       MK_ENUM_CONST(1)
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_JUMP_TO_5                       MK_ENUM_CONST(2)
#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_POR_RESET                       MK_ENUM_CONST(3)

#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_SHIFT                    MK_SHIFT_CONST(25)
#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_RANGE                    25:25
#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_MSB                      MK_SHIFT_CONST(25)
#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_LSB                      MK_SHIFT_CONST(25)
#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_WOFFSET                  0x0
#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_SHIFT                    MK_SHIFT_CONST(28)
#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_FIELD                    MK_FIELD_CONST(0xf, TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_SHIFT)
#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_RANGE                    31:28
#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_MSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_LSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_WOFFSET                  0x0
#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT0_WDTSR_0
#define TKE_TOP_WDT0_WDTSR_0                    MK_ADDR_CONST(0x110004)
#define TKE_TOP_WDT0_WDTSR_0_SECURE                     0x0
#define TKE_TOP_WDT0_WDTSR_0_DUAL                       0x0
#define TKE_TOP_WDT0_WDTSR_0_SCR                        WDTSCR0_0
#define TKE_TOP_WDT0_WDTSR_0_SCRREG                     TKE_TOP_SCR_WDTSCR0_0
#define TKE_TOP_WDT0_WDTSR_0_WORD_COUNT                         0x1
#define TKE_TOP_WDT0_WDTSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_RESET_MASK                         MK_MASK_CONST(0xf7fff)
#define TKE_TOP_WDT0_WDTSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_READ_MASK                  MK_MASK_CONST(0xf7fff)
#define TKE_TOP_WDT0_WDTSR_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_Enabled_SHIFT                      MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTSR_0_Enabled_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_Enabled_SHIFT)
#define TKE_TOP_WDT0_WDTSR_0_Enabled_RANGE                      0:0
#define TKE_TOP_WDT0_WDTSR_0_Enabled_MSB                        MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTSR_0_Enabled_LSB                        MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTSR_0_Enabled_WOFFSET                    0x0
#define TKE_TOP_WDT0_WDTSR_0_Enabled_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_Enabled_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSR_0_Enabled_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_Enabled_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_Enabled_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_Enabled_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSR_0_Enabled_DISABLE                    MK_ENUM_CONST(0)
#define TKE_TOP_WDT0_WDTSR_0_Enabled_ENABLE                     MK_ENUM_CONST(1)

#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_SHIFT                 MK_SHIFT_CONST(1)
#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_SHIFT)
#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_RANGE                 1:1
#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_MSB                   MK_SHIFT_CONST(1)
#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_LSB                   MK_SHIFT_CONST(1)
#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_WOFFSET                       0x0
#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_SHIFT                       MK_SHIFT_CONST(2)
#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_SHIFT)
#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_RANGE                       2:2
#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_MSB                 MK_SHIFT_CONST(2)
#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_LSB                 MK_SHIFT_CONST(2)
#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_WOFFSET                     0x0
#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_SHIFT                        MK_SHIFT_CONST(3)
#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_SHIFT)
#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_RANGE                        3:3
#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_MSB                  MK_SHIFT_CONST(3)
#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_LSB                  MK_SHIFT_CONST(3)
#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_WOFFSET                      0x0
#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_SHIFT                 MK_SHIFT_CONST(4)
#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_FIELD                 MK_FIELD_CONST(0xff, TKE_TOP_WDT0_WDTSR_0_CurrentCount_SHIFT)
#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_RANGE                 11:4
#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_MSB                   MK_SHIFT_CONST(11)
#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_LSB                   MK_SHIFT_CONST(4)
#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_WOFFSET                       0x0
#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_SHIFT                       MK_SHIFT_CONST(12)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_SHIFT)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_RANGE                       14:12
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_MSB                 MK_SHIFT_CONST(14)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_LSB                 MK_SHIFT_CONST(12)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_WOFFSET                     0x0
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_NO_EXPIRY                   MK_ENUM_CONST(0)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_LOCAL_IRQ                   MK_ENUM_CONST(1)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_LOCAL_FIQ                   MK_ENUM_CONST(2)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_REMOTE_IRQ                  MK_ENUM_CONST(3)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_DEBUG_RESET                 MK_ENUM_CONST(4)
#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_SYSTEM_RESET                        MK_ENUM_CONST(5)

#define TKE_TOP_WDT0_WDTSR_0_CurrentError_SHIFT                 MK_SHIFT_CONST(16)
#define TKE_TOP_WDT0_WDTSR_0_CurrentError_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_CurrentError_SHIFT)
#define TKE_TOP_WDT0_WDTSR_0_CurrentError_RANGE                 16:16
#define TKE_TOP_WDT0_WDTSR_0_CurrentError_MSB                   MK_SHIFT_CONST(16)
#define TKE_TOP_WDT0_WDTSR_0_CurrentError_LSB                   MK_SHIFT_CONST(16)
#define TKE_TOP_WDT0_WDTSR_0_CurrentError_WOFFSET                       0x0
#define TKE_TOP_WDT0_WDTSR_0_CurrentError_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_CurrentError_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSR_0_CurrentError_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_CurrentError_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_CurrentError_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_CurrentError_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_SHIFT                        MK_SHIFT_CONST(17)
#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_StickyEnabled_SHIFT)
#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_RANGE                        17:17
#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_MSB                  MK_SHIFT_CONST(17)
#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_LSB                  MK_SHIFT_CONST(17)
#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_WOFFSET                      0x0
#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_SHIFT                  MK_SHIFT_CONST(18)
#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_FIELD                  MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_ErrorForced_SHIFT)
#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_RANGE                  18:18
#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_MSB                    MK_SHIFT_CONST(18)
#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_LSB                    MK_SHIFT_CONST(18)
#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_WOFFSET                        0x0
#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTSR_0_Frozen_SHIFT                       MK_SHIFT_CONST(19)
#define TKE_TOP_WDT0_WDTSR_0_Frozen_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_Frozen_SHIFT)
#define TKE_TOP_WDT0_WDTSR_0_Frozen_RANGE                       19:19
#define TKE_TOP_WDT0_WDTSR_0_Frozen_MSB                 MK_SHIFT_CONST(19)
#define TKE_TOP_WDT0_WDTSR_0_Frozen_LSB                 MK_SHIFT_CONST(19)
#define TKE_TOP_WDT0_WDTSR_0_Frozen_WOFFSET                     0x0
#define TKE_TOP_WDT0_WDTSR_0_Frozen_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_Frozen_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSR_0_Frozen_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_Frozen_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_Frozen_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSR_0_Frozen_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT0_WDTCMDR_0
#define TKE_TOP_WDT0_WDTCMDR_0                  MK_ADDR_CONST(0x110008)
#define TKE_TOP_WDT0_WDTCMDR_0_SECURE                   0x0
#define TKE_TOP_WDT0_WDTCMDR_0_DUAL                     0x0
#define TKE_TOP_WDT0_WDTCMDR_0_SCR                      WDTSCR0_0
#define TKE_TOP_WDT0_WDTCMDR_0_SCRREG                   TKE_TOP_SCR_WDTSCR0_0
#define TKE_TOP_WDT0_WDTCMDR_0_WORD_COUNT                       0x1
#define TKE_TOP_WDT0_WDTCMDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_RESET_MASK                       MK_MASK_CONST(0xf)
#define TKE_TOP_WDT0_WDTCMDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_READ_MASK                        MK_MASK_CONST(0xf)
#define TKE_TOP_WDT0_WDTCMDR_0_WRITE_MASK                       MK_MASK_CONST(0xf)
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCMDR_0_StartCounter_SHIFT)
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_RANGE                       0:0
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_MSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_WOFFSET                     0x0
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_DISABLE                     MK_ENUM_CONST(0)
#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_ENABLE                      MK_ENUM_CONST(1)

#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_SHIFT                     MK_SHIFT_CONST(1)
#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_SHIFT)
#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_RANGE                     1:1
#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_MSB                       MK_SHIFT_CONST(1)
#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_LSB                       MK_SHIFT_CONST(1)
#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_WOFFSET                   0x0
#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_DISABLE                   MK_ENUM_CONST(0)
#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_ENABLE                    MK_ENUM_CONST(1)

#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_SHIFT                        MK_SHIFT_CONST(2)
#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCMDR_0_StickyStart_SHIFT)
#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_RANGE                        2:2
#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_MSB                  MK_SHIFT_CONST(2)
#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_LSB                  MK_SHIFT_CONST(2)
#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_WOFFSET                      0x0
#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_SHIFT                 MK_SHIFT_CONST(3)
#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCMDR_0_ForceError_SHIFT)
#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_RANGE                 3:3
#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_MSB                   MK_SHIFT_CONST(3)
#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_LSB                   MK_SHIFT_CONST(3)
#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_WOFFSET                       0x0
#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT0_WDTUR_0
#define TKE_TOP_WDT0_WDTUR_0                    MK_ADDR_CONST(0x11000c)
#define TKE_TOP_WDT0_WDTUR_0_SECURE                     0x0
#define TKE_TOP_WDT0_WDTUR_0_DUAL                       0x0
#define TKE_TOP_WDT0_WDTUR_0_SCR                        WDTSCR0_0
#define TKE_TOP_WDT0_WDTUR_0_SCRREG                     TKE_TOP_SCR_WDTSCR0_0
#define TKE_TOP_WDT0_WDTUR_0_WORD_COUNT                         0x1
#define TKE_TOP_WDT0_WDTUR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTUR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define TKE_TOP_WDT0_WDTUR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTUR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTUR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define TKE_TOP_WDT0_WDTUR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_WDT0_WDTUR_0_UnlockPattern_SHIFT)
#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_RANGE                        31:0
#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_MSB                  MK_SHIFT_CONST(31)
#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_WOFFSET                      0x0
#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_UNLOCK                       MK_ENUM_CONST(50266)


// Register TKE_TOP_WDT0_WDTSCR_0
#define TKE_TOP_WDT0_WDTSCR_0                   MK_ADDR_CONST(0x110010)
#define TKE_TOP_WDT0_WDTSCR_0_SECURE                    0x0
#define TKE_TOP_WDT0_WDTSCR_0_DUAL                      0x0
#define TKE_TOP_WDT0_WDTSCR_0_SCR                       WDTSCR0_0
#define TKE_TOP_WDT0_WDTSCR_0_SCRREG                    TKE_TOP_SCR_WDTSCR0_0
#define TKE_TOP_WDT0_WDTSCR_0_WORD_COUNT                        0x1
#define TKE_TOP_WDT0_WDTSCR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_RESET_MASK                        MK_MASK_CONST(0x7777)
#define TKE_TOP_WDT0_WDTSCR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_READ_MASK                         MK_MASK_CONST(0x7777)
#define TKE_TOP_WDT0_WDTSCR_0_WRITE_MASK                        MK_MASK_CONST(0x7777)
#define TKE_TOP_WDT0_WDTSCR_0_Skip0_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip0_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTSCR_0_Skip0_SHIFT)
#define TKE_TOP_WDT0_WDTSCR_0_Skip0_RANGE                       2:0
#define TKE_TOP_WDT0_WDTSCR_0_Skip0_MSB                 MK_SHIFT_CONST(2)
#define TKE_TOP_WDT0_WDTSCR_0_Skip0_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip0_WOFFSET                     0x0
#define TKE_TOP_WDT0_WDTSCR_0_Skip0_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip0_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT0_WDTSCR_0_Skip0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSCR_0_Skip0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTSCR_0_Skip1_SHIFT                       MK_SHIFT_CONST(4)
#define TKE_TOP_WDT0_WDTSCR_0_Skip1_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTSCR_0_Skip1_SHIFT)
#define TKE_TOP_WDT0_WDTSCR_0_Skip1_RANGE                       6:4
#define TKE_TOP_WDT0_WDTSCR_0_Skip1_MSB                 MK_SHIFT_CONST(6)
#define TKE_TOP_WDT0_WDTSCR_0_Skip1_LSB                 MK_SHIFT_CONST(4)
#define TKE_TOP_WDT0_WDTSCR_0_Skip1_WOFFSET                     0x0
#define TKE_TOP_WDT0_WDTSCR_0_Skip1_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip1_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT0_WDTSCR_0_Skip1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSCR_0_Skip1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTSCR_0_Skip2_SHIFT                       MK_SHIFT_CONST(8)
#define TKE_TOP_WDT0_WDTSCR_0_Skip2_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTSCR_0_Skip2_SHIFT)
#define TKE_TOP_WDT0_WDTSCR_0_Skip2_RANGE                       10:8
#define TKE_TOP_WDT0_WDTSCR_0_Skip2_MSB                 MK_SHIFT_CONST(10)
#define TKE_TOP_WDT0_WDTSCR_0_Skip2_LSB                 MK_SHIFT_CONST(8)
#define TKE_TOP_WDT0_WDTSCR_0_Skip2_WOFFSET                     0x0
#define TKE_TOP_WDT0_WDTSCR_0_Skip2_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip2_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT0_WDTSCR_0_Skip2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSCR_0_Skip2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTSCR_0_Skip3_SHIFT                       MK_SHIFT_CONST(12)
#define TKE_TOP_WDT0_WDTSCR_0_Skip3_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTSCR_0_Skip3_SHIFT)
#define TKE_TOP_WDT0_WDTSCR_0_Skip3_RANGE                       14:12
#define TKE_TOP_WDT0_WDTSCR_0_Skip3_MSB                 MK_SHIFT_CONST(14)
#define TKE_TOP_WDT0_WDTSCR_0_Skip3_LSB                 MK_SHIFT_CONST(12)
#define TKE_TOP_WDT0_WDTSCR_0_Skip3_WOFFSET                     0x0
#define TKE_TOP_WDT0_WDTSCR_0_Skip3_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip3_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT0_WDTSCR_0_Skip3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTSCR_0_Skip3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTSCR_0_Skip3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT0_WDTFWCR_0
#define TKE_TOP_WDT0_WDTFWCR_0                  MK_ADDR_CONST(0x110014)
#define TKE_TOP_WDT0_WDTFWCR_0_SECURE                   0x0
#define TKE_TOP_WDT0_WDTFWCR_0_DUAL                     0x0
#define TKE_TOP_WDT0_WDTFWCR_0_SCR                      WDTSCR0_0
#define TKE_TOP_WDT0_WDTFWCR_0_SCRREG                   TKE_TOP_SCR_WDTSCR0_0
#define TKE_TOP_WDT0_WDTFWCR_0_WORD_COUNT                       0x1
#define TKE_TOP_WDT0_WDTFWCR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTFWCR_0_RESET_MASK                       MK_MASK_CONST(0x700ff)
#define TKE_TOP_WDT0_WDTFWCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTFWCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTFWCR_0_READ_MASK                        MK_MASK_CONST(0x700ff)
#define TKE_TOP_WDT0_WDTFWCR_0_WRITE_MASK                       MK_MASK_CONST(0x700ff)
#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_SHIFT                 MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_FIELD                 MK_FIELD_CONST(0xff, TKE_TOP_WDT0_WDTFWCR_0_StartCount_SHIFT)
#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_RANGE                 7:0
#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_MSB                   MK_SHIFT_CONST(7)
#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_LSB                   MK_SHIFT_CONST(0)
#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_WOFFSET                       0x0
#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_SHIFT                 MK_SHIFT_CONST(16)
#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_FIELD                 MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTFWCR_0_StartLevel_SHIFT)
#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_RANGE                 18:16
#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_MSB                   MK_SHIFT_CONST(18)
#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_LSB                   MK_SHIFT_CONST(16)
#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_WOFFSET                       0x0
#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT1_WDTCR_0
#define TKE_TOP_WDT1_WDTCR_0                    MK_ADDR_CONST(0x120000)
#define TKE_TOP_WDT1_WDTCR_0_SECURE                     0x0
#define TKE_TOP_WDT1_WDTCR_0_DUAL                       0x0
#define TKE_TOP_WDT1_WDTCR_0_SCR                        WDTSCR1_0
#define TKE_TOP_WDT1_WDTCR_0_SCRREG                     TKE_TOP_SCR_WDTSCR1_0
#define TKE_TOP_WDT1_WDTCR_0_WORD_COUNT                         0x1
#define TKE_TOP_WDT1_WDTCR_0_RESET_VAL                  MK_MASK_CONST(0x700000)
#define TKE_TOP_WDT1_WDTCR_0_RESET_MASK                         MK_MASK_CONST(0xf3ffffff)
#define TKE_TOP_WDT1_WDTCR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_READ_MASK                  MK_MASK_CONST(0xf3ffffff)
#define TKE_TOP_WDT1_WDTCR_0_WRITE_MASK                         MK_MASK_CONST(0xf3ffffff)
#define TKE_TOP_WDT1_WDTCR_0_TimerSource_SHIFT                  MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTCR_0_TimerSource_FIELD                  MK_FIELD_CONST(0xf, TKE_TOP_WDT1_WDTCR_0_TimerSource_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_TimerSource_RANGE                  3:0
#define TKE_TOP_WDT1_WDTCR_0_TimerSource_MSB                    MK_SHIFT_CONST(3)
#define TKE_TOP_WDT1_WDTCR_0_TimerSource_LSB                    MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTCR_0_TimerSource_WOFFSET                        0x0
#define TKE_TOP_WDT1_WDTCR_0_TimerSource_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_TimerSource_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define TKE_TOP_WDT1_WDTCR_0_TimerSource_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_TimerSource_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_TimerSource_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_TimerSource_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_TimerSource_TMR0                   MK_ENUM_CONST(0)

#define TKE_TOP_WDT1_WDTCR_0_Period_SHIFT                       MK_SHIFT_CONST(4)
#define TKE_TOP_WDT1_WDTCR_0_Period_FIELD                       MK_FIELD_CONST(0xff, TKE_TOP_WDT1_WDTCR_0_Period_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_Period_RANGE                       11:4
#define TKE_TOP_WDT1_WDTCR_0_Period_MSB                 MK_SHIFT_CONST(11)
#define TKE_TOP_WDT1_WDTCR_0_Period_LSB                 MK_SHIFT_CONST(4)
#define TKE_TOP_WDT1_WDTCR_0_Period_WOFFSET                     0x0
#define TKE_TOP_WDT1_WDTCR_0_Period_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_Period_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define TKE_TOP_WDT1_WDTCR_0_Period_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_Period_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_Period_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_Period_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_SHIFT                 MK_SHIFT_CONST(12)
#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_RANGE                 12:12
#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_MSB                   MK_SHIFT_CONST(12)
#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_LSB                   MK_SHIFT_CONST(12)
#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_WOFFSET                       0x0
#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_SHIFT                       MK_SHIFT_CONST(13)
#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_RANGE                       13:13
#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_MSB                 MK_SHIFT_CONST(13)
#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_LSB                 MK_SHIFT_CONST(13)
#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_WOFFSET                     0x0
#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_SHIFT                        MK_SHIFT_CONST(14)
#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_RANGE                        14:14
#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_MSB                  MK_SHIFT_CONST(14)
#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_LSB                  MK_SHIFT_CONST(14)
#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_WOFFSET                      0x0
#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_SHIFT                       MK_SHIFT_CONST(15)
#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_RANGE                       15:15
#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_MSB                 MK_SHIFT_CONST(15)
#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_LSB                 MK_SHIFT_CONST(15)
#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_WOFFSET                     0x0
#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_SHIFT                  MK_SHIFT_CONST(16)
#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_FIELD                  MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_RANGE                  16:16
#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_MSB                    MK_SHIFT_CONST(16)
#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_LSB                    MK_SHIFT_CONST(16)
#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_WOFFSET                        0x0
#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_DISABLE                        MK_ENUM_CONST(0)
#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_ENABLE                 MK_ENUM_CONST(1)

#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_SHIFT                      MK_SHIFT_CONST(17)
#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_RANGE                      17:17
#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_MSB                        MK_SHIFT_CONST(17)
#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_LSB                        MK_SHIFT_CONST(17)
#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_WOFFSET                    0x0
#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_SHIFT                      MK_SHIFT_CONST(18)
#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_RANGE                      18:18
#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_MSB                        MK_SHIFT_CONST(18)
#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_LSB                        MK_SHIFT_CONST(18)
#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_WOFFSET                    0x0
#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_SHIFT                   MK_SHIFT_CONST(19)
#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_RANGE                   19:19
#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_MSB                     MK_SHIFT_CONST(19)
#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_LSB                     MK_SHIFT_CONST(19)
#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_WOFFSET                 0x0
#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_SHIFT                       MK_SHIFT_CONST(20)
#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_RANGE                       22:20
#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_MSB                 MK_SHIFT_CONST(22)
#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_LSB                 MK_SHIFT_CONST(20)
#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_WOFFSET                     0x0
#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_DEFAULT                     MK_MASK_CONST(0x7)
#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_SHIFT                   MK_SHIFT_CONST(23)
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_FIELD                   MK_FIELD_CONST(0x3, TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_RANGE                   24:23
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_MSB                     MK_SHIFT_CONST(24)
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_LSB                     MK_SHIFT_CONST(23)
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_WOFFSET                 0x0
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_NOP                     MK_ENUM_CONST(0)
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_JUMP_TO_4                       MK_ENUM_CONST(1)
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_JUMP_TO_5                       MK_ENUM_CONST(2)
#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_POR_RESET                       MK_ENUM_CONST(3)

#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_SHIFT                    MK_SHIFT_CONST(25)
#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_RANGE                    25:25
#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_MSB                      MK_SHIFT_CONST(25)
#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_LSB                      MK_SHIFT_CONST(25)
#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_WOFFSET                  0x0
#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_SHIFT                    MK_SHIFT_CONST(28)
#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_FIELD                    MK_FIELD_CONST(0xf, TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_SHIFT)
#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_RANGE                    31:28
#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_MSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_LSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_WOFFSET                  0x0
#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT1_WDTSR_0
#define TKE_TOP_WDT1_WDTSR_0                    MK_ADDR_CONST(0x120004)
#define TKE_TOP_WDT1_WDTSR_0_SECURE                     0x0
#define TKE_TOP_WDT1_WDTSR_0_DUAL                       0x0
#define TKE_TOP_WDT1_WDTSR_0_SCR                        WDTSCR1_0
#define TKE_TOP_WDT1_WDTSR_0_SCRREG                     TKE_TOP_SCR_WDTSCR1_0
#define TKE_TOP_WDT1_WDTSR_0_WORD_COUNT                         0x1
#define TKE_TOP_WDT1_WDTSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_RESET_MASK                         MK_MASK_CONST(0xf7fff)
#define TKE_TOP_WDT1_WDTSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_READ_MASK                  MK_MASK_CONST(0xf7fff)
#define TKE_TOP_WDT1_WDTSR_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_Enabled_SHIFT                      MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTSR_0_Enabled_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_Enabled_SHIFT)
#define TKE_TOP_WDT1_WDTSR_0_Enabled_RANGE                      0:0
#define TKE_TOP_WDT1_WDTSR_0_Enabled_MSB                        MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTSR_0_Enabled_LSB                        MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTSR_0_Enabled_WOFFSET                    0x0
#define TKE_TOP_WDT1_WDTSR_0_Enabled_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_Enabled_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSR_0_Enabled_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_Enabled_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_Enabled_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_Enabled_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSR_0_Enabled_DISABLE                    MK_ENUM_CONST(0)
#define TKE_TOP_WDT1_WDTSR_0_Enabled_ENABLE                     MK_ENUM_CONST(1)

#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_SHIFT                 MK_SHIFT_CONST(1)
#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_SHIFT)
#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_RANGE                 1:1
#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_MSB                   MK_SHIFT_CONST(1)
#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_LSB                   MK_SHIFT_CONST(1)
#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_WOFFSET                       0x0
#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_SHIFT                       MK_SHIFT_CONST(2)
#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_SHIFT)
#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_RANGE                       2:2
#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_MSB                 MK_SHIFT_CONST(2)
#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_LSB                 MK_SHIFT_CONST(2)
#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_WOFFSET                     0x0
#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_SHIFT                        MK_SHIFT_CONST(3)
#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_SHIFT)
#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_RANGE                        3:3
#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_MSB                  MK_SHIFT_CONST(3)
#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_LSB                  MK_SHIFT_CONST(3)
#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_WOFFSET                      0x0
#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_SHIFT                 MK_SHIFT_CONST(4)
#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_FIELD                 MK_FIELD_CONST(0xff, TKE_TOP_WDT1_WDTSR_0_CurrentCount_SHIFT)
#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_RANGE                 11:4
#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_MSB                   MK_SHIFT_CONST(11)
#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_LSB                   MK_SHIFT_CONST(4)
#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_WOFFSET                       0x0
#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_SHIFT                       MK_SHIFT_CONST(12)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_SHIFT)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_RANGE                       14:12
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_MSB                 MK_SHIFT_CONST(14)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_LSB                 MK_SHIFT_CONST(12)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_WOFFSET                     0x0
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_NO_EXPIRY                   MK_ENUM_CONST(0)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_LOCAL_IRQ                   MK_ENUM_CONST(1)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_LOCAL_FIQ                   MK_ENUM_CONST(2)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_REMOTE_IRQ                  MK_ENUM_CONST(3)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_DEBUG_RESET                 MK_ENUM_CONST(4)
#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_SYSTEM_RESET                        MK_ENUM_CONST(5)

#define TKE_TOP_WDT1_WDTSR_0_CurrentError_SHIFT                 MK_SHIFT_CONST(16)
#define TKE_TOP_WDT1_WDTSR_0_CurrentError_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_CurrentError_SHIFT)
#define TKE_TOP_WDT1_WDTSR_0_CurrentError_RANGE                 16:16
#define TKE_TOP_WDT1_WDTSR_0_CurrentError_MSB                   MK_SHIFT_CONST(16)
#define TKE_TOP_WDT1_WDTSR_0_CurrentError_LSB                   MK_SHIFT_CONST(16)
#define TKE_TOP_WDT1_WDTSR_0_CurrentError_WOFFSET                       0x0
#define TKE_TOP_WDT1_WDTSR_0_CurrentError_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_CurrentError_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSR_0_CurrentError_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_CurrentError_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_CurrentError_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_CurrentError_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_SHIFT                        MK_SHIFT_CONST(17)
#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_StickyEnabled_SHIFT)
#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_RANGE                        17:17
#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_MSB                  MK_SHIFT_CONST(17)
#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_LSB                  MK_SHIFT_CONST(17)
#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_WOFFSET                      0x0
#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_SHIFT                  MK_SHIFT_CONST(18)
#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_FIELD                  MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_ErrorForced_SHIFT)
#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_RANGE                  18:18
#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_MSB                    MK_SHIFT_CONST(18)
#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_LSB                    MK_SHIFT_CONST(18)
#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_WOFFSET                        0x0
#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTSR_0_Frozen_SHIFT                       MK_SHIFT_CONST(19)
#define TKE_TOP_WDT1_WDTSR_0_Frozen_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_Frozen_SHIFT)
#define TKE_TOP_WDT1_WDTSR_0_Frozen_RANGE                       19:19
#define TKE_TOP_WDT1_WDTSR_0_Frozen_MSB                 MK_SHIFT_CONST(19)
#define TKE_TOP_WDT1_WDTSR_0_Frozen_LSB                 MK_SHIFT_CONST(19)
#define TKE_TOP_WDT1_WDTSR_0_Frozen_WOFFSET                     0x0
#define TKE_TOP_WDT1_WDTSR_0_Frozen_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_Frozen_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSR_0_Frozen_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_Frozen_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_Frozen_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSR_0_Frozen_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT1_WDTCMDR_0
#define TKE_TOP_WDT1_WDTCMDR_0                  MK_ADDR_CONST(0x120008)
#define TKE_TOP_WDT1_WDTCMDR_0_SECURE                   0x0
#define TKE_TOP_WDT1_WDTCMDR_0_DUAL                     0x0
#define TKE_TOP_WDT1_WDTCMDR_0_SCR                      WDTSCR1_0
#define TKE_TOP_WDT1_WDTCMDR_0_SCRREG                   TKE_TOP_SCR_WDTSCR1_0
#define TKE_TOP_WDT1_WDTCMDR_0_WORD_COUNT                       0x1
#define TKE_TOP_WDT1_WDTCMDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_RESET_MASK                       MK_MASK_CONST(0xf)
#define TKE_TOP_WDT1_WDTCMDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_READ_MASK                        MK_MASK_CONST(0xf)
#define TKE_TOP_WDT1_WDTCMDR_0_WRITE_MASK                       MK_MASK_CONST(0xf)
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCMDR_0_StartCounter_SHIFT)
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_RANGE                       0:0
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_MSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_WOFFSET                     0x0
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_DISABLE                     MK_ENUM_CONST(0)
#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_ENABLE                      MK_ENUM_CONST(1)

#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_SHIFT                     MK_SHIFT_CONST(1)
#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_SHIFT)
#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_RANGE                     1:1
#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_MSB                       MK_SHIFT_CONST(1)
#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_LSB                       MK_SHIFT_CONST(1)
#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_WOFFSET                   0x0
#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_DISABLE                   MK_ENUM_CONST(0)
#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_ENABLE                    MK_ENUM_CONST(1)

#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_SHIFT                        MK_SHIFT_CONST(2)
#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCMDR_0_StickyStart_SHIFT)
#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_RANGE                        2:2
#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_MSB                  MK_SHIFT_CONST(2)
#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_LSB                  MK_SHIFT_CONST(2)
#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_WOFFSET                      0x0
#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_SHIFT                 MK_SHIFT_CONST(3)
#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCMDR_0_ForceError_SHIFT)
#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_RANGE                 3:3
#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_MSB                   MK_SHIFT_CONST(3)
#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_LSB                   MK_SHIFT_CONST(3)
#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_WOFFSET                       0x0
#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT1_WDTUR_0
#define TKE_TOP_WDT1_WDTUR_0                    MK_ADDR_CONST(0x12000c)
#define TKE_TOP_WDT1_WDTUR_0_SECURE                     0x0
#define TKE_TOP_WDT1_WDTUR_0_DUAL                       0x0
#define TKE_TOP_WDT1_WDTUR_0_SCR                        WDTSCR1_0
#define TKE_TOP_WDT1_WDTUR_0_SCRREG                     TKE_TOP_SCR_WDTSCR1_0
#define TKE_TOP_WDT1_WDTUR_0_WORD_COUNT                         0x1
#define TKE_TOP_WDT1_WDTUR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTUR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define TKE_TOP_WDT1_WDTUR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTUR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTUR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define TKE_TOP_WDT1_WDTUR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_WDT1_WDTUR_0_UnlockPattern_SHIFT)
#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_RANGE                        31:0
#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_MSB                  MK_SHIFT_CONST(31)
#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_WOFFSET                      0x0
#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_UNLOCK                       MK_ENUM_CONST(50266)


// Register TKE_TOP_WDT1_WDTSCR_0
#define TKE_TOP_WDT1_WDTSCR_0                   MK_ADDR_CONST(0x120010)
#define TKE_TOP_WDT1_WDTSCR_0_SECURE                    0x0
#define TKE_TOP_WDT1_WDTSCR_0_DUAL                      0x0
#define TKE_TOP_WDT1_WDTSCR_0_SCR                       WDTSCR1_0
#define TKE_TOP_WDT1_WDTSCR_0_SCRREG                    TKE_TOP_SCR_WDTSCR1_0
#define TKE_TOP_WDT1_WDTSCR_0_WORD_COUNT                        0x1
#define TKE_TOP_WDT1_WDTSCR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_RESET_MASK                        MK_MASK_CONST(0x7777)
#define TKE_TOP_WDT1_WDTSCR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_READ_MASK                         MK_MASK_CONST(0x7777)
#define TKE_TOP_WDT1_WDTSCR_0_WRITE_MASK                        MK_MASK_CONST(0x7777)
#define TKE_TOP_WDT1_WDTSCR_0_Skip0_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip0_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTSCR_0_Skip0_SHIFT)
#define TKE_TOP_WDT1_WDTSCR_0_Skip0_RANGE                       2:0
#define TKE_TOP_WDT1_WDTSCR_0_Skip0_MSB                 MK_SHIFT_CONST(2)
#define TKE_TOP_WDT1_WDTSCR_0_Skip0_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip0_WOFFSET                     0x0
#define TKE_TOP_WDT1_WDTSCR_0_Skip0_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip0_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT1_WDTSCR_0_Skip0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSCR_0_Skip0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTSCR_0_Skip1_SHIFT                       MK_SHIFT_CONST(4)
#define TKE_TOP_WDT1_WDTSCR_0_Skip1_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTSCR_0_Skip1_SHIFT)
#define TKE_TOP_WDT1_WDTSCR_0_Skip1_RANGE                       6:4
#define TKE_TOP_WDT1_WDTSCR_0_Skip1_MSB                 MK_SHIFT_CONST(6)
#define TKE_TOP_WDT1_WDTSCR_0_Skip1_LSB                 MK_SHIFT_CONST(4)
#define TKE_TOP_WDT1_WDTSCR_0_Skip1_WOFFSET                     0x0
#define TKE_TOP_WDT1_WDTSCR_0_Skip1_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip1_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT1_WDTSCR_0_Skip1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSCR_0_Skip1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTSCR_0_Skip2_SHIFT                       MK_SHIFT_CONST(8)
#define TKE_TOP_WDT1_WDTSCR_0_Skip2_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTSCR_0_Skip2_SHIFT)
#define TKE_TOP_WDT1_WDTSCR_0_Skip2_RANGE                       10:8
#define TKE_TOP_WDT1_WDTSCR_0_Skip2_MSB                 MK_SHIFT_CONST(10)
#define TKE_TOP_WDT1_WDTSCR_0_Skip2_LSB                 MK_SHIFT_CONST(8)
#define TKE_TOP_WDT1_WDTSCR_0_Skip2_WOFFSET                     0x0
#define TKE_TOP_WDT1_WDTSCR_0_Skip2_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip2_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT1_WDTSCR_0_Skip2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSCR_0_Skip2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTSCR_0_Skip3_SHIFT                       MK_SHIFT_CONST(12)
#define TKE_TOP_WDT1_WDTSCR_0_Skip3_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTSCR_0_Skip3_SHIFT)
#define TKE_TOP_WDT1_WDTSCR_0_Skip3_RANGE                       14:12
#define TKE_TOP_WDT1_WDTSCR_0_Skip3_MSB                 MK_SHIFT_CONST(14)
#define TKE_TOP_WDT1_WDTSCR_0_Skip3_LSB                 MK_SHIFT_CONST(12)
#define TKE_TOP_WDT1_WDTSCR_0_Skip3_WOFFSET                     0x0
#define TKE_TOP_WDT1_WDTSCR_0_Skip3_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip3_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT1_WDTSCR_0_Skip3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTSCR_0_Skip3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTSCR_0_Skip3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT1_WDTFWCR_0
#define TKE_TOP_WDT1_WDTFWCR_0                  MK_ADDR_CONST(0x120014)
#define TKE_TOP_WDT1_WDTFWCR_0_SECURE                   0x0
#define TKE_TOP_WDT1_WDTFWCR_0_DUAL                     0x0
#define TKE_TOP_WDT1_WDTFWCR_0_SCR                      WDTSCR1_0
#define TKE_TOP_WDT1_WDTFWCR_0_SCRREG                   TKE_TOP_SCR_WDTSCR1_0
#define TKE_TOP_WDT1_WDTFWCR_0_WORD_COUNT                       0x1
#define TKE_TOP_WDT1_WDTFWCR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTFWCR_0_RESET_MASK                       MK_MASK_CONST(0x700ff)
#define TKE_TOP_WDT1_WDTFWCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTFWCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTFWCR_0_READ_MASK                        MK_MASK_CONST(0x700ff)
#define TKE_TOP_WDT1_WDTFWCR_0_WRITE_MASK                       MK_MASK_CONST(0x700ff)
#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_SHIFT                 MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_FIELD                 MK_FIELD_CONST(0xff, TKE_TOP_WDT1_WDTFWCR_0_StartCount_SHIFT)
#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_RANGE                 7:0
#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_MSB                   MK_SHIFT_CONST(7)
#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_LSB                   MK_SHIFT_CONST(0)
#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_WOFFSET                       0x0
#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_SHIFT                 MK_SHIFT_CONST(16)
#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_FIELD                 MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTFWCR_0_StartLevel_SHIFT)
#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_RANGE                 18:16
#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_MSB                   MK_SHIFT_CONST(18)
#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_LSB                   MK_SHIFT_CONST(16)
#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_WOFFSET                       0x0
#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT2_WDTCR_0
#define TKE_TOP_WDT2_WDTCR_0                    MK_ADDR_CONST(0x130000)
#define TKE_TOP_WDT2_WDTCR_0_SECURE                     0x0
#define TKE_TOP_WDT2_WDTCR_0_DUAL                       0x0
#define TKE_TOP_WDT2_WDTCR_0_SCR                        WDTSCR2_0
#define TKE_TOP_WDT2_WDTCR_0_SCRREG                     TKE_TOP_SCR_WDTSCR2_0
#define TKE_TOP_WDT2_WDTCR_0_WORD_COUNT                         0x1
#define TKE_TOP_WDT2_WDTCR_0_RESET_VAL                  MK_MASK_CONST(0x700000)
#define TKE_TOP_WDT2_WDTCR_0_RESET_MASK                         MK_MASK_CONST(0xf3ffffff)
#define TKE_TOP_WDT2_WDTCR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_READ_MASK                  MK_MASK_CONST(0xf3ffffff)
#define TKE_TOP_WDT2_WDTCR_0_WRITE_MASK                         MK_MASK_CONST(0xf3ffffff)
#define TKE_TOP_WDT2_WDTCR_0_TimerSource_SHIFT                  MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTCR_0_TimerSource_FIELD                  MK_FIELD_CONST(0xf, TKE_TOP_WDT2_WDTCR_0_TimerSource_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_TimerSource_RANGE                  3:0
#define TKE_TOP_WDT2_WDTCR_0_TimerSource_MSB                    MK_SHIFT_CONST(3)
#define TKE_TOP_WDT2_WDTCR_0_TimerSource_LSB                    MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTCR_0_TimerSource_WOFFSET                        0x0
#define TKE_TOP_WDT2_WDTCR_0_TimerSource_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_TimerSource_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define TKE_TOP_WDT2_WDTCR_0_TimerSource_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_TimerSource_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_TimerSource_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_TimerSource_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_TimerSource_TMR0                   MK_ENUM_CONST(0)

#define TKE_TOP_WDT2_WDTCR_0_Period_SHIFT                       MK_SHIFT_CONST(4)
#define TKE_TOP_WDT2_WDTCR_0_Period_FIELD                       MK_FIELD_CONST(0xff, TKE_TOP_WDT2_WDTCR_0_Period_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_Period_RANGE                       11:4
#define TKE_TOP_WDT2_WDTCR_0_Period_MSB                 MK_SHIFT_CONST(11)
#define TKE_TOP_WDT2_WDTCR_0_Period_LSB                 MK_SHIFT_CONST(4)
#define TKE_TOP_WDT2_WDTCR_0_Period_WOFFSET                     0x0
#define TKE_TOP_WDT2_WDTCR_0_Period_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_Period_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define TKE_TOP_WDT2_WDTCR_0_Period_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_Period_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_Period_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_Period_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_SHIFT                 MK_SHIFT_CONST(12)
#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_RANGE                 12:12
#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_MSB                   MK_SHIFT_CONST(12)
#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_LSB                   MK_SHIFT_CONST(12)
#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_WOFFSET                       0x0
#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_SHIFT                       MK_SHIFT_CONST(13)
#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_RANGE                       13:13
#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_MSB                 MK_SHIFT_CONST(13)
#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_LSB                 MK_SHIFT_CONST(13)
#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_WOFFSET                     0x0
#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_SHIFT                        MK_SHIFT_CONST(14)
#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_RANGE                        14:14
#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_MSB                  MK_SHIFT_CONST(14)
#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_LSB                  MK_SHIFT_CONST(14)
#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_WOFFSET                      0x0
#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_SHIFT                       MK_SHIFT_CONST(15)
#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_RANGE                       15:15
#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_MSB                 MK_SHIFT_CONST(15)
#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_LSB                 MK_SHIFT_CONST(15)
#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_WOFFSET                     0x0
#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_SHIFT                  MK_SHIFT_CONST(16)
#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_FIELD                  MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_RANGE                  16:16
#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_MSB                    MK_SHIFT_CONST(16)
#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_LSB                    MK_SHIFT_CONST(16)
#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_WOFFSET                        0x0
#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_DISABLE                        MK_ENUM_CONST(0)
#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_ENABLE                 MK_ENUM_CONST(1)

#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_SHIFT                      MK_SHIFT_CONST(17)
#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_RANGE                      17:17
#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_MSB                        MK_SHIFT_CONST(17)
#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_LSB                        MK_SHIFT_CONST(17)
#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_WOFFSET                    0x0
#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_SHIFT                      MK_SHIFT_CONST(18)
#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_RANGE                      18:18
#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_MSB                        MK_SHIFT_CONST(18)
#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_LSB                        MK_SHIFT_CONST(18)
#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_WOFFSET                    0x0
#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_SHIFT                   MK_SHIFT_CONST(19)
#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_RANGE                   19:19
#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_MSB                     MK_SHIFT_CONST(19)
#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_LSB                     MK_SHIFT_CONST(19)
#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_WOFFSET                 0x0
#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_SHIFT                       MK_SHIFT_CONST(20)
#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_RANGE                       22:20
#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_MSB                 MK_SHIFT_CONST(22)
#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_LSB                 MK_SHIFT_CONST(20)
#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_WOFFSET                     0x0
#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_DEFAULT                     MK_MASK_CONST(0x7)
#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_SHIFT                   MK_SHIFT_CONST(23)
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_FIELD                   MK_FIELD_CONST(0x3, TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_RANGE                   24:23
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_MSB                     MK_SHIFT_CONST(24)
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_LSB                     MK_SHIFT_CONST(23)
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_WOFFSET                 0x0
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_NOP                     MK_ENUM_CONST(0)
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_JUMP_TO_4                       MK_ENUM_CONST(1)
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_JUMP_TO_5                       MK_ENUM_CONST(2)
#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_POR_RESET                       MK_ENUM_CONST(3)

#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_SHIFT                    MK_SHIFT_CONST(25)
#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_RANGE                    25:25
#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_MSB                      MK_SHIFT_CONST(25)
#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_LSB                      MK_SHIFT_CONST(25)
#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_WOFFSET                  0x0
#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_SHIFT                    MK_SHIFT_CONST(28)
#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_FIELD                    MK_FIELD_CONST(0xf, TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_SHIFT)
#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_RANGE                    31:28
#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_MSB                      MK_SHIFT_CONST(31)
#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_LSB                      MK_SHIFT_CONST(28)
#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_WOFFSET                  0x0
#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_DEFAULT_MASK                     MK_MASK_CONST(0xf)
#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT2_WDTSR_0
#define TKE_TOP_WDT2_WDTSR_0                    MK_ADDR_CONST(0x130004)
#define TKE_TOP_WDT2_WDTSR_0_SECURE                     0x0
#define TKE_TOP_WDT2_WDTSR_0_DUAL                       0x0
#define TKE_TOP_WDT2_WDTSR_0_SCR                        WDTSCR2_0
#define TKE_TOP_WDT2_WDTSR_0_SCRREG                     TKE_TOP_SCR_WDTSCR2_0
#define TKE_TOP_WDT2_WDTSR_0_WORD_COUNT                         0x1
#define TKE_TOP_WDT2_WDTSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_RESET_MASK                         MK_MASK_CONST(0xf7fff)
#define TKE_TOP_WDT2_WDTSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_READ_MASK                  MK_MASK_CONST(0xf7fff)
#define TKE_TOP_WDT2_WDTSR_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_Enabled_SHIFT                      MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTSR_0_Enabled_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_Enabled_SHIFT)
#define TKE_TOP_WDT2_WDTSR_0_Enabled_RANGE                      0:0
#define TKE_TOP_WDT2_WDTSR_0_Enabled_MSB                        MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTSR_0_Enabled_LSB                        MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTSR_0_Enabled_WOFFSET                    0x0
#define TKE_TOP_WDT2_WDTSR_0_Enabled_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_Enabled_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSR_0_Enabled_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_Enabled_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_Enabled_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_Enabled_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSR_0_Enabled_DISABLE                    MK_ENUM_CONST(0)
#define TKE_TOP_WDT2_WDTSR_0_Enabled_ENABLE                     MK_ENUM_CONST(1)

#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_SHIFT                 MK_SHIFT_CONST(1)
#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_SHIFT)
#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_RANGE                 1:1
#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_MSB                   MK_SHIFT_CONST(1)
#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_LSB                   MK_SHIFT_CONST(1)
#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_WOFFSET                       0x0
#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_SHIFT                       MK_SHIFT_CONST(2)
#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_SHIFT)
#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_RANGE                       2:2
#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_MSB                 MK_SHIFT_CONST(2)
#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_LSB                 MK_SHIFT_CONST(2)
#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_WOFFSET                     0x0
#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_SHIFT                        MK_SHIFT_CONST(3)
#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_SHIFT)
#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_RANGE                        3:3
#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_MSB                  MK_SHIFT_CONST(3)
#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_LSB                  MK_SHIFT_CONST(3)
#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_WOFFSET                      0x0
#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_SHIFT                 MK_SHIFT_CONST(4)
#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_FIELD                 MK_FIELD_CONST(0xff, TKE_TOP_WDT2_WDTSR_0_CurrentCount_SHIFT)
#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_RANGE                 11:4
#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_MSB                   MK_SHIFT_CONST(11)
#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_LSB                   MK_SHIFT_CONST(4)
#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_WOFFSET                       0x0
#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_SHIFT                       MK_SHIFT_CONST(12)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_SHIFT)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_RANGE                       14:12
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_MSB                 MK_SHIFT_CONST(14)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_LSB                 MK_SHIFT_CONST(12)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_WOFFSET                     0x0
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_NO_EXPIRY                   MK_ENUM_CONST(0)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_LOCAL_IRQ                   MK_ENUM_CONST(1)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_LOCAL_FIQ                   MK_ENUM_CONST(2)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_REMOTE_IRQ                  MK_ENUM_CONST(3)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_DEBUG_RESET                 MK_ENUM_CONST(4)
#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_SYSTEM_RESET                        MK_ENUM_CONST(5)

#define TKE_TOP_WDT2_WDTSR_0_CurrentError_SHIFT                 MK_SHIFT_CONST(16)
#define TKE_TOP_WDT2_WDTSR_0_CurrentError_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_CurrentError_SHIFT)
#define TKE_TOP_WDT2_WDTSR_0_CurrentError_RANGE                 16:16
#define TKE_TOP_WDT2_WDTSR_0_CurrentError_MSB                   MK_SHIFT_CONST(16)
#define TKE_TOP_WDT2_WDTSR_0_CurrentError_LSB                   MK_SHIFT_CONST(16)
#define TKE_TOP_WDT2_WDTSR_0_CurrentError_WOFFSET                       0x0
#define TKE_TOP_WDT2_WDTSR_0_CurrentError_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_CurrentError_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSR_0_CurrentError_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_CurrentError_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_CurrentError_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_CurrentError_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_SHIFT                        MK_SHIFT_CONST(17)
#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_StickyEnabled_SHIFT)
#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_RANGE                        17:17
#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_MSB                  MK_SHIFT_CONST(17)
#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_LSB                  MK_SHIFT_CONST(17)
#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_WOFFSET                      0x0
#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_SHIFT                  MK_SHIFT_CONST(18)
#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_FIELD                  MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_ErrorForced_SHIFT)
#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_RANGE                  18:18
#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_MSB                    MK_SHIFT_CONST(18)
#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_LSB                    MK_SHIFT_CONST(18)
#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_WOFFSET                        0x0
#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTSR_0_Frozen_SHIFT                       MK_SHIFT_CONST(19)
#define TKE_TOP_WDT2_WDTSR_0_Frozen_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_Frozen_SHIFT)
#define TKE_TOP_WDT2_WDTSR_0_Frozen_RANGE                       19:19
#define TKE_TOP_WDT2_WDTSR_0_Frozen_MSB                 MK_SHIFT_CONST(19)
#define TKE_TOP_WDT2_WDTSR_0_Frozen_LSB                 MK_SHIFT_CONST(19)
#define TKE_TOP_WDT2_WDTSR_0_Frozen_WOFFSET                     0x0
#define TKE_TOP_WDT2_WDTSR_0_Frozen_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_Frozen_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSR_0_Frozen_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_Frozen_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_Frozen_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSR_0_Frozen_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT2_WDTCMDR_0
#define TKE_TOP_WDT2_WDTCMDR_0                  MK_ADDR_CONST(0x130008)
#define TKE_TOP_WDT2_WDTCMDR_0_SECURE                   0x0
#define TKE_TOP_WDT2_WDTCMDR_0_DUAL                     0x0
#define TKE_TOP_WDT2_WDTCMDR_0_SCR                      WDTSCR2_0
#define TKE_TOP_WDT2_WDTCMDR_0_SCRREG                   TKE_TOP_SCR_WDTSCR2_0
#define TKE_TOP_WDT2_WDTCMDR_0_WORD_COUNT                       0x1
#define TKE_TOP_WDT2_WDTCMDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_RESET_MASK                       MK_MASK_CONST(0xf)
#define TKE_TOP_WDT2_WDTCMDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_READ_MASK                        MK_MASK_CONST(0xf)
#define TKE_TOP_WDT2_WDTCMDR_0_WRITE_MASK                       MK_MASK_CONST(0xf)
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCMDR_0_StartCounter_SHIFT)
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_RANGE                       0:0
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_MSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_WOFFSET                     0x0
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_DISABLE                     MK_ENUM_CONST(0)
#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_ENABLE                      MK_ENUM_CONST(1)

#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_SHIFT                     MK_SHIFT_CONST(1)
#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_SHIFT)
#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_RANGE                     1:1
#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_MSB                       MK_SHIFT_CONST(1)
#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_LSB                       MK_SHIFT_CONST(1)
#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_WOFFSET                   0x0
#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_DISABLE                   MK_ENUM_CONST(0)
#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_ENABLE                    MK_ENUM_CONST(1)

#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_SHIFT                        MK_SHIFT_CONST(2)
#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCMDR_0_StickyStart_SHIFT)
#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_RANGE                        2:2
#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_MSB                  MK_SHIFT_CONST(2)
#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_LSB                  MK_SHIFT_CONST(2)
#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_WOFFSET                      0x0
#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_SHIFT                 MK_SHIFT_CONST(3)
#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCMDR_0_ForceError_SHIFT)
#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_RANGE                 3:3
#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_MSB                   MK_SHIFT_CONST(3)
#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_LSB                   MK_SHIFT_CONST(3)
#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_WOFFSET                       0x0
#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT2_WDTUR_0
#define TKE_TOP_WDT2_WDTUR_0                    MK_ADDR_CONST(0x13000c)
#define TKE_TOP_WDT2_WDTUR_0_SECURE                     0x0
#define TKE_TOP_WDT2_WDTUR_0_DUAL                       0x0
#define TKE_TOP_WDT2_WDTUR_0_SCR                        WDTSCR2_0
#define TKE_TOP_WDT2_WDTUR_0_SCRREG                     TKE_TOP_SCR_WDTSCR2_0
#define TKE_TOP_WDT2_WDTUR_0_WORD_COUNT                         0x1
#define TKE_TOP_WDT2_WDTUR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTUR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define TKE_TOP_WDT2_WDTUR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTUR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTUR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define TKE_TOP_WDT2_WDTUR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_SHIFT                        MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_WDT2_WDTUR_0_UnlockPattern_SHIFT)
#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_RANGE                        31:0
#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_MSB                  MK_SHIFT_CONST(31)
#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_LSB                  MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_WOFFSET                      0x0
#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_DEFAULT                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_UNLOCK                       MK_ENUM_CONST(50266)


// Register TKE_TOP_WDT2_WDTSCR_0
#define TKE_TOP_WDT2_WDTSCR_0                   MK_ADDR_CONST(0x130010)
#define TKE_TOP_WDT2_WDTSCR_0_SECURE                    0x0
#define TKE_TOP_WDT2_WDTSCR_0_DUAL                      0x0
#define TKE_TOP_WDT2_WDTSCR_0_SCR                       WDTSCR2_0
#define TKE_TOP_WDT2_WDTSCR_0_SCRREG                    TKE_TOP_SCR_WDTSCR2_0
#define TKE_TOP_WDT2_WDTSCR_0_WORD_COUNT                        0x1
#define TKE_TOP_WDT2_WDTSCR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_RESET_MASK                        MK_MASK_CONST(0x7777)
#define TKE_TOP_WDT2_WDTSCR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_READ_MASK                         MK_MASK_CONST(0x7777)
#define TKE_TOP_WDT2_WDTSCR_0_WRITE_MASK                        MK_MASK_CONST(0x7777)
#define TKE_TOP_WDT2_WDTSCR_0_Skip0_SHIFT                       MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip0_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTSCR_0_Skip0_SHIFT)
#define TKE_TOP_WDT2_WDTSCR_0_Skip0_RANGE                       2:0
#define TKE_TOP_WDT2_WDTSCR_0_Skip0_MSB                 MK_SHIFT_CONST(2)
#define TKE_TOP_WDT2_WDTSCR_0_Skip0_LSB                 MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip0_WOFFSET                     0x0
#define TKE_TOP_WDT2_WDTSCR_0_Skip0_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip0_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT2_WDTSCR_0_Skip0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSCR_0_Skip0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTSCR_0_Skip1_SHIFT                       MK_SHIFT_CONST(4)
#define TKE_TOP_WDT2_WDTSCR_0_Skip1_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTSCR_0_Skip1_SHIFT)
#define TKE_TOP_WDT2_WDTSCR_0_Skip1_RANGE                       6:4
#define TKE_TOP_WDT2_WDTSCR_0_Skip1_MSB                 MK_SHIFT_CONST(6)
#define TKE_TOP_WDT2_WDTSCR_0_Skip1_LSB                 MK_SHIFT_CONST(4)
#define TKE_TOP_WDT2_WDTSCR_0_Skip1_WOFFSET                     0x0
#define TKE_TOP_WDT2_WDTSCR_0_Skip1_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip1_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT2_WDTSCR_0_Skip1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSCR_0_Skip1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTSCR_0_Skip2_SHIFT                       MK_SHIFT_CONST(8)
#define TKE_TOP_WDT2_WDTSCR_0_Skip2_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTSCR_0_Skip2_SHIFT)
#define TKE_TOP_WDT2_WDTSCR_0_Skip2_RANGE                       10:8
#define TKE_TOP_WDT2_WDTSCR_0_Skip2_MSB                 MK_SHIFT_CONST(10)
#define TKE_TOP_WDT2_WDTSCR_0_Skip2_LSB                 MK_SHIFT_CONST(8)
#define TKE_TOP_WDT2_WDTSCR_0_Skip2_WOFFSET                     0x0
#define TKE_TOP_WDT2_WDTSCR_0_Skip2_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip2_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT2_WDTSCR_0_Skip2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSCR_0_Skip2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTSCR_0_Skip3_SHIFT                       MK_SHIFT_CONST(12)
#define TKE_TOP_WDT2_WDTSCR_0_Skip3_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTSCR_0_Skip3_SHIFT)
#define TKE_TOP_WDT2_WDTSCR_0_Skip3_RANGE                       14:12
#define TKE_TOP_WDT2_WDTSCR_0_Skip3_MSB                 MK_SHIFT_CONST(14)
#define TKE_TOP_WDT2_WDTSCR_0_Skip3_LSB                 MK_SHIFT_CONST(12)
#define TKE_TOP_WDT2_WDTSCR_0_Skip3_WOFFSET                     0x0
#define TKE_TOP_WDT2_WDTSCR_0_Skip3_DEFAULT                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip3_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define TKE_TOP_WDT2_WDTSCR_0_Skip3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTSCR_0_Skip3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTSCR_0_Skip3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register TKE_TOP_WDT2_WDTFWCR_0
#define TKE_TOP_WDT2_WDTFWCR_0                  MK_ADDR_CONST(0x130014)
#define TKE_TOP_WDT2_WDTFWCR_0_SECURE                   0x0
#define TKE_TOP_WDT2_WDTFWCR_0_DUAL                     0x0
#define TKE_TOP_WDT2_WDTFWCR_0_SCR                      WDTSCR2_0
#define TKE_TOP_WDT2_WDTFWCR_0_SCRREG                   TKE_TOP_SCR_WDTSCR2_0
#define TKE_TOP_WDT2_WDTFWCR_0_WORD_COUNT                       0x1
#define TKE_TOP_WDT2_WDTFWCR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTFWCR_0_RESET_MASK                       MK_MASK_CONST(0x700ff)
#define TKE_TOP_WDT2_WDTFWCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTFWCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTFWCR_0_READ_MASK                        MK_MASK_CONST(0x700ff)
#define TKE_TOP_WDT2_WDTFWCR_0_WRITE_MASK                       MK_MASK_CONST(0x700ff)
#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_SHIFT                 MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_FIELD                 MK_FIELD_CONST(0xff, TKE_TOP_WDT2_WDTFWCR_0_StartCount_SHIFT)
#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_RANGE                 7:0
#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_MSB                   MK_SHIFT_CONST(7)
#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_LSB                   MK_SHIFT_CONST(0)
#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_WOFFSET                       0x0
#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_SHIFT                 MK_SHIFT_CONST(16)
#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_FIELD                 MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTFWCR_0_StartLevel_SHIFT)
#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_RANGE                 18:16
#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_MSB                   MK_SHIFT_CONST(18)
#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_LSB                   MK_SHIFT_CONST(16)
#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_WOFFSET                       0x0
#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_DEFAULT                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARTKE_TOP_REGS(_op_) \
_op_(TKE_TOP_SHARED_TKETSC0_0) \
_op_(TKE_TOP_SHARED_TKETSC1_0) \
_op_(TKE_TOP_SHARED_TKEUSEC_0) \
_op_(TKE_TOP_SHARED_TKEOSC_0) \
_op_(TKE_TOP_SHARED_TKECR_0) \
_op_(TKE_TOP_SHARED_CLK_OVR_ON_0) \
_op_(TKE_TOP_SHARED_TKEIE0_0) \
_op_(TKE_TOP_SHARED_TKEIE1_0) \
_op_(TKE_TOP_SHARED_TKEIE2_0) \
_op_(TKE_TOP_SHARED_TKEIE3_0) \
_op_(TKE_TOP_SHARED_TKEIE4_0) \
_op_(TKE_TOP_SHARED_TKEIE5_0) \
_op_(TKE_TOP_SHARED_TKEIE6_0) \
_op_(TKE_TOP_SHARED_TKEIE7_0) \
_op_(TKE_TOP_SHARED_TKEIE8_0) \
_op_(TKE_TOP_SHARED_TKEIE9_0) \
_op_(TKE_TOP_SHARED_TKEIE10_0) \
_op_(TKE_TOP_SHARED_TKEIE11_0) \
_op_(TKE_TOP_SHARED_TKEIE12_0) \
_op_(TKE_TOP_SHARED_TKEIE13_0) \
_op_(TKE_TOP_SHARED_TKEIE14_0) \
_op_(TKE_TOP_SHARED_TKEIE15_0) \
_op_(TKE_TOP_SHARED_TKEIV_0) \
_op_(TKE_TOP_SHARED_TKEIR_0) \
_op_(TKE_TOP_TIMER_TMR0_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR0_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR0_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR0_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR1_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR1_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR1_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR1_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR2_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR2_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR2_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR2_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR3_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR3_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR3_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR3_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR4_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR4_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR4_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR4_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR5_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR5_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR5_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR5_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR6_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR6_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR6_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR6_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR7_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR7_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR7_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR7_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR8_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR8_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR8_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR8_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR9_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR9_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR9_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR9_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR10_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR10_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR10_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR10_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR11_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR11_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR11_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR11_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR12_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR12_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR12_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR12_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR13_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR13_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR13_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR13_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR14_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR14_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR14_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR14_TMRATR_0) \
_op_(TKE_TOP_TIMER_TMR15_TMRCR_0) \
_op_(TKE_TOP_TIMER_TMR15_TMRSR_0) \
_op_(TKE_TOP_TIMER_TMR15_TMRCSSR_0) \
_op_(TKE_TOP_TIMER_TMR15_TMRATR_0) \
_op_(TKE_TOP_WDT0_WDTCR_0) \
_op_(TKE_TOP_WDT0_WDTSR_0) \
_op_(TKE_TOP_WDT0_WDTCMDR_0) \
_op_(TKE_TOP_WDT0_WDTUR_0) \
_op_(TKE_TOP_WDT0_WDTSCR_0) \
_op_(TKE_TOP_WDT0_WDTFWCR_0) \
_op_(TKE_TOP_WDT1_WDTCR_0) \
_op_(TKE_TOP_WDT1_WDTSR_0) \
_op_(TKE_TOP_WDT1_WDTCMDR_0) \
_op_(TKE_TOP_WDT1_WDTUR_0) \
_op_(TKE_TOP_WDT1_WDTSCR_0) \
_op_(TKE_TOP_WDT1_WDTFWCR_0) \
_op_(TKE_TOP_WDT2_WDTCR_0) \
_op_(TKE_TOP_WDT2_WDTSR_0) \
_op_(TKE_TOP_WDT2_WDTCMDR_0) \
_op_(TKE_TOP_WDT2_WDTUR_0) \
_op_(TKE_TOP_WDT2_WDTSCR_0) \
_op_(TKE_TOP_WDT2_WDTFWCR_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_TKE_TOP_SHARED     0x00000000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR0 0x00010000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR1 0x00020000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR2 0x00030000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR3 0x00040000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR4 0x00050000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR5 0x00060000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR6 0x00070000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR7 0x00080000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR8 0x00090000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR9 0x000a0000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR10        0x000b0000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR11        0x000c0000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR12        0x000d0000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR13        0x000e0000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR14        0x000f0000
#define BASE_ADDRESS_TKE_TOP_TIMER_TMR15        0x00100000
#define BASE_ADDRESS_TKE_TOP_WDT0       0x00110000
#define BASE_ADDRESS_TKE_TOP_WDT1       0x00120000
#define BASE_ADDRESS_TKE_TOP_WDT2       0x00130000

//
// ARTKE_TOP REGISTER BANKS
//

#define TKE_TOP_SHARED0_FIRST_REG 0x0000 // TKE_TOP_SHARED_TKETSC0_0
#define TKE_TOP_SHARED0_LAST_REG 0x0014 // TKE_TOP_SHARED_CLK_OVR_ON_0
#define TKE_TOP_SHARED1_FIRST_REG 0x0100 // TKE_TOP_SHARED_TKEIE0_0
#define TKE_TOP_SHARED1_LAST_REG 0x013c // TKE_TOP_SHARED_TKEIE15_0
#define TKE_TOP_SHARED2_FIRST_REG 0x0200 // TKE_TOP_SHARED_TKEIV_0
#define TKE_TOP_SHARED2_LAST_REG 0x0204 // TKE_TOP_SHARED_TKEIR_0
#define TKE_TOP_TIMER_TMR00_FIRST_REG 0x10000 // TKE_TOP_TIMER_TMR0_TMRCR_0
#define TKE_TOP_TIMER_TMR00_LAST_REG 0x1000c // TKE_TOP_TIMER_TMR0_TMRATR_0
#define TKE_TOP_TIMER_TMR10_FIRST_REG 0x20000 // TKE_TOP_TIMER_TMR1_TMRCR_0
#define TKE_TOP_TIMER_TMR10_LAST_REG 0x2000c // TKE_TOP_TIMER_TMR1_TMRATR_0
#define TKE_TOP_TIMER_TMR20_FIRST_REG 0x30000 // TKE_TOP_TIMER_TMR2_TMRCR_0
#define TKE_TOP_TIMER_TMR20_LAST_REG 0x3000c // TKE_TOP_TIMER_TMR2_TMRATR_0
#define TKE_TOP_TIMER_TMR30_FIRST_REG 0x40000 // TKE_TOP_TIMER_TMR3_TMRCR_0
#define TKE_TOP_TIMER_TMR30_LAST_REG 0x4000c // TKE_TOP_TIMER_TMR3_TMRATR_0
#define TKE_TOP_TIMER_TMR40_FIRST_REG 0x50000 // TKE_TOP_TIMER_TMR4_TMRCR_0
#define TKE_TOP_TIMER_TMR40_LAST_REG 0x5000c // TKE_TOP_TIMER_TMR4_TMRATR_0
#define TKE_TOP_TIMER_TMR50_FIRST_REG 0x60000 // TKE_TOP_TIMER_TMR5_TMRCR_0
#define TKE_TOP_TIMER_TMR50_LAST_REG 0x6000c // TKE_TOP_TIMER_TMR5_TMRATR_0
#define TKE_TOP_TIMER_TMR60_FIRST_REG 0x70000 // TKE_TOP_TIMER_TMR6_TMRCR_0
#define TKE_TOP_TIMER_TMR60_LAST_REG 0x7000c // TKE_TOP_TIMER_TMR6_TMRATR_0
#define TKE_TOP_TIMER_TMR70_FIRST_REG 0x80000 // TKE_TOP_TIMER_TMR7_TMRCR_0
#define TKE_TOP_TIMER_TMR70_LAST_REG 0x8000c // TKE_TOP_TIMER_TMR7_TMRATR_0
#define TKE_TOP_TIMER_TMR80_FIRST_REG 0x90000 // TKE_TOP_TIMER_TMR8_TMRCR_0
#define TKE_TOP_TIMER_TMR80_LAST_REG 0x9000c // TKE_TOP_TIMER_TMR8_TMRATR_0
#define TKE_TOP_TIMER_TMR90_FIRST_REG 0xa0000 // TKE_TOP_TIMER_TMR9_TMRCR_0
#define TKE_TOP_TIMER_TMR90_LAST_REG 0xa000c // TKE_TOP_TIMER_TMR9_TMRATR_0
#define TKE_TOP_TIMER_TMR100_FIRST_REG 0xb0000 // TKE_TOP_TIMER_TMR10_TMRCR_0
#define TKE_TOP_TIMER_TMR100_LAST_REG 0xb000c // TKE_TOP_TIMER_TMR10_TMRATR_0
#define TKE_TOP_TIMER_TMR110_FIRST_REG 0xc0000 // TKE_TOP_TIMER_TMR11_TMRCR_0
#define TKE_TOP_TIMER_TMR110_LAST_REG 0xc000c // TKE_TOP_TIMER_TMR11_TMRATR_0
#define TKE_TOP_TIMER_TMR120_FIRST_REG 0xd0000 // TKE_TOP_TIMER_TMR12_TMRCR_0
#define TKE_TOP_TIMER_TMR120_LAST_REG 0xd000c // TKE_TOP_TIMER_TMR12_TMRATR_0
#define TKE_TOP_TIMER_TMR130_FIRST_REG 0xe0000 // TKE_TOP_TIMER_TMR13_TMRCR_0
#define TKE_TOP_TIMER_TMR130_LAST_REG 0xe000c // TKE_TOP_TIMER_TMR13_TMRATR_0
#define TKE_TOP_TIMER_TMR140_FIRST_REG 0xf0000 // TKE_TOP_TIMER_TMR14_TMRCR_0
#define TKE_TOP_TIMER_TMR140_LAST_REG 0xf000c // TKE_TOP_TIMER_TMR14_TMRATR_0
#define TKE_TOP_TIMER_TMR150_FIRST_REG 0x100000 // TKE_TOP_TIMER_TMR15_TMRCR_0
#define TKE_TOP_TIMER_TMR150_LAST_REG 0x10000c // TKE_TOP_TIMER_TMR15_TMRATR_0
#define TKE_TOP_WDT00_FIRST_REG 0x110000 // TKE_TOP_WDT0_WDTCR_0
#define TKE_TOP_WDT00_LAST_REG 0x110014 // TKE_TOP_WDT0_WDTFWCR_0
#define TKE_TOP_WDT10_FIRST_REG 0x120000 // TKE_TOP_WDT1_WDTCR_0
#define TKE_TOP_WDT10_LAST_REG 0x120014 // TKE_TOP_WDT1_WDTFWCR_0
#define TKE_TOP_WDT20_FIRST_REG 0x130000 // TKE_TOP_WDT2_WDTCR_0
#define TKE_TOP_WDT20_LAST_REG 0x130014 // TKE_TOP_WDT2_WDTFWCR_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARTKE_TOP_H_INC
