/*
 * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */
#ifndef AST_DEFS_H
#define AST_DEFS_H
#define FSP__SOC_COMMON__AST_DEFS_H     1

/* Compiler headers */

/* Early FSP headers */

/* Hardware headers */

/* Late FSP headers */

/* Module-specific FSP headers */

/**
 * @brief Number of regions each AST provides
 */
#define AST_NUM_REGIONS         8U

static inline uint32_t
tegra_ast_get_num_regions(void)
{
    return AST_NUM_REGIONS;
}

/**
 * @brief Slave base of the DM region that contains the enable bit
 *
 * Not implemented on this SoC.  The value isn't important because
 * it's only here to allow for compilation.  It will never be used
 * at run-time.
 */
#define AST_DM_REGION_SLAVE_BASE_LO     0U

#endif
