/*
 * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION &
 * AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */

/* Compiler headers */

/* Early FSP headers */
#include <soc-common/hw-const.h>        /* Must appear before any hwinc files */

/* Hardware headers */
#include <araps_vic.h>

/* Late FSP headers */
#include <hw-config/vic-irqs.h>

/* Module-specific FSP headers */
#include <vic/vic-asm.h>

	.section	SECTION_STR_VIC_TEXT, "ax"
	.arm
	.syntax		unified
/*
 * Code to handle the end of interrupt processing.
 *
 * Defines the vic0_isr_end and vic1_isr_end functions
 */
	ACK_VIC0_IRQ	vic0_isr_end
	rtosIRQ_EXIT

	ACK_VIC1_IRQ	vic1_isr_end
	rtosIRQ_EXIT

.if MAX_VIC_CONTROLLER == 4
	ACK_VIC2_IRQ	vic2_isr_end
	rtosIRQ_EXIT

	ACK_VIC3_IRQ	vic3_isr_end
	rtosIRQ_EXIT
.endif
