/*
 * Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
 *
 * NVIDIA CORPORATION and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA CORPORATION is strictly prohibited.
 */

/* Compiler headers */
#include <stdbool.h>                      // for false, true, bool
#include <stddef.h>                       // for NULL
#include <stdint.h>                       // for uint32_t, uint8_t, UINT32_C

/* Early FSP headers */
#include <misc/ct-assert.h>               // for CT_ASSERT

/* Hardware headers */

/* Late FSP headers */
#include <error/common-errors.h>          // for E_SUCCESS, E_INVALID_PARAM,...
#include <misc/attributes.h>              // for UNUSED
#include <misc/macros.h>                  // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD

/* Module-specific FSP headers */
#include <i2c/i2c-errors.h>               // for E_I2C_IO, E_I2C_ARB_LOST
#include <i2c/i2c-tegra.h>                // for i2c_tegra_handle, i2c_xfer_msg
#include <i2c/i2c.h>                      // for I2C_BUS_BUSY, I2C_SCL_BUSY
#include <soc-common/i2c-dependencies.h>  // for appfw_udelay, appfw_timer_c...
#include <i2c/i2c-tegra-async.h>

/*
 * Compile-time check for FSP header files
 *   Each FSP header file contains a signature unique to that file, and the
 *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
 *   check for this signature.  If it does not exist, then the build will
 *   abort.
 *
 *   This is a trap for projects which have their own include files of the
 *   same names, but different contents.  This trap ensures that only the
 *   files from the FSP project, are built into the FSP source code.
 */
START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
CT_ASSERT(FSP__I2C__I2C_ERRORS_H, "Header file missing or invalid.")
CT_ASSERT(FSP__I2C__I2C_TEGRA_H, "Header file missing or invalid.")
CT_ASSERT(FSP__I2C__I2C_H, "Header file missing or invalid.")
CT_ASSERT(FSP__I2C__I2C_TEGRA_ASYNC_H, "Header file missing or invalid.")
CT_ASSERT(FSP__SOC_COMMON__I2C_DEPENDENCIES_H, "Header file missing or invalid.")
END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")

/* Custom Defines */

/* Struct Definitions and Declarations */

/* API definitions */
error_t tegra_i2c_start_async_xfer(struct i2c_tegra_handle *hi2c_tegra,
                        struct i2c_xfer_msg *msgs, uint32_t num_msgs,
                        void *client_data, i2c_async_callback async_xfer_cb)
{
    uint32_t i;
    error_t ret;
    const struct i2c_xfer_msg *this;
    const struct i2c_xfer_msg *next;

    ret = tegra_i2c_acquire(hi2c_tegra);
    if (ret != E_SUCCESS) {
        goto out;
    }

    ret = tegra_i2c_check_state(hi2c_tegra);
    if (ret != E_SUCCESS) {
        /* Assuming the worst possible scenario in the previous transfer */
        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
        UNUSED((tegra_i2c_hw_init(hi2c_tegra)));
        goto release;
    }

    ret = tegra_i2c_validate_msgs(msgs, num_msgs);
    if (ret < 0) {
        goto release;
    }

    /* Default transfer variables */
    hi2c_tegra->is_async_xfer = true;
    hi2c_tegra->async_xfer_cb = async_xfer_cb;
    hi2c_tegra->client_data = client_data;
    hi2c_tegra->xfer_status = I2C_XFER_REQUESTED;
    hi2c_tegra->msgs = msgs;
    hi2c_tegra->bytes_to_xfer = msgs[0].buf_len;
    hi2c_tegra->msg_index = 0;

    for (i = 0U; i < num_msgs; i++) {
        this = &msgs[i];
        next = ((i + 1U) < num_msgs) ? &msgs[i + 1U] : NULL;

        /*
         * Ignoring the wait time return as the async transfer does not need to
         * wait for intterupt.
         */
        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
        UNUSED(tegra_i2c_xfer_one_msg(hi2c_tegra, this, next));
    }

    hi2c_tegra->xfer_status = I2C_XFER_STARTED;

release:
    /* Clk needs to be enabled throughout the xfer */
    if (ret != E_SUCCESS) {
        /* Above failure reasons take priority than release return */
        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
        UNUSED(tegra_i2c_release(hi2c_tegra));
    }

out:
    return ret;
}

error_t tegra_i2c_finish_async_xfer(const struct i2c_tegra_handle *hi2c_tegra,
                                        error_t xfer_ret)
{
    error_t ret = E_SUCCESS;
    error_t tmp = E_SUCCESS;

    /* Skip handling for ARB lost */
    if ((xfer_ret != E_SUCCESS) && ((xfer_ret != E_I2C_ARB_LOST))) {
        ret = tegra_i2c_hw_init(hi2c_tegra);
    }

    tmp = tegra_i2c_release(hi2c_tegra);
    if (ret == E_SUCCESS) {
        ret = tmp;
    }

    return ret;
}

uint32_t tegra_i2c_get_xfer_state(const struct i2c_tegra_handle *hi2c_tegra,
                                    uint32_t *msgs_xfered)
{
    *msgs_xfered = hi2c_tegra->msg_index;
    return hi2c_tegra->xfer_status;
}
END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
