/*
 * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *  * Neither the name of NVIDIA CORPORATION nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */


#ifndef ARCLK_RST_H
#define ARCLK_RST_H

#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0                                          MK_ADDR_CONST(0xb40004)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_ENABLE                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0                                      MK_ADDR_CONST(0xb41004)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_LSB                MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_ENABLE             MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0                                           MK_ADDR_CONST(0xb43000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_ENABLE                 MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_LSB                    MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0                                          MK_ADDR_CONST(0xb40008)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_MSB                         MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_MSB                         MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0                                                MK_ADDR_CONST(0xbe0000)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0                                              MK_ADDR_CONST(0xbe0008)
#define CLK_RST_CONTROLLER_PLLP_BASE_0                                                  MK_ADDR_CONST(0x7000c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_pllAON_out      MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_LSB             MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_PLLP_OUT0       MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_OSC_UNDIV       MK_ENUM_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_CLK_S           MK_ENUM_CONST(6)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0                          MK_ADDR_CONST(0xc30060)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0                   MK_ADDR_CONST(0xc30064)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0                    MK_ADDR_CONST(0xc30068)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0                       MK_ADDR_CONST(0xc3006c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0                    MK_ADDR_CONST(0xc30070)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0                       MK_ADDR_CONST(0xc30074)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0                 MK_ADDR_CONST(0xc30078)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0                    MK_ADDR_CONST(0xc3007c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0                              MK_ADDR_CONST(0xc300a0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0                       MK_ADDR_CONST(0xc300a4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0                        MK_ADDR_CONST(0xc300a8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0                           MK_ADDR_CONST(0xc300ac)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0                        MK_ADDR_CONST(0xc300b0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0                           MK_ADDR_CONST(0xc300b4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0                     MK_ADDR_CONST(0xc300b8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0                        MK_ADDR_CONST(0xc300bc)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0                                     MK_ADDR_CONST(0xb03000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0                                         MK_ADDR_CONST(0xb32000)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_LSB                                MK_SHIFT_CONST(20)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_MSB                                MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_LSB                              MK_SHIFT_CONST(16)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_MSB                              MK_SHIFT_CONST(23)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_LSB                                MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_LSB                                MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_MSB                                MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_LSB                         MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_MSB                         MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_OSC_CTRL_0                                                   MK_ADDR_CONST(0xbf0000)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_LSB                                      MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_MSB                                      MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC12                                    MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC13                                    MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC16P8                                  MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC19P2                                  MK_ENUM_CONST(4)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC26                                    MK_ENUM_CONST(12)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC38P4                                  MK_ENUM_CONST(5)
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC48                                    MK_ENUM_CONST(9)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_MSB         MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_LSB         MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0                                   MK_ADDR_CONST(0xc300c0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_LSB                MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_MSB                MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_MSB              MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_LSB              MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_MSB                MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_LSB                MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_SHIFT                         MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_SHIFT                              MK_SHIFT_CONST(26)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_MSB                              MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_LSB                              MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_DISABLE                          MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_MSB                              MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_LSB                              MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_ON                               MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_MSB                              MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_LSB                              MK_SHIFT_CONST(27)
#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_OFF                              MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_MSB                              MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_LSB                              MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_ENABLE                           MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_PLLP_OUT0               MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_pllAON_out              MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_OSC_UNDIV               MK_ENUM_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_MSB             MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_LSB                                MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_MSB                                MK_SHIFT_CONST(17)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0                                     MK_ADDR_CONST(0xc30080)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_SHIFT       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_FIELD       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_SHIFT     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_FIELD     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_MSB         MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_LSB         MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_MSB       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_LSB       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0                              MK_ADDR_CONST(0xc30084)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0                                  MK_ADDR_CONST(0xc3008c)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0                               MK_ADDR_CONST(0xc30090)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0                                  MK_ADDR_CONST(0xc30094)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0                               MK_ADDR_CONST(0xc30088)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0                            MK_ADDR_CONST(0xc30098)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0                               MK_ADDR_CONST(0xc3009c)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT       MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_FIELD       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_FIELD     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_MSB         MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_LSB         MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_MSB       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_LSB       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT         MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_FIELD         MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_FIELD       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_MSB           MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_MSB           MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_MSB         MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_LSB         MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_SHIFT               MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_FIELD               MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_SHIFT             MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_FIELD             MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_MSB               MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_LSB               MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT         MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_FIELD         MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT         MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_FIELD         MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_MSB           MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_LSB           MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_MSB         MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_LSB         MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_SHIFT               MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_FIELD               MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_SHIFT             MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_FIELD             MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_MSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_MSB               MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_LSB               MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT   MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_FIELD   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_FIELD MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_MSB     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_LSB     MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_MSB   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_SHIFT         MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_FIELD         MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_SHIFT       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_FIELD       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_MSB           MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_LSB           MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_LSB           MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_MSB         MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_LSB         MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_LSB           MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_FIELD       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT)
#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_LSB   MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0                                              MK_ADDR_CONST(0xbe0004)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_MSB                             MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_LSB                             MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0                                              MK_ADDR_CONST(0xbe0014)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_MSB                          MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_LSB                          MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_MSB                            MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_LSB                            MK_SHIFT_CONST(28)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_MSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_LSB                   MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_MSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_LSB                     MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0                                              MK_ADDR_CONST(0xc300c4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0                                          MK_ADDR_CONST(0x1c1000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0                                           MK_ADDR_CONST(0x1c3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0                                              MK_ADDR_CONST(0x1c0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0                                          MK_ADDR_CONST(0x1d1000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0                                           MK_ADDR_CONST(0x1d3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0                                              MK_ADDR_CONST(0x1d0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0                                          MK_ADDR_CONST(0xb41000)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0                                              MK_ADDR_CONST(0xb40000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0                                          MK_ADDR_CONST(0x9e1000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0                                           MK_ADDR_CONST(0x9e3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0                                              MK_ADDR_CONST(0x9e0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0                                          MK_ADDR_CONST(0xb51000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0                                           MK_ADDR_CONST(0xb53000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0                                              MK_ADDR_CONST(0xb50000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0                                          MK_ADDR_CONST(0x1281000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0                                           MK_ADDR_CONST(0x1283000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0                                              MK_ADDR_CONST(0x1280000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0                                   MK_ADDR_CONST(0xba0000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0                                    MK_ADDR_CONST(0xba2000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_LSB       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_MSB       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_PLLP_OUT0     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_LSB           MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0                                       MK_ADDR_CONST(0x390000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0                                        MK_ADDR_CONST(0x392000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_LSB               MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_MSB               MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_PLLP_OUT0             MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0                                           MK_ADDR_CONST(0x121000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0                                            MK_ADDR_CONST(0x123000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0                                               MK_ADDR_CONST(0x120000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0                                           MK_ADDR_CONST(0xb71000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0                                            MK_ADDR_CONST(0xb73000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0                                               MK_ADDR_CONST(0xb70000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0                                           MK_ADDR_CONST(0x241000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0                                            MK_ADDR_CONST(0x243000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0                                               MK_ADDR_CONST(0x240000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0                                           MK_ADDR_CONST(0xb81000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0                                            MK_ADDR_CONST(0xb83000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0                                               MK_ADDR_CONST(0xb80000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0                                          MK_ADDR_CONST(0xb91000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0                                           MK_ADDR_CONST(0xb93000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0                                              MK_ADDR_CONST(0xb90000)
#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0                                            MK_ADDR_CONST(0xb00030)
#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0                                            MK_ADDR_CONST(0xd00024)
#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0                                            MK_ADDR_CONST(0x1000024)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0                                          MK_ADDR_CONST(0xbc1000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0                                           MK_ADDR_CONST(0xbc3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0                                              MK_ADDR_CONST(0xbc0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0                                           MK_ADDR_CONST(0x141000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0                                            MK_ADDR_CONST(0x143000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0                                               MK_ADDR_CONST(0x140000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0                                           MK_ADDR_CONST(0xbb1000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0                                            MK_ADDR_CONST(0xbb3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0                                               MK_ADDR_CONST(0xbb0000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0                                           MK_ADDR_CONST(0x111000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0                                            MK_ADDR_CONST(0x113000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0                                               MK_ADDR_CONST(0x110000)
#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0                                               MK_ADDR_CONST(0xb10000)
#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0                                               MK_ADDR_CONST(0xb20000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTJ_0                                          MK_ADDR_CONST(0xc41000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0                                           MK_ADDR_CONST(0xc43000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0_UARTJ_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0_UARTJ_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0_UARTJ_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0_UARTJ_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0_UARTJ_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0_UARTJ_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_UARTJ_0                                              MK_ADDR_CONST(0xc40000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0                                           MK_ADDR_CONST(0x321000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0                                            MK_ADDR_CONST(0x323000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0                                               MK_ADDR_CONST(0x320000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0                                           MK_ADDR_CONST(0x531000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0                                            MK_ADDR_CONST(0x533000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0                                               MK_ADDR_CONST(0x530000)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0                                           MK_ADDR_CONST(0x8f1000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0                                            MK_ADDR_CONST(0x8f3000)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0                                               MK_ADDR_CONST(0x8f0000)
#define CLK_RST_CONTROLLER_RST_DEV_DCE_DMA_0                                            MK_ADDR_CONST(0x1700024)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_LSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_MSB                        MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_ENABLE                     MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_LSB                            MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_MSB                            MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_DISABLE                        MK_ENUM_CONST(0)

#endif /* ARCLK_RST_H */
