/*
 * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */

#ifndef CHIPID__CHIP_ID_H
#define CHIPID__CHIP_ID_H
#define FSP__CHIPID__CHIP_ID_H                          1

/* Compiler headers */
#include <stdint.h>
#include <stdbool.h>

/* Early FSP headers */

/* Hardware headers */

/* Late FSP headers */
#include <misc/macros.h>        // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD

START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
/* Module-specific FSP headers */

/**
 * @brief Defines for the Tegra Platform ID
 *
 * @macro-title Tegra Platform ID
 * @TEGRA_PLATFORM_ID_T186 Platform ID for Tegra T186
 * @TEGRA_PLATFORM_ID_T194 Platform ID for Tegra T194
 * @TEGRA_PLATFORM_ID_T234 Platform ID for Tegra T234
 * @TEGRA_PLATFORM_ID_T239 Platform ID for Tegra T239
 * @TEGRA_PLATFORM_ID_T264 Platform ID for Tegra T264
 */
#define TEGRA_PLATFORM_ID_T186 0x186
#define TEGRA_PLATFORM_ID_T194 0x194
#define TEGRA_PLATFORM_ID_T234 0x234
#define TEGRA_PLATFORM_ID_T239 0x239
#define TEGRA_PLATFORM_ID_T264 0x264

/**
 * @brief Defines for the Tegra CHIP ID
 *
 * @macro-title Tegra SOC Name
 * @TEGRA_SOC_NAME_T18X Chip ID for Tegra T18x
 * @TEGRA_SOC_NAME_T19X Chip ID for Tegra T19x
 * @TEGRA_SOC_NAME_T23X Chip ID for Tegra T23x
 * @TEGRA_SOC_NAME_T26X Chip ID for Tegra T26x
 */
#define TEGRA_SOC_NAME_T18X 0x18
#define TEGRA_SOC_NAME_T19X 0x19
#define TEGRA_SOC_NAME_T23X 0x23
#define TEGRA_SOC_NAME_T26X 0x26

/**
 * @brief Defines for the Tegra Major Revision number
 *
 * @macro-title Tegra Major Revision
 * @TEGRA_MAJOR_REVISION_A Tegra Chip Major Revision 'A'
 * @TEGRA_MAJOR_REVISION_B Tegra Chip Major Revision 'B'
 * @TEGRA_MAJOR_REVISION_C Tegra Chip Major Revision 'C'
 * @TEGRA_MAJOR_REVISION_D Tegra Chip Major Revision 'D'
 * @TEGRA_MAJOR_REVISION_E Tegra Chip Major Revision 'E'
 * @TEGRA_MAJOR_REVISION_F Tegra Chip Major Revision 'F'
 * @TEGRA_MAJOR_REVISION_G Tegra Chip Major Revision 'G'
 * @TEGRA_MAJOR_REVISION_H Tegra Chip Major Revision 'H'
 * @TEGRA_MAJOR_REVISION_I Tegra Chip Major Revision 'I'
 */
#define TEGRA_MAJOR_REVISION_A 0x1
#define TEGRA_MAJOR_REVISION_B 0x2
#define TEGRA_MAJOR_REVISION_C 0x3
#define TEGRA_MAJOR_REVISION_D 0x4
#define TEGRA_MAJOR_REVISION_E 0x5
#define TEGRA_MAJOR_REVISION_F 0x6
#define TEGRA_MAJOR_REVISION_G 0x7
#define TEGRA_MAJOR_REVISION_H 0x8
#define TEGRA_MAJOR_REVISION_I 0x9

/**
 * @brief Defines for the Tegra Minor Revision number
 *
 * @macro-title Tegra Minor Revision
 * @TEGRA_MINOR_REVISION_1 Tegra Chip Minor Revision number 1
 * @TEGRA_MINOR_REVISION_2 Tegra Chip Minor Revision number 2
 */
#define TEGRA_MINOR_REVISION_1 0x1
#define TEGRA_MINOR_REVISION_2 0x2

/**
 * @brief Defines for the Tegra Sub Revision
 *
 * @macro-title Tegra Sub Revision
 * @TEGRA_SUB_REVISION_P Tegra Chip Sub Revision 'P'
 * @TEGRA_SUB_REVISION_Q Tegra Chip Sub Revision 'Q'
 * @TEGRA_SUB_REVISION_R Tegra Chip Sub Revision 'R'
 */
#define TEGRA_SUB_REVISION_P 0x1
#define TEGRA_SUB_REVISION_Q 0x2
#define TEGRA_SUB_REVISION_R 0x3
#define TEGRA_SUB_NONE 0x0
END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")

/**
 * @brief Get the platforms id
 *
 * The api internally calls tegra_get_chipid and tegra_get_major_rev and returns
 * the actual platoform ID. +
 * Ex - for platform T239, +
 * tegra_get_chipid returns - 0x23 +
 * tegra_get_major_rev returns - 0x9 +
 * tegra_get_platform returns - 0x239
 *
 * @jama_func_req_id ?
 *
 * @retval 0x186 Tegra 186 platform
 * @retval 0x194 Tegra 194 platform
 * @retval 0x234 Tegra 234 platform
 * @retval 0x239 Tegra 239 platform
 * @retval 0x264 Tegra 264 platform
 */
uint16_t tegra_get_platform(void);

/**
 * @brief Get the Tegra chip family identifier
 *
 * @jama_func_req_id 8160164
 *
 * @retval TEGRA_SOC_NAME_T18X Tegra chip family identifier for T18X chips
 * @retval TEGRA_SOC_NAME_T19X Tegra chip family identifier for T19X chips
 * @retval TEGRA_SOC_NAME_T26X Tegra chip family identifier for T26X chips
 */
uint8_t tegra_get_chipid(void);

/**
 * @brief Get the chip major revision number
 *
 * @jama_func_req_id 8160170
 *
 * @retval TEGRA_MAJOR_REVISION_A Tegra chip major revision is A
 * @retval TEGRA_MAJOR_REVISION_B Tegra chip major revision is B
 */
uint8_t tegra_get_major_rev(void);

/**
 * @brief Get the minor revision number
 *
 * @jama_func_req_id 8161055
 *
 * @retval TEGRA_MINOR_REVISION_1 Tegra chip minor revision is 1
 * @retval TEGRA_MINOR_REVISION_2 Tegra chip minor revision is 2
 */
uint8_t tegra_get_minor_rev(void);

/**
 * @brief Check if running on actual silicon
 *
 * @jama_func_req_id 8161334
 *
 * @retval True If the API is called on Silicon
 * @retval False If the API is called on non-silicon platform
 */
bool tegra_platform_is_silicon(void);

/**
 * @brief Check if running on fpga
 *
 * @jama_func_req_id 8161334
 *
 * @retval True If the API is called on fpga
 * @retval False If the API is called on silicon or simulation platform
 */
bool tegra_platform_is_fpga(void);

/**
 * @brief Check if running on vdk
 *
 * @jama_func_req_id 8161334
 *
 * @retval True If the API is called on VDK
 * @retval False If the API is called on silicon platform
 */
bool tegra_platform_is_vdk(void);

/**
 * @brief Get sub revision number
 *
 * @jama_func_req_id 8191178
 *
 * @retval TEGRA_SUB_REVISION_P Tegra chip sub revision is 1
 * @retval TEGRA_SUB_REVISION_Q Tegra chip sub revision is 2
 * @retval TEGRA_SUB_REVISION_R Tegra chip sub revision is 3
 * @retval TEGRA_NO_SUB_REVISION Tegra chip with no sub revision
 */
uint8_t tegra_get_sub_rev(void);

/**
 * @brief Get tegra chip sku
 *
 * @jama_func_req_id 8247959
 *
 * @retval >0 Tegra chip SKU ID
 */
uint8_t tegra_get_sku_id(void);

/**
 * @brief Read fuse register
 *
 * @param[in] offset The register offset from the FUSE base
 * @param[out] val   Value read from register.
 *
 * @retval true for read success else false
 */
bool tegra_fuse_control_read(uint32_t offset, uint32_t *val);

#endif
