//
// Copyright (c) 2023 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARSPI_H_INC
#define ARSPI_H_INC
#define NV_MOBILE_ARSPI_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARSPI_H_SCRREG_NOMENCLATURE INFERRED

// Register SPI_COMMAND_0
#define SPI_COMMAND_0                   MK_ADDR_CONST(0x0)
#define SPI_COMMAND_0_SECURE                    0x0
#define SPI_COMMAND_0_DUAL                      0x0
#define SPI_COMMAND_0_SCR                       0
#define SPI_COMMAND_0_SCRREG                    0
#define SPI_COMMAND_0_WORD_COUNT                        0x1
#define SPI_COMMAND_0_RESET_VAL                         MK_MASK_CONST(0x43d00000)
#define SPI_COMMAND_0_RESET_MASK                        MK_MASK_CONST(0xfffff87f)
#define SPI_COMMAND_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_READ_MASK                         MK_MASK_CONST(0xfffff87f)
#define SPI_COMMAND_0_WRITE_MASK                        MK_MASK_CONST(0xfffff87f)
#define SPI_COMMAND_0_PIO_SHIFT                 MK_SHIFT_CONST(31)
#define SPI_COMMAND_0_PIO_FIELD                 MK_FIELD_CONST(0x1, SPI_COMMAND_0_PIO_SHIFT)
#define SPI_COMMAND_0_PIO_RANGE                 31:31
#define SPI_COMMAND_0_PIO_MSB                   MK_SHIFT_CONST(31)
#define SPI_COMMAND_0_PIO_LSB                   MK_SHIFT_CONST(31)
#define SPI_COMMAND_0_PIO_WOFFSET                       0x0
#define SPI_COMMAND_0_PIO_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_PIO_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_PIO_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_PIO_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_PIO_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_PIO_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_PIO_STOP                  MK_ENUM_CONST(0)
#define SPI_COMMAND_0_PIO_PIO                   MK_ENUM_CONST(1)

#define SPI_COMMAND_0_M_S_SHIFT                 MK_SHIFT_CONST(30)
#define SPI_COMMAND_0_M_S_FIELD                 MK_FIELD_CONST(0x1, SPI_COMMAND_0_M_S_SHIFT)
#define SPI_COMMAND_0_M_S_RANGE                 30:30
#define SPI_COMMAND_0_M_S_MSB                   MK_SHIFT_CONST(30)
#define SPI_COMMAND_0_M_S_LSB                   MK_SHIFT_CONST(30)
#define SPI_COMMAND_0_M_S_WOFFSET                       0x0
#define SPI_COMMAND_0_M_S_DEFAULT                       MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_M_S_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_M_S_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_M_S_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_M_S_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_M_S_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_M_S_SLAVE                 MK_ENUM_CONST(0)
#define SPI_COMMAND_0_M_S_MASTER                        MK_ENUM_CONST(1)

#define SPI_COMMAND_0_MODE_SHIFT                        MK_SHIFT_CONST(28)
#define SPI_COMMAND_0_MODE_FIELD                        MK_FIELD_CONST(0x3, SPI_COMMAND_0_MODE_SHIFT)
#define SPI_COMMAND_0_MODE_RANGE                        29:28
#define SPI_COMMAND_0_MODE_MSB                  MK_SHIFT_CONST(29)
#define SPI_COMMAND_0_MODE_LSB                  MK_SHIFT_CONST(28)
#define SPI_COMMAND_0_MODE_WOFFSET                      0x0
#define SPI_COMMAND_0_MODE_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define SPI_COMMAND_0_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_MODE_Mode0                        MK_ENUM_CONST(0)
#define SPI_COMMAND_0_MODE_Mode1                        MK_ENUM_CONST(1)
#define SPI_COMMAND_0_MODE_Mode2                        MK_ENUM_CONST(2)
#define SPI_COMMAND_0_MODE_Mode3                        MK_ENUM_CONST(3)

#define SPI_COMMAND_0_CS_SEL_SHIFT                      MK_SHIFT_CONST(26)
#define SPI_COMMAND_0_CS_SEL_FIELD                      MK_FIELD_CONST(0x3, SPI_COMMAND_0_CS_SEL_SHIFT)
#define SPI_COMMAND_0_CS_SEL_RANGE                      27:26
#define SPI_COMMAND_0_CS_SEL_MSB                        MK_SHIFT_CONST(27)
#define SPI_COMMAND_0_CS_SEL_LSB                        MK_SHIFT_CONST(26)
#define SPI_COMMAND_0_CS_SEL_WOFFSET                    0x0
#define SPI_COMMAND_0_CS_SEL_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define SPI_COMMAND_0_CS_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_SEL_CS0                        MK_ENUM_CONST(0)
#define SPI_COMMAND_0_CS_SEL_CS1                        MK_ENUM_CONST(1)
#define SPI_COMMAND_0_CS_SEL_CS2                        MK_ENUM_CONST(2)
#define SPI_COMMAND_0_CS_SEL_CS3                        MK_ENUM_CONST(3)

#define SPI_COMMAND_0_CS_POL_INACTIVE3_SHIFT                    MK_SHIFT_CONST(25)
#define SPI_COMMAND_0_CS_POL_INACTIVE3_FIELD                    MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_POL_INACTIVE3_SHIFT)
#define SPI_COMMAND_0_CS_POL_INACTIVE3_RANGE                    25:25
#define SPI_COMMAND_0_CS_POL_INACTIVE3_MSB                      MK_SHIFT_CONST(25)
#define SPI_COMMAND_0_CS_POL_INACTIVE3_LSB                      MK_SHIFT_CONST(25)
#define SPI_COMMAND_0_CS_POL_INACTIVE3_WOFFSET                  0x0
#define SPI_COMMAND_0_CS_POL_INACTIVE3_DEFAULT                  MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_POL_INACTIVE3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_POL_INACTIVE3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_POL_INACTIVE3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_POL_INACTIVE3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_POL_INACTIVE3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_POL_INACTIVE3_LOW                      MK_ENUM_CONST(0)
#define SPI_COMMAND_0_CS_POL_INACTIVE3_HIGH                     MK_ENUM_CONST(1)

#define SPI_COMMAND_0_CS_POL_INACTIVE2_SHIFT                    MK_SHIFT_CONST(24)
#define SPI_COMMAND_0_CS_POL_INACTIVE2_FIELD                    MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_POL_INACTIVE2_SHIFT)
#define SPI_COMMAND_0_CS_POL_INACTIVE2_RANGE                    24:24
#define SPI_COMMAND_0_CS_POL_INACTIVE2_MSB                      MK_SHIFT_CONST(24)
#define SPI_COMMAND_0_CS_POL_INACTIVE2_LSB                      MK_SHIFT_CONST(24)
#define SPI_COMMAND_0_CS_POL_INACTIVE2_WOFFSET                  0x0
#define SPI_COMMAND_0_CS_POL_INACTIVE2_DEFAULT                  MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_POL_INACTIVE2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_POL_INACTIVE2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_POL_INACTIVE2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_POL_INACTIVE2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_POL_INACTIVE2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_POL_INACTIVE2_LOW                      MK_ENUM_CONST(0)
#define SPI_COMMAND_0_CS_POL_INACTIVE2_HIGH                     MK_ENUM_CONST(1)

#define SPI_COMMAND_0_CS_POL_INACTIVE1_SHIFT                    MK_SHIFT_CONST(23)
#define SPI_COMMAND_0_CS_POL_INACTIVE1_FIELD                    MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_POL_INACTIVE1_SHIFT)
#define SPI_COMMAND_0_CS_POL_INACTIVE1_RANGE                    23:23
#define SPI_COMMAND_0_CS_POL_INACTIVE1_MSB                      MK_SHIFT_CONST(23)
#define SPI_COMMAND_0_CS_POL_INACTIVE1_LSB                      MK_SHIFT_CONST(23)
#define SPI_COMMAND_0_CS_POL_INACTIVE1_WOFFSET                  0x0
#define SPI_COMMAND_0_CS_POL_INACTIVE1_DEFAULT                  MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_POL_INACTIVE1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_POL_INACTIVE1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_POL_INACTIVE1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_POL_INACTIVE1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_POL_INACTIVE1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_POL_INACTIVE1_LOW                      MK_ENUM_CONST(0)
#define SPI_COMMAND_0_CS_POL_INACTIVE1_HIGH                     MK_ENUM_CONST(1)

#define SPI_COMMAND_0_CS_POL_INACTIVE0_SHIFT                    MK_SHIFT_CONST(22)
#define SPI_COMMAND_0_CS_POL_INACTIVE0_FIELD                    MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_POL_INACTIVE0_SHIFT)
#define SPI_COMMAND_0_CS_POL_INACTIVE0_RANGE                    22:22
#define SPI_COMMAND_0_CS_POL_INACTIVE0_MSB                      MK_SHIFT_CONST(22)
#define SPI_COMMAND_0_CS_POL_INACTIVE0_LSB                      MK_SHIFT_CONST(22)
#define SPI_COMMAND_0_CS_POL_INACTIVE0_WOFFSET                  0x0
#define SPI_COMMAND_0_CS_POL_INACTIVE0_DEFAULT                  MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_POL_INACTIVE0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_POL_INACTIVE0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_POL_INACTIVE0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_POL_INACTIVE0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_POL_INACTIVE0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_POL_INACTIVE0_LOW                      MK_ENUM_CONST(0)
#define SPI_COMMAND_0_CS_POL_INACTIVE0_HIGH                     MK_ENUM_CONST(1)

#define SPI_COMMAND_0_CS_SW_HW_SHIFT                    MK_SHIFT_CONST(21)
#define SPI_COMMAND_0_CS_SW_HW_FIELD                    MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_SW_HW_SHIFT)
#define SPI_COMMAND_0_CS_SW_HW_RANGE                    21:21
#define SPI_COMMAND_0_CS_SW_HW_MSB                      MK_SHIFT_CONST(21)
#define SPI_COMMAND_0_CS_SW_HW_LSB                      MK_SHIFT_CONST(21)
#define SPI_COMMAND_0_CS_SW_HW_WOFFSET                  0x0
#define SPI_COMMAND_0_CS_SW_HW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_SW_HW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_SW_HW_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_SW_HW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_SW_HW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_SW_HW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_SW_HW_HARDWARE                 MK_ENUM_CONST(0)
#define SPI_COMMAND_0_CS_SW_HW_SOFTWARE                 MK_ENUM_CONST(1)

#define SPI_COMMAND_0_CS_SW_VAL_SHIFT                   MK_SHIFT_CONST(20)
#define SPI_COMMAND_0_CS_SW_VAL_FIELD                   MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_SW_VAL_SHIFT)
#define SPI_COMMAND_0_CS_SW_VAL_RANGE                   20:20
#define SPI_COMMAND_0_CS_SW_VAL_MSB                     MK_SHIFT_CONST(20)
#define SPI_COMMAND_0_CS_SW_VAL_LSB                     MK_SHIFT_CONST(20)
#define SPI_COMMAND_0_CS_SW_VAL_WOFFSET                 0x0
#define SPI_COMMAND_0_CS_SW_VAL_DEFAULT                 MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_SW_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_SW_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_SW_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_SW_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_SW_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_SW_VAL_LOW                     MK_ENUM_CONST(0)
#define SPI_COMMAND_0_CS_SW_VAL_HIGH                    MK_ENUM_CONST(1)

#define SPI_COMMAND_0_IDLE_SDA_SHIFT                    MK_SHIFT_CONST(18)
#define SPI_COMMAND_0_IDLE_SDA_FIELD                    MK_FIELD_CONST(0x3, SPI_COMMAND_0_IDLE_SDA_SHIFT)
#define SPI_COMMAND_0_IDLE_SDA_RANGE                    19:18
#define SPI_COMMAND_0_IDLE_SDA_MSB                      MK_SHIFT_CONST(19)
#define SPI_COMMAND_0_IDLE_SDA_LSB                      MK_SHIFT_CONST(18)
#define SPI_COMMAND_0_IDLE_SDA_WOFFSET                  0x0
#define SPI_COMMAND_0_IDLE_SDA_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_IDLE_SDA_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define SPI_COMMAND_0_IDLE_SDA_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_IDLE_SDA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_IDLE_SDA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_IDLE_SDA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_IDLE_SDA_DRIVE_LOW                        MK_ENUM_CONST(0)
#define SPI_COMMAND_0_IDLE_SDA_DRIVE_HIGH                       MK_ENUM_CONST(1)
#define SPI_COMMAND_0_IDLE_SDA_PULL_LOW                 MK_ENUM_CONST(2)
#define SPI_COMMAND_0_IDLE_SDA_PULL_HIGH                        MK_ENUM_CONST(3)

#define SPI_COMMAND_0_BIDIR_SHIFT                       MK_SHIFT_CONST(17)
#define SPI_COMMAND_0_BIDIR_FIELD                       MK_FIELD_CONST(0x1, SPI_COMMAND_0_BIDIR_SHIFT)
#define SPI_COMMAND_0_BIDIR_RANGE                       17:17
#define SPI_COMMAND_0_BIDIR_MSB                 MK_SHIFT_CONST(17)
#define SPI_COMMAND_0_BIDIR_LSB                 MK_SHIFT_CONST(17)
#define SPI_COMMAND_0_BIDIR_WOFFSET                     0x0
#define SPI_COMMAND_0_BIDIR_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BIDIR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_BIDIR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BIDIR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BIDIR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BIDIR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_BIDIR_NORMAL                      MK_ENUM_CONST(0)
#define SPI_COMMAND_0_BIDIR_BIDIR                       MK_ENUM_CONST(1)

#define SPI_COMMAND_0_En_LE_Bit_SHIFT                   MK_SHIFT_CONST(16)
#define SPI_COMMAND_0_En_LE_Bit_FIELD                   MK_FIELD_CONST(0x1, SPI_COMMAND_0_En_LE_Bit_SHIFT)
#define SPI_COMMAND_0_En_LE_Bit_RANGE                   16:16
#define SPI_COMMAND_0_En_LE_Bit_MSB                     MK_SHIFT_CONST(16)
#define SPI_COMMAND_0_En_LE_Bit_LSB                     MK_SHIFT_CONST(16)
#define SPI_COMMAND_0_En_LE_Bit_WOFFSET                 0x0
#define SPI_COMMAND_0_En_LE_Bit_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_En_LE_Bit_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_En_LE_Bit_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_En_LE_Bit_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_En_LE_Bit_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_En_LE_Bit_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_En_LE_Bit_LAST                    MK_ENUM_CONST(0)
#define SPI_COMMAND_0_En_LE_Bit_FIRST                   MK_ENUM_CONST(1)

#define SPI_COMMAND_0_En_LE_Byte_SHIFT                  MK_SHIFT_CONST(15)
#define SPI_COMMAND_0_En_LE_Byte_FIELD                  MK_FIELD_CONST(0x1, SPI_COMMAND_0_En_LE_Byte_SHIFT)
#define SPI_COMMAND_0_En_LE_Byte_RANGE                  15:15
#define SPI_COMMAND_0_En_LE_Byte_MSB                    MK_SHIFT_CONST(15)
#define SPI_COMMAND_0_En_LE_Byte_LSB                    MK_SHIFT_CONST(15)
#define SPI_COMMAND_0_En_LE_Byte_WOFFSET                        0x0
#define SPI_COMMAND_0_En_LE_Byte_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_En_LE_Byte_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_En_LE_Byte_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_En_LE_Byte_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_En_LE_Byte_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_En_LE_Byte_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_En_LE_Byte_LAST                   MK_ENUM_CONST(0)
#define SPI_COMMAND_0_En_LE_Byte_FIRST                  MK_ENUM_CONST(1)

#define SPI_COMMAND_0_BOTH_EN_BIT_SHIFT                 MK_SHIFT_CONST(14)
#define SPI_COMMAND_0_BOTH_EN_BIT_FIELD                 MK_FIELD_CONST(0x1, SPI_COMMAND_0_BOTH_EN_BIT_SHIFT)
#define SPI_COMMAND_0_BOTH_EN_BIT_RANGE                 14:14
#define SPI_COMMAND_0_BOTH_EN_BIT_MSB                   MK_SHIFT_CONST(14)
#define SPI_COMMAND_0_BOTH_EN_BIT_LSB                   MK_SHIFT_CONST(14)
#define SPI_COMMAND_0_BOTH_EN_BIT_WOFFSET                       0x0
#define SPI_COMMAND_0_BOTH_EN_BIT_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BOTH_EN_BIT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_BOTH_EN_BIT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BOTH_EN_BIT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BOTH_EN_BIT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BOTH_EN_BIT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_BOTH_EN_BIT_DISABLE                       MK_ENUM_CONST(0)
#define SPI_COMMAND_0_BOTH_EN_BIT_ENABLE                        MK_ENUM_CONST(1)

#define SPI_COMMAND_0_BOTH_EN_BYTE_SHIFT                        MK_SHIFT_CONST(13)
#define SPI_COMMAND_0_BOTH_EN_BYTE_FIELD                        MK_FIELD_CONST(0x1, SPI_COMMAND_0_BOTH_EN_BYTE_SHIFT)
#define SPI_COMMAND_0_BOTH_EN_BYTE_RANGE                        13:13
#define SPI_COMMAND_0_BOTH_EN_BYTE_MSB                  MK_SHIFT_CONST(13)
#define SPI_COMMAND_0_BOTH_EN_BYTE_LSB                  MK_SHIFT_CONST(13)
#define SPI_COMMAND_0_BOTH_EN_BYTE_WOFFSET                      0x0
#define SPI_COMMAND_0_BOTH_EN_BYTE_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BOTH_EN_BYTE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_BOTH_EN_BYTE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BOTH_EN_BYTE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BOTH_EN_BYTE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BOTH_EN_BYTE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_BOTH_EN_BYTE_DISABLE                      MK_ENUM_CONST(0)
#define SPI_COMMAND_0_BOTH_EN_BYTE_ENABLE                       MK_ENUM_CONST(1)

#define SPI_COMMAND_0_Rx_EN_SHIFT                       MK_SHIFT_CONST(12)
#define SPI_COMMAND_0_Rx_EN_FIELD                       MK_FIELD_CONST(0x1, SPI_COMMAND_0_Rx_EN_SHIFT)
#define SPI_COMMAND_0_Rx_EN_RANGE                       12:12
#define SPI_COMMAND_0_Rx_EN_MSB                 MK_SHIFT_CONST(12)
#define SPI_COMMAND_0_Rx_EN_LSB                 MK_SHIFT_CONST(12)
#define SPI_COMMAND_0_Rx_EN_WOFFSET                     0x0
#define SPI_COMMAND_0_Rx_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_Rx_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_Rx_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_Rx_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_Rx_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_Rx_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_Rx_EN_DISABLE                     MK_ENUM_CONST(0)
#define SPI_COMMAND_0_Rx_EN_ENABLE                      MK_ENUM_CONST(1)

#define SPI_COMMAND_0_Tx_EN_SHIFT                       MK_SHIFT_CONST(11)
#define SPI_COMMAND_0_Tx_EN_FIELD                       MK_FIELD_CONST(0x1, SPI_COMMAND_0_Tx_EN_SHIFT)
#define SPI_COMMAND_0_Tx_EN_RANGE                       11:11
#define SPI_COMMAND_0_Tx_EN_MSB                 MK_SHIFT_CONST(11)
#define SPI_COMMAND_0_Tx_EN_LSB                 MK_SHIFT_CONST(11)
#define SPI_COMMAND_0_Tx_EN_WOFFSET                     0x0
#define SPI_COMMAND_0_Tx_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_Tx_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_Tx_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_Tx_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_Tx_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_Tx_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_Tx_EN_DISABLE                     MK_ENUM_CONST(0)
#define SPI_COMMAND_0_Tx_EN_ENABLE                      MK_ENUM_CONST(1)

#define SPI_COMMAND_0_CS_GPIO_SHIFT                     MK_SHIFT_CONST(6)
#define SPI_COMMAND_0_CS_GPIO_FIELD                     MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_GPIO_SHIFT)
#define SPI_COMMAND_0_CS_GPIO_RANGE                     6:6
#define SPI_COMMAND_0_CS_GPIO_MSB                       MK_SHIFT_CONST(6)
#define SPI_COMMAND_0_CS_GPIO_LSB                       MK_SHIFT_CONST(6)
#define SPI_COMMAND_0_CS_GPIO_WOFFSET                   0x0
#define SPI_COMMAND_0_CS_GPIO_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_GPIO_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_GPIO_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_GPIO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_GPIO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_CS_GPIO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_CS_GPIO_DISABLE                   MK_ENUM_CONST(0)
#define SPI_COMMAND_0_CS_GPIO_ENABLE                    MK_ENUM_CONST(1)

#define SPI_COMMAND_0_PACKED_SHIFT                      MK_SHIFT_CONST(5)
#define SPI_COMMAND_0_PACKED_FIELD                      MK_FIELD_CONST(0x1, SPI_COMMAND_0_PACKED_SHIFT)
#define SPI_COMMAND_0_PACKED_RANGE                      5:5
#define SPI_COMMAND_0_PACKED_MSB                        MK_SHIFT_CONST(5)
#define SPI_COMMAND_0_PACKED_LSB                        MK_SHIFT_CONST(5)
#define SPI_COMMAND_0_PACKED_WOFFSET                    0x0
#define SPI_COMMAND_0_PACKED_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_PACKED_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_PACKED_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_PACKED_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_PACKED_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_PACKED_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define SPI_COMMAND_0_PACKED_DISABLE                    MK_ENUM_CONST(0)
#define SPI_COMMAND_0_PACKED_ENABLE                     MK_ENUM_CONST(1)

#define SPI_COMMAND_0_BIT_LENGTH_SHIFT                  MK_SHIFT_CONST(0)
#define SPI_COMMAND_0_BIT_LENGTH_FIELD                  MK_FIELD_CONST(0x1f, SPI_COMMAND_0_BIT_LENGTH_SHIFT)
#define SPI_COMMAND_0_BIT_LENGTH_RANGE                  4:0
#define SPI_COMMAND_0_BIT_LENGTH_MSB                    MK_SHIFT_CONST(4)
#define SPI_COMMAND_0_BIT_LENGTH_LSB                    MK_SHIFT_CONST(0)
#define SPI_COMMAND_0_BIT_LENGTH_WOFFSET                        0x0
#define SPI_COMMAND_0_BIT_LENGTH_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BIT_LENGTH_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
#define SPI_COMMAND_0_BIT_LENGTH_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BIT_LENGTH_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BIT_LENGTH_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define SPI_COMMAND_0_BIT_LENGTH_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

// Register SPI_COMMAND2_0
#define SPI_COMMAND2_0                  MK_ADDR_CONST(0x4)
#define SPI_COMMAND2_0_SECURE                   0x0
#define SPI_COMMAND2_0_DUAL                     0x0
#define SPI_COMMAND2_0_SCR                      0
#define SPI_COMMAND2_0_SCRREG                   0
#define SPI_COMMAND2_0_WORD_COUNT                       0x1
#define SPI_COMMAND2_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define SPI_COMMAND2_0_RESET_MASK                       MK_MASK_CONST(0xfff)
#define SPI_COMMAND2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define SPI_COMMAND2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define SPI_COMMAND2_0_READ_MASK                        MK_MASK_CONST(0xfff)
#define SPI_COMMAND2_0_WRITE_MASK                       MK_MASK_CONST(0xfff)
#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_SHIFT                   MK_SHIFT_CONST(6)
#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_FIELD                   MK_FIELD_CONST(0x3f, SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_SHIFT)
#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_RANGE                   11:6
#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_MSB                     MK_SHIFT_CONST(11)
#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_LSB                     MK_SHIFT_CONST(6)
#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_WOFFSET                 0x0
#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_SHIFT                   MK_SHIFT_CONST(0)
#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_FIELD                   MK_FIELD_CONST(0x3f, SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_SHIFT)
#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_RANGE                   5:0
#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_MSB                     MK_SHIFT_CONST(5)
#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_LSB                     MK_SHIFT_CONST(0)
#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_WOFFSET                 0x0
#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

// Register SPI_TIMING_REG1_0
#define SPI_TIMING_REG1_0                       MK_ADDR_CONST(0x8)
#define SPI_TIMING_REG1_0_SECURE                        0x0
#define SPI_TIMING_REG1_0_DUAL                  0x0
#define SPI_TIMING_REG1_0_SCR                   0
#define SPI_TIMING_REG1_0_SCRREG                        0
#define SPI_TIMING_REG1_0_WORD_COUNT                    0x1
#define SPI_TIMING_REG1_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define SPI_TIMING_REG1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define SPI_TIMING_REG1_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define SPI_TIMING_REG1_0_CS_SETUP_3_SHIFT                      MK_SHIFT_CONST(28)
#define SPI_TIMING_REG1_0_CS_SETUP_3_FIELD                      MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_SETUP_3_SHIFT)
#define SPI_TIMING_REG1_0_CS_SETUP_3_RANGE                      31:28
#define SPI_TIMING_REG1_0_CS_SETUP_3_MSB                        MK_SHIFT_CONST(31)
#define SPI_TIMING_REG1_0_CS_SETUP_3_LSB                        MK_SHIFT_CONST(28)
#define SPI_TIMING_REG1_0_CS_SETUP_3_WOFFSET                    0x0
#define SPI_TIMING_REG1_0_CS_SETUP_3_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_3_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define SPI_TIMING_REG1_0_CS_SETUP_3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define SPI_TIMING_REG1_0_CS_HOLD_3_SHIFT                       MK_SHIFT_CONST(24)
#define SPI_TIMING_REG1_0_CS_HOLD_3_FIELD                       MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_HOLD_3_SHIFT)
#define SPI_TIMING_REG1_0_CS_HOLD_3_RANGE                       27:24
#define SPI_TIMING_REG1_0_CS_HOLD_3_MSB                 MK_SHIFT_CONST(27)
#define SPI_TIMING_REG1_0_CS_HOLD_3_LSB                 MK_SHIFT_CONST(24)
#define SPI_TIMING_REG1_0_CS_HOLD_3_WOFFSET                     0x0
#define SPI_TIMING_REG1_0_CS_HOLD_3_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_3_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define SPI_TIMING_REG1_0_CS_HOLD_3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define SPI_TIMING_REG1_0_CS_SETUP_2_SHIFT                      MK_SHIFT_CONST(20)
#define SPI_TIMING_REG1_0_CS_SETUP_2_FIELD                      MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_SETUP_2_SHIFT)
#define SPI_TIMING_REG1_0_CS_SETUP_2_RANGE                      23:20
#define SPI_TIMING_REG1_0_CS_SETUP_2_MSB                        MK_SHIFT_CONST(23)
#define SPI_TIMING_REG1_0_CS_SETUP_2_LSB                        MK_SHIFT_CONST(20)
#define SPI_TIMING_REG1_0_CS_SETUP_2_WOFFSET                    0x0
#define SPI_TIMING_REG1_0_CS_SETUP_2_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_2_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define SPI_TIMING_REG1_0_CS_SETUP_2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define SPI_TIMING_REG1_0_CS_HOLD_2_SHIFT                       MK_SHIFT_CONST(16)
#define SPI_TIMING_REG1_0_CS_HOLD_2_FIELD                       MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_HOLD_2_SHIFT)
#define SPI_TIMING_REG1_0_CS_HOLD_2_RANGE                       19:16
#define SPI_TIMING_REG1_0_CS_HOLD_2_MSB                 MK_SHIFT_CONST(19)
#define SPI_TIMING_REG1_0_CS_HOLD_2_LSB                 MK_SHIFT_CONST(16)
#define SPI_TIMING_REG1_0_CS_HOLD_2_WOFFSET                     0x0
#define SPI_TIMING_REG1_0_CS_HOLD_2_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_2_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define SPI_TIMING_REG1_0_CS_HOLD_2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define SPI_TIMING_REG1_0_CS_SETUP_1_SHIFT                      MK_SHIFT_CONST(12)
#define SPI_TIMING_REG1_0_CS_SETUP_1_FIELD                      MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_SETUP_1_SHIFT)
#define SPI_TIMING_REG1_0_CS_SETUP_1_RANGE                      15:12
#define SPI_TIMING_REG1_0_CS_SETUP_1_MSB                        MK_SHIFT_CONST(15)
#define SPI_TIMING_REG1_0_CS_SETUP_1_LSB                        MK_SHIFT_CONST(12)
#define SPI_TIMING_REG1_0_CS_SETUP_1_WOFFSET                    0x0
#define SPI_TIMING_REG1_0_CS_SETUP_1_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_1_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define SPI_TIMING_REG1_0_CS_SETUP_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define SPI_TIMING_REG1_0_CS_HOLD_1_SHIFT                       MK_SHIFT_CONST(8)
#define SPI_TIMING_REG1_0_CS_HOLD_1_FIELD                       MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_HOLD_1_SHIFT)
#define SPI_TIMING_REG1_0_CS_HOLD_1_RANGE                       11:8
#define SPI_TIMING_REG1_0_CS_HOLD_1_MSB                 MK_SHIFT_CONST(11)
#define SPI_TIMING_REG1_0_CS_HOLD_1_LSB                 MK_SHIFT_CONST(8)
#define SPI_TIMING_REG1_0_CS_HOLD_1_WOFFSET                     0x0
#define SPI_TIMING_REG1_0_CS_HOLD_1_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_1_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define SPI_TIMING_REG1_0_CS_HOLD_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define SPI_TIMING_REG1_0_CS_SETUP_0_SHIFT                      MK_SHIFT_CONST(4)
#define SPI_TIMING_REG1_0_CS_SETUP_0_FIELD                      MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_SETUP_0_SHIFT)
#define SPI_TIMING_REG1_0_CS_SETUP_0_RANGE                      7:4
#define SPI_TIMING_REG1_0_CS_SETUP_0_MSB                        MK_SHIFT_CONST(7)
#define SPI_TIMING_REG1_0_CS_SETUP_0_LSB                        MK_SHIFT_CONST(4)
#define SPI_TIMING_REG1_0_CS_SETUP_0_WOFFSET                    0x0
#define SPI_TIMING_REG1_0_CS_SETUP_0_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_0_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define SPI_TIMING_REG1_0_CS_SETUP_0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_SETUP_0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define SPI_TIMING_REG1_0_CS_HOLD_0_SHIFT                       MK_SHIFT_CONST(0)
#define SPI_TIMING_REG1_0_CS_HOLD_0_FIELD                       MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_HOLD_0_SHIFT)
#define SPI_TIMING_REG1_0_CS_HOLD_0_RANGE                       3:0
#define SPI_TIMING_REG1_0_CS_HOLD_0_MSB                 MK_SHIFT_CONST(3)
#define SPI_TIMING_REG1_0_CS_HOLD_0_LSB                 MK_SHIFT_CONST(0)
#define SPI_TIMING_REG1_0_CS_HOLD_0_WOFFSET                     0x0
#define SPI_TIMING_REG1_0_CS_HOLD_0_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_0_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define SPI_TIMING_REG1_0_CS_HOLD_0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define SPI_TIMING_REG1_0_CS_HOLD_0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

// Register SPI_TIMING_REG2_0
#define SPI_TIMING_REG2_0                       MK_ADDR_CONST(0xc)
#define SPI_TIMING_REG2_0_SECURE                        0x0
#define SPI_TIMING_REG2_0_DUAL                  0x0
#define SPI_TIMING_REG2_0_SCR                   0
#define SPI_TIMING_REG2_0_SCRREG                        0
#define SPI_TIMING_REG2_0_WORD_COUNT                    0x1
#define SPI_TIMING_REG2_0_RESET_VAL                     MK_MASK_CONST(0x20202020)
#define SPI_TIMING_REG2_0_RESET_MASK                    MK_MASK_CONST(0x3f3f3f3f)
#define SPI_TIMING_REG2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_READ_MASK                     MK_MASK_CONST(0x3f3f3f3f)
#define SPI_TIMING_REG2_0_WRITE_MASK                    MK_MASK_CONST(0x3f3f3f3f)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_SHIFT                     MK_SHIFT_CONST(29)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_FIELD                     MK_FIELD_CONST(0x1, SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_SHIFT)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_RANGE                     29:29
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_MSB                       MK_SHIFT_CONST(29)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_LSB                       MK_SHIFT_CONST(29)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_WOFFSET                   0x0
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_DEFAULT                   MK_MASK_CONST(0x1)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_SHIFT                        MK_SHIFT_CONST(24)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_FIELD                        MK_FIELD_CONST(0x1f, SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_SHIFT)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_RANGE                        28:24
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_MSB                  MK_SHIFT_CONST(28)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_LSB                  MK_SHIFT_CONST(24)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_WOFFSET                      0x0
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_SHIFT                     MK_SHIFT_CONST(21)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_FIELD                     MK_FIELD_CONST(0x1, SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_SHIFT)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_RANGE                     21:21
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_MSB                       MK_SHIFT_CONST(21)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_LSB                       MK_SHIFT_CONST(21)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_WOFFSET                   0x0
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_DEFAULT                   MK_MASK_CONST(0x1)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_SHIFT                        MK_SHIFT_CONST(16)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_FIELD                        MK_FIELD_CONST(0x1f, SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_SHIFT)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_RANGE                        20:16
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_MSB                  MK_SHIFT_CONST(20)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_LSB                  MK_SHIFT_CONST(16)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_WOFFSET                      0x0
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_SHIFT                     MK_SHIFT_CONST(13)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_FIELD                     MK_FIELD_CONST(0x1, SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_SHIFT)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_RANGE                     13:13
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_MSB                       MK_SHIFT_CONST(13)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_LSB                       MK_SHIFT_CONST(13)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_WOFFSET                   0x0
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_DEFAULT                   MK_MASK_CONST(0x1)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_SHIFT                        MK_SHIFT_CONST(8)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_FIELD                        MK_FIELD_CONST(0x1f, SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_SHIFT)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_RANGE                        12:8
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_MSB                  MK_SHIFT_CONST(12)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_LSB                  MK_SHIFT_CONST(8)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_WOFFSET                      0x0
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_SHIFT                     MK_SHIFT_CONST(5)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_FIELD                     MK_FIELD_CONST(0x1, SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_SHIFT)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_RANGE                     5:5
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_MSB                       MK_SHIFT_CONST(5)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_LSB                       MK_SHIFT_CONST(5)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_WOFFSET                   0x0
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_DEFAULT                   MK_MASK_CONST(0x1)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_SHIFT                        MK_SHIFT_CONST(0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_FIELD                        MK_FIELD_CONST(0x1f, SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_SHIFT)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_RANGE                        4:0
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_MSB                  MK_SHIFT_CONST(4)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_LSB                  MK_SHIFT_CONST(0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_WOFFSET                      0x0
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

// Register SPI_TRANSFER_STATUS_0
#define SPI_TRANSFER_STATUS_0                   MK_ADDR_CONST(0x10)
#define SPI_TRANSFER_STATUS_0_SECURE                    0x0
#define SPI_TRANSFER_STATUS_0_DUAL                      0x0
#define SPI_TRANSFER_STATUS_0_SCR                       0
#define SPI_TRANSFER_STATUS_0_SCRREG                    0
#define SPI_TRANSFER_STATUS_0_WORD_COUNT                        0x1
#define SPI_TRANSFER_STATUS_0_RESET_VAL                         MK_MASK_CONST(0xff0000)
#define SPI_TRANSFER_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x40ffffff)
#define SPI_TRANSFER_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define SPI_TRANSFER_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_TRANSFER_STATUS_0_READ_MASK                         MK_MASK_CONST(0x40ffffff)
#define SPI_TRANSFER_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x40ff0000)
#define SPI_TRANSFER_STATUS_0_RDY_SHIFT                 MK_SHIFT_CONST(30)
#define SPI_TRANSFER_STATUS_0_RDY_FIELD                 MK_FIELD_CONST(0x1, SPI_TRANSFER_STATUS_0_RDY_SHIFT)
#define SPI_TRANSFER_STATUS_0_RDY_RANGE                 30:30
#define SPI_TRANSFER_STATUS_0_RDY_MSB                   MK_SHIFT_CONST(30)
#define SPI_TRANSFER_STATUS_0_RDY_LSB                   MK_SHIFT_CONST(30)
#define SPI_TRANSFER_STATUS_0_RDY_WOFFSET                       0x0
#define SPI_TRANSFER_STATUS_0_RDY_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_TRANSFER_STATUS_0_RDY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define SPI_TRANSFER_STATUS_0_RDY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_TRANSFER_STATUS_0_RDY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define SPI_TRANSFER_STATUS_0_RDY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define SPI_TRANSFER_STATUS_0_RDY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define SPI_TRANSFER_STATUS_0_RDY_NOT_READY                     MK_ENUM_CONST(0)
#define SPI_TRANSFER_STATUS_0_RDY_READY                 MK_ENUM_CONST(1)

#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_SHIFT                        MK_SHIFT_CONST(16)
#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_FIELD                        MK_FIELD_CONST(0xff, SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_SHIFT)
#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_RANGE                        23:16
#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_MSB                  MK_SHIFT_CONST(23)
#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_LSB                  MK_SHIFT_CONST(16)
#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_WOFFSET                      0x0
#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_DEFAULT                      MK_MASK_CONST(0xff)
#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define SPI_TRANSFER_STATUS_0_BLK_CNT_SHIFT                     MK_SHIFT_CONST(0)
#define SPI_TRANSFER_STATUS_0_BLK_CNT_FIELD                     MK_FIELD_CONST(0xffff, SPI_TRANSFER_STATUS_0_BLK_CNT_SHIFT)
#define SPI_TRANSFER_STATUS_0_BLK_CNT_RANGE                     15:0
#define SPI_TRANSFER_STATUS_0_BLK_CNT_MSB                       MK_SHIFT_CONST(15)
#define SPI_TRANSFER_STATUS_0_BLK_CNT_LSB                       MK_SHIFT_CONST(0)
#define SPI_TRANSFER_STATUS_0_BLK_CNT_WOFFSET                   0x0
#define SPI_TRANSFER_STATUS_0_BLK_CNT_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_TRANSFER_STATUS_0_BLK_CNT_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define SPI_TRANSFER_STATUS_0_BLK_CNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_TRANSFER_STATUS_0_BLK_CNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_TRANSFER_STATUS_0_BLK_CNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_TRANSFER_STATUS_0_BLK_CNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

// Register SPI_FIFO_STATUS_0
#define SPI_FIFO_STATUS_0                       MK_ADDR_CONST(0x14)
#define SPI_FIFO_STATUS_0_SECURE                        0x0
#define SPI_FIFO_STATUS_0_DUAL                  0x0
#define SPI_FIFO_STATUS_0_SCR                   0
#define SPI_FIFO_STATUS_0_SCRREG                        0
#define SPI_FIFO_STATUS_0_WORD_COUNT                    0x1
#define SPI_FIFO_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x400005)
#define SPI_FIFO_STATUS_0_RESET_MASK                    MK_MASK_CONST(0xffffc3ff)
#define SPI_FIFO_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_READ_MASK                     MK_MASK_CONST(0xffffc3ff)
#define SPI_FIFO_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0xc000c3f0)
#define SPI_FIFO_STATUS_0_CS_INACTIVE_SHIFT                     MK_SHIFT_CONST(31)
#define SPI_FIFO_STATUS_0_CS_INACTIVE_FIELD                     MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_CS_INACTIVE_SHIFT)
#define SPI_FIFO_STATUS_0_CS_INACTIVE_RANGE                     31:31
#define SPI_FIFO_STATUS_0_CS_INACTIVE_MSB                       MK_SHIFT_CONST(31)
#define SPI_FIFO_STATUS_0_CS_INACTIVE_LSB                       MK_SHIFT_CONST(31)
#define SPI_FIFO_STATUS_0_CS_INACTIVE_WOFFSET                   0x0
#define SPI_FIFO_STATUS_0_CS_INACTIVE_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_CS_INACTIVE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_CS_INACTIVE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_CS_INACTIVE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_CS_INACTIVE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_CS_INACTIVE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define SPI_FIFO_STATUS_0_FRAME_END_SHIFT                       MK_SHIFT_CONST(30)
#define SPI_FIFO_STATUS_0_FRAME_END_FIELD                       MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_FRAME_END_SHIFT)
#define SPI_FIFO_STATUS_0_FRAME_END_RANGE                       30:30
#define SPI_FIFO_STATUS_0_FRAME_END_MSB                 MK_SHIFT_CONST(30)
#define SPI_FIFO_STATUS_0_FRAME_END_LSB                 MK_SHIFT_CONST(30)
#define SPI_FIFO_STATUS_0_FRAME_END_WOFFSET                     0x0
#define SPI_FIFO_STATUS_0_FRAME_END_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_FRAME_END_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_FRAME_END_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_FRAME_END_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_FRAME_END_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_FRAME_END_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_SHIFT                      MK_SHIFT_CONST(23)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_FIELD                      MK_FIELD_CONST(0x7f, SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_SHIFT)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_RANGE                      29:23
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_MSB                        MK_SHIFT_CONST(29)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_LSB                        MK_SHIFT_CONST(23)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_WOFFSET                    0x0
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_SHIFT                     MK_SHIFT_CONST(16)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_FIELD                     MK_FIELD_CONST(0x7f, SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_SHIFT)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_RANGE                     22:16
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_MSB                       MK_SHIFT_CONST(22)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_LSB                       MK_SHIFT_CONST(16)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_WOFFSET                   0x0
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_DEFAULT                   MK_MASK_CONST(0x40)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_SHIFT                   MK_SHIFT_CONST(15)
#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_FIELD                   MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_SHIFT)
#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_RANGE                   15:15
#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_MSB                     MK_SHIFT_CONST(15)
#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_LSB                     MK_SHIFT_CONST(15)
#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_WOFFSET                 0x0
#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_NOP                     MK_ENUM_CONST(0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_FLUSH                   MK_ENUM_CONST(1)

#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_SHIFT                   MK_SHIFT_CONST(14)
#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_FIELD                   MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_SHIFT)
#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_RANGE                   14:14
#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_MSB                     MK_SHIFT_CONST(14)
#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_LSB                     MK_SHIFT_CONST(14)
#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_WOFFSET                 0x0
#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_NOP                     MK_ENUM_CONST(0)
#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_FLUSH                   MK_ENUM_CONST(1)

#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_SHIFT                        MK_SHIFT_CONST(9)
#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_FIELD                        MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_SHIFT)
#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_RANGE                        9:9
#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_MSB                  MK_SHIFT_CONST(9)
#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_LSB                  MK_SHIFT_CONST(9)
#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_WOFFSET                      0x0
#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define SPI_FIFO_STATUS_0_ERR_SHIFT                     MK_SHIFT_CONST(8)
#define SPI_FIFO_STATUS_0_ERR_FIELD                     MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_ERR_SHIFT)
#define SPI_FIFO_STATUS_0_ERR_RANGE                     8:8
#define SPI_FIFO_STATUS_0_ERR_MSB                       MK_SHIFT_CONST(8)
#define SPI_FIFO_STATUS_0_ERR_LSB                       MK_SHIFT_CONST(8)
#define SPI_FIFO_STATUS_0_ERR_WOFFSET                   0x0
#define SPI_FIFO_STATUS_0_ERR_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_ERR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_ERR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_ERR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_ERR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_ERR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_ERR_OK                        MK_ENUM_CONST(0)
#define SPI_FIFO_STATUS_0_ERR_ERROR                     MK_ENUM_CONST(1)

#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_SHIFT                     MK_SHIFT_CONST(7)
#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_FIELD                     MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_TX_FIFO_OVF_SHIFT)
#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_RANGE                     7:7
#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_MSB                       MK_SHIFT_CONST(7)
#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_LSB                       MK_SHIFT_CONST(7)
#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_WOFFSET                   0x0
#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_OK                        MK_ENUM_CONST(0)
#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_ERROR                     MK_ENUM_CONST(1)

#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_SHIFT                     MK_SHIFT_CONST(6)
#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_FIELD                     MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_TX_FIFO_UNF_SHIFT)
#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_RANGE                     6:6
#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_MSB                       MK_SHIFT_CONST(6)
#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_LSB                       MK_SHIFT_CONST(6)
#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_WOFFSET                   0x0
#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_OK                        MK_ENUM_CONST(0)
#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_ERROR                     MK_ENUM_CONST(1)

#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_SHIFT                     MK_SHIFT_CONST(5)
#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_FIELD                     MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_RX_FIFO_OVF_SHIFT)
#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_RANGE                     5:5
#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_MSB                       MK_SHIFT_CONST(5)
#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_LSB                       MK_SHIFT_CONST(5)
#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_WOFFSET                   0x0
#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_OK                        MK_ENUM_CONST(0)
#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_ERROR                     MK_ENUM_CONST(1)

#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_SHIFT                     MK_SHIFT_CONST(4)
#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_FIELD                     MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_RX_FIFO_UNF_SHIFT)
#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_RANGE                     4:4
#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_MSB                       MK_SHIFT_CONST(4)
#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_LSB                       MK_SHIFT_CONST(4)
#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_WOFFSET                   0x0
#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_OK                        MK_ENUM_CONST(0)
#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_ERROR                     MK_ENUM_CONST(1)

#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_SHIFT                    MK_SHIFT_CONST(3)
#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_FIELD                    MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_TX_FIFO_FULL_SHIFT)
#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_RANGE                    3:3
#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_MSB                      MK_SHIFT_CONST(3)
#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_LSB                      MK_SHIFT_CONST(3)
#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_WOFFSET                  0x0
#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_NOT_FULL                 MK_ENUM_CONST(0)
#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_FULL                     MK_ENUM_CONST(1)

#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_SHIFT                   MK_SHIFT_CONST(2)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_FIELD                   MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_SHIFT)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_RANGE                   2:2
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_MSB                     MK_SHIFT_CONST(2)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_LSB                     MK_SHIFT_CONST(2)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_WOFFSET                 0x0
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_DEFAULT                 MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_NOT_EMPTY                       MK_ENUM_CONST(0)
#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_EMPTY                   MK_ENUM_CONST(1)

#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_SHIFT                    MK_SHIFT_CONST(1)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_FIELD                    MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_RX_FIFO_FULL_SHIFT)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_RANGE                    1:1
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_MSB                      MK_SHIFT_CONST(1)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_LSB                      MK_SHIFT_CONST(1)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_WOFFSET                  0x0
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_NOT_FULL                 MK_ENUM_CONST(0)
#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_FULL                     MK_ENUM_CONST(1)

#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_SHIFT                   MK_SHIFT_CONST(0)
#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_FIELD                   MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_SHIFT)
#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_RANGE                   0:0
#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_MSB                     MK_SHIFT_CONST(0)
#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_LSB                     MK_SHIFT_CONST(0)
#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_WOFFSET                 0x0
#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_DEFAULT                 MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_NOT_EMPTY                       MK_ENUM_CONST(0)
#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_EMPTY                   MK_ENUM_CONST(1)

// Register SPI_TX_DATA_0
#define SPI_TX_DATA_0                   MK_ADDR_CONST(0x18)
#define SPI_TX_DATA_0_SECURE                    0x0
#define SPI_TX_DATA_0_DUAL                      0x0
#define SPI_TX_DATA_0_SCR                       0
#define SPI_TX_DATA_0_SCRREG                    0
#define SPI_TX_DATA_0_WORD_COUNT                        0x1
#define SPI_TX_DATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define SPI_TX_DATA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define SPI_TX_DATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define SPI_TX_DATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_TX_DATA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define SPI_TX_DATA_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define SPI_TX_DATA_0_Tx_BUFFER_SHIFT                   MK_SHIFT_CONST(0)
#define SPI_TX_DATA_0_Tx_BUFFER_FIELD                   MK_FIELD_CONST(0xffffffff, SPI_TX_DATA_0_Tx_BUFFER_SHIFT)
#define SPI_TX_DATA_0_Tx_BUFFER_RANGE                   31:0
#define SPI_TX_DATA_0_Tx_BUFFER_MSB                     MK_SHIFT_CONST(31)
#define SPI_TX_DATA_0_Tx_BUFFER_LSB                     MK_SHIFT_CONST(0)
#define SPI_TX_DATA_0_Tx_BUFFER_WOFFSET                 0x0
#define SPI_TX_DATA_0_Tx_BUFFER_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_TX_DATA_0_Tx_BUFFER_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define SPI_TX_DATA_0_Tx_BUFFER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_TX_DATA_0_Tx_BUFFER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define SPI_TX_DATA_0_Tx_BUFFER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define SPI_TX_DATA_0_Tx_BUFFER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

// Register SPI_RX_DATA_0
#define SPI_RX_DATA_0                   MK_ADDR_CONST(0x1c)
#define SPI_RX_DATA_0_SECURE                    0x0
#define SPI_RX_DATA_0_DUAL                      0x0
#define SPI_RX_DATA_0_SCR                       0
#define SPI_RX_DATA_0_SCRREG                    0
#define SPI_RX_DATA_0_WORD_COUNT                        0x1
#define SPI_RX_DATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define SPI_RX_DATA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define SPI_RX_DATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define SPI_RX_DATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_RX_DATA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define SPI_RX_DATA_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define SPI_RX_DATA_0_Rx_BUFFER_SHIFT                   MK_SHIFT_CONST(0)
#define SPI_RX_DATA_0_Rx_BUFFER_FIELD                   MK_FIELD_CONST(0xffffffff, SPI_RX_DATA_0_Rx_BUFFER_SHIFT)
#define SPI_RX_DATA_0_Rx_BUFFER_RANGE                   31:0
#define SPI_RX_DATA_0_Rx_BUFFER_MSB                     MK_SHIFT_CONST(31)
#define SPI_RX_DATA_0_Rx_BUFFER_LSB                     MK_SHIFT_CONST(0)
#define SPI_RX_DATA_0_Rx_BUFFER_WOFFSET                 0x0
#define SPI_RX_DATA_0_Rx_BUFFER_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_RX_DATA_0_Rx_BUFFER_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define SPI_RX_DATA_0_Rx_BUFFER_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_RX_DATA_0_Rx_BUFFER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define SPI_RX_DATA_0_Rx_BUFFER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define SPI_RX_DATA_0_Rx_BUFFER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

// Register SPI_DMA_CTL_0
#define SPI_DMA_CTL_0                   MK_ADDR_CONST(0x20)
#define SPI_DMA_CTL_0_SECURE                    0x0
#define SPI_DMA_CTL_0_DUAL                      0x0
#define SPI_DMA_CTL_0_SCR                       0
#define SPI_DMA_CTL_0_SCRREG                    0
#define SPI_DMA_CTL_0_WORD_COUNT                        0x1
#define SPI_DMA_CTL_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_RESET_MASK                        MK_MASK_CONST(0xe0198000)
#define SPI_DMA_CTL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_READ_MASK                         MK_MASK_CONST(0xe0198000)
#define SPI_DMA_CTL_0_WRITE_MASK                        MK_MASK_CONST(0xe0198000)
#define SPI_DMA_CTL_0_DMA_EN_SHIFT                      MK_SHIFT_CONST(31)
#define SPI_DMA_CTL_0_DMA_EN_FIELD                      MK_FIELD_CONST(0x1, SPI_DMA_CTL_0_DMA_EN_SHIFT)
#define SPI_DMA_CTL_0_DMA_EN_RANGE                      31:31
#define SPI_DMA_CTL_0_DMA_EN_MSB                        MK_SHIFT_CONST(31)
#define SPI_DMA_CTL_0_DMA_EN_LSB                        MK_SHIFT_CONST(31)
#define SPI_DMA_CTL_0_DMA_EN_WOFFSET                    0x0
#define SPI_DMA_CTL_0_DMA_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_DMA_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define SPI_DMA_CTL_0_DMA_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_DMA_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_DMA_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_DMA_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define SPI_DMA_CTL_0_DMA_EN_DISABLE                    MK_ENUM_CONST(0)
#define SPI_DMA_CTL_0_DMA_EN_ENABLE                     MK_ENUM_CONST(1)

#define SPI_DMA_CTL_0_CONT_SHIFT                        MK_SHIFT_CONST(30)
#define SPI_DMA_CTL_0_CONT_FIELD                        MK_FIELD_CONST(0x1, SPI_DMA_CTL_0_CONT_SHIFT)
#define SPI_DMA_CTL_0_CONT_RANGE                        30:30
#define SPI_DMA_CTL_0_CONT_MSB                  MK_SHIFT_CONST(30)
#define SPI_DMA_CTL_0_CONT_LSB                  MK_SHIFT_CONST(30)
#define SPI_DMA_CTL_0_CONT_WOFFSET                      0x0
#define SPI_DMA_CTL_0_CONT_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_CONT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define SPI_DMA_CTL_0_CONT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_CONT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_CONT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_CONT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define SPI_DMA_CTL_0_CONT_DISABLE                      MK_ENUM_CONST(0)
#define SPI_DMA_CTL_0_CONT_ENABLE                       MK_ENUM_CONST(1)

#define SPI_DMA_CTL_0_PAUSE_SHIFT                       MK_SHIFT_CONST(29)
#define SPI_DMA_CTL_0_PAUSE_FIELD                       MK_FIELD_CONST(0x1, SPI_DMA_CTL_0_PAUSE_SHIFT)
#define SPI_DMA_CTL_0_PAUSE_RANGE                       29:29
#define SPI_DMA_CTL_0_PAUSE_MSB                 MK_SHIFT_CONST(29)
#define SPI_DMA_CTL_0_PAUSE_LSB                 MK_SHIFT_CONST(29)
#define SPI_DMA_CTL_0_PAUSE_WOFFSET                     0x0
#define SPI_DMA_CTL_0_PAUSE_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_PAUSE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define SPI_DMA_CTL_0_PAUSE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_PAUSE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_PAUSE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_PAUSE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define SPI_DMA_CTL_0_PAUSE_DISABLE                     MK_ENUM_CONST(0)
#define SPI_DMA_CTL_0_PAUSE_ENABLE                      MK_ENUM_CONST(1)

#define SPI_DMA_CTL_0_RX_TRIG_SHIFT                     MK_SHIFT_CONST(19)
#define SPI_DMA_CTL_0_RX_TRIG_FIELD                     MK_FIELD_CONST(0x3, SPI_DMA_CTL_0_RX_TRIG_SHIFT)
#define SPI_DMA_CTL_0_RX_TRIG_RANGE                     20:19
#define SPI_DMA_CTL_0_RX_TRIG_MSB                       MK_SHIFT_CONST(20)
#define SPI_DMA_CTL_0_RX_TRIG_LSB                       MK_SHIFT_CONST(19)
#define SPI_DMA_CTL_0_RX_TRIG_WOFFSET                   0x0
#define SPI_DMA_CTL_0_RX_TRIG_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_RX_TRIG_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define SPI_DMA_CTL_0_RX_TRIG_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_RX_TRIG_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_RX_TRIG_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_RX_TRIG_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_DMA_CTL_0_RX_TRIG_TRIG1                     MK_ENUM_CONST(0)
#define SPI_DMA_CTL_0_RX_TRIG_TRIG4                     MK_ENUM_CONST(1)
#define SPI_DMA_CTL_0_RX_TRIG_TRIG8                     MK_ENUM_CONST(2)
#define SPI_DMA_CTL_0_RX_TRIG_TRIG16                    MK_ENUM_CONST(3)

#define SPI_DMA_CTL_0_TX_TRIG_SHIFT                     MK_SHIFT_CONST(15)
#define SPI_DMA_CTL_0_TX_TRIG_FIELD                     MK_FIELD_CONST(0x3, SPI_DMA_CTL_0_TX_TRIG_SHIFT)
#define SPI_DMA_CTL_0_TX_TRIG_RANGE                     16:15
#define SPI_DMA_CTL_0_TX_TRIG_MSB                       MK_SHIFT_CONST(16)
#define SPI_DMA_CTL_0_TX_TRIG_LSB                       MK_SHIFT_CONST(15)
#define SPI_DMA_CTL_0_TX_TRIG_WOFFSET                   0x0
#define SPI_DMA_CTL_0_TX_TRIG_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_TX_TRIG_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define SPI_DMA_CTL_0_TX_TRIG_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_TX_TRIG_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_TX_TRIG_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_DMA_CTL_0_TX_TRIG_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_DMA_CTL_0_TX_TRIG_TRIG1                     MK_ENUM_CONST(0)
#define SPI_DMA_CTL_0_TX_TRIG_TRIG4                     MK_ENUM_CONST(1)
#define SPI_DMA_CTL_0_TX_TRIG_TRIG8                     MK_ENUM_CONST(2)
#define SPI_DMA_CTL_0_TX_TRIG_TRIG16                    MK_ENUM_CONST(3)

// Register SPI_DMA_BLK_SIZE_0
#define SPI_DMA_BLK_SIZE_0                      MK_ADDR_CONST(0x24)
#define SPI_DMA_BLK_SIZE_0_SECURE                       0x0
#define SPI_DMA_BLK_SIZE_0_DUAL                         0x0
#define SPI_DMA_BLK_SIZE_0_SCR                  0
#define SPI_DMA_BLK_SIZE_0_SCRREG                       0
#define SPI_DMA_BLK_SIZE_0_WORD_COUNT                   0x1
#define SPI_DMA_BLK_SIZE_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define SPI_DMA_BLK_SIZE_0_RESET_MASK                   MK_MASK_CONST(0xffff)
#define SPI_DMA_BLK_SIZE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define SPI_DMA_BLK_SIZE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_DMA_BLK_SIZE_0_READ_MASK                    MK_MASK_CONST(0xffff)
#define SPI_DMA_BLK_SIZE_0_WRITE_MASK                   MK_MASK_CONST(0xffff)
#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_SHIFT                 MK_SHIFT_CONST(0)
#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_FIELD                 MK_FIELD_CONST(0xffff, SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_SHIFT)
#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_RANGE                 15:0
#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_MSB                   MK_SHIFT_CONST(15)
#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_LSB                   MK_SHIFT_CONST(0)
#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_WOFFSET                       0x0
#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Reserved address 0x28

// Reserved address 0x2c

// Reserved address 0x30

// Reserved address 0x34

// Reserved address 0x38

// Reserved address 0x3c

// Reserved address 0x40

// Reserved address 0x44

// Reserved address 0x48

// Reserved address 0x4c

// Reserved address 0x50

// Reserved address 0x54

// Reserved address 0x58

// Reserved address 0x5c

// Reserved address 0x60

// Reserved address 0x64

// Reserved address 0x68

// Reserved address 0x6c

// Reserved address 0x70

// Reserved address 0x74

// Reserved address 0x78

// Reserved address 0x7c

// Reserved address 0x80

// Reserved address 0x84

// Reserved address 0x88

// Reserved address 0x8c

// Reserved address 0x90

// Reserved address 0x94

// Reserved address 0x98

// Reserved address 0x9c

// Reserved address 0xa0

// Reserved address 0xa4

// Reserved address 0xa8

// Reserved address 0xac

// Reserved address 0xb0

// Reserved address 0xb4

// Reserved address 0xb8

// Reserved address 0xbc

// Reserved address 0xc0

// Reserved address 0xc4

// Reserved address 0xc8

// Reserved address 0xcc

// Reserved address 0xd0

// Reserved address 0xd4

// Reserved address 0xd8

// Reserved address 0xdc

// Reserved address 0xe0

// Reserved address 0xe4

// Reserved address 0xe8

// Reserved address 0xec

// Reserved address 0xf0

// Reserved address 0xf4

// Reserved address 0xf8

// Reserved address 0xfc

// Reserved address 0x100

// Reserved address 0x104

// Register SPI_TX_FIFO_0
#define SPI_TX_FIFO_0                   MK_ADDR_CONST(0x108)
#define SPI_TX_FIFO_0_SECURE                    0x0
#define SPI_TX_FIFO_0_DUAL                      0x0
#define SPI_TX_FIFO_0_SCR                       0
#define SPI_TX_FIFO_0_SCRREG                    0
#define SPI_TX_FIFO_0_WORD_COUNT                        0x1
#define SPI_TX_FIFO_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define SPI_TX_FIFO_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define SPI_TX_FIFO_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define SPI_TX_FIFO_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_TX_FIFO_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define SPI_TX_FIFO_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT                    MK_SHIFT_CONST(0)
#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_FIELD                    MK_FIELD_CONST(0xffffffff, SPI_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT)
#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_RANGE                    31:0
#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_MSB                      MK_SHIFT_CONST(31)
#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_LSB                      MK_SHIFT_CONST(0)
#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_WOFFSET                  0x0
#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

// Reserved address 0x10c

// Reserved address 0x110

// Reserved address 0x114

// Reserved address 0x118

// Reserved address 0x11c

// Reserved address 0x120

// Reserved address 0x124

// Reserved address 0x128

// Reserved address 0x12c

// Reserved address 0x130

// Reserved address 0x134

// Reserved address 0x138

// Reserved address 0x13c

// Reserved address 0x140

// Reserved address 0x144

// Reserved address 0x148

// Reserved address 0x14c

// Reserved address 0x150

// Reserved address 0x154

// Reserved address 0x158

// Reserved address 0x15c

// Reserved address 0x160

// Reserved address 0x164

// Reserved address 0x168

// Reserved address 0x16c

// Reserved address 0x170

// Reserved address 0x174

// Reserved address 0x178

// Reserved address 0x17c

// Reserved address 0x180

// Reserved address 0x184

// Register SPI_RX_FIFO_0
#define SPI_RX_FIFO_0                   MK_ADDR_CONST(0x188)
#define SPI_RX_FIFO_0_SECURE                    0x0
#define SPI_RX_FIFO_0_DUAL                      0x0
#define SPI_RX_FIFO_0_SCR                       0
#define SPI_RX_FIFO_0_SCRREG                    0
#define SPI_RX_FIFO_0_WORD_COUNT                        0x1
#define SPI_RX_FIFO_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define SPI_RX_FIFO_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define SPI_RX_FIFO_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define SPI_RX_FIFO_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_RX_FIFO_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define SPI_RX_FIFO_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT                    MK_SHIFT_CONST(0)
#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_FIELD                    MK_FIELD_CONST(0xffffffff, SPI_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT)
#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_RANGE                    31:0
#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_MSB                      MK_SHIFT_CONST(31)
#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_LSB                      MK_SHIFT_CONST(0)
#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_WOFFSET                  0x0
#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

// Register SPI_INTR_MASK_0
#define SPI_INTR_MASK_0                 MK_ADDR_CONST(0x18c)
#define SPI_INTR_MASK_0_SECURE                  0x0
#define SPI_INTR_MASK_0_DUAL                    0x0
#define SPI_INTR_MASK_0_SCR                     0
#define SPI_INTR_MASK_0_SCRREG                  0
#define SPI_INTR_MASK_0_WORD_COUNT                      0x1
#define SPI_INTR_MASK_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_RESET_MASK                      MK_MASK_CONST(0xfe000200)
#define SPI_INTR_MASK_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_READ_MASK                       MK_MASK_CONST(0xfe000200)
#define SPI_INTR_MASK_0_WRITE_MASK                      MK_MASK_CONST(0xfe000200)
#define SPI_INTR_MASK_0_CS_INTR_MASK_SHIFT                      MK_SHIFT_CONST(31)
#define SPI_INTR_MASK_0_CS_INTR_MASK_FIELD                      MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_CS_INTR_MASK_SHIFT)
#define SPI_INTR_MASK_0_CS_INTR_MASK_RANGE                      31:31
#define SPI_INTR_MASK_0_CS_INTR_MASK_MSB                        MK_SHIFT_CONST(31)
#define SPI_INTR_MASK_0_CS_INTR_MASK_LSB                        MK_SHIFT_CONST(31)
#define SPI_INTR_MASK_0_CS_INTR_MASK_WOFFSET                    0x0
#define SPI_INTR_MASK_0_CS_INTR_MASK_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_CS_INTR_MASK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_CS_INTR_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_CS_INTR_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_CS_INTR_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_CS_INTR_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_CS_INTR_MASK_DISABLE                    MK_ENUM_CONST(0)
#define SPI_INTR_MASK_0_CS_INTR_MASK_ENABLE                     MK_ENUM_CONST(1)

#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_SHIFT                       MK_SHIFT_CONST(30)
#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_FIELD                       MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_FRAME_END_INTR_MASK_SHIFT)
#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_RANGE                       30:30
#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_MSB                 MK_SHIFT_CONST(30)
#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_LSB                 MK_SHIFT_CONST(30)
#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_WOFFSET                     0x0
#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_DISABLE                     MK_ENUM_CONST(0)
#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_ENABLE                      MK_ENUM_CONST(1)

#define SPI_INTR_MASK_0_RDY_INTR_MASK_SHIFT                     MK_SHIFT_CONST(29)
#define SPI_INTR_MASK_0_RDY_INTR_MASK_FIELD                     MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_RDY_INTR_MASK_SHIFT)
#define SPI_INTR_MASK_0_RDY_INTR_MASK_RANGE                     29:29
#define SPI_INTR_MASK_0_RDY_INTR_MASK_MSB                       MK_SHIFT_CONST(29)
#define SPI_INTR_MASK_0_RDY_INTR_MASK_LSB                       MK_SHIFT_CONST(29)
#define SPI_INTR_MASK_0_RDY_INTR_MASK_WOFFSET                   0x0
#define SPI_INTR_MASK_0_RDY_INTR_MASK_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_RDY_INTR_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_RDY_INTR_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_RDY_INTR_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_RDY_INTR_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_RDY_INTR_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_RDY_INTR_MASK_DISABLE                   MK_ENUM_CONST(0)
#define SPI_INTR_MASK_0_RDY_INTR_MASK_ENABLE                    MK_ENUM_CONST(1)

#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_SHIFT                     MK_SHIFT_CONST(28)
#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_FIELD                     MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_SHIFT)
#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_RANGE                     28:28
#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_MSB                       MK_SHIFT_CONST(28)
#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_LSB                       MK_SHIFT_CONST(28)
#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_WOFFSET                   0x0
#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_DISABLE                   MK_ENUM_CONST(0)
#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_ENABLE                    MK_ENUM_CONST(1)

#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_SHIFT                     MK_SHIFT_CONST(27)
#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_FIELD                     MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_SHIFT)
#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_RANGE                     27:27
#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_MSB                       MK_SHIFT_CONST(27)
#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_LSB                       MK_SHIFT_CONST(27)
#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_WOFFSET                   0x0
#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_DISABLE                   MK_ENUM_CONST(0)
#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_ENABLE                    MK_ENUM_CONST(1)

#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_SHIFT                     MK_SHIFT_CONST(26)
#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_FIELD                     MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_SHIFT)
#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_RANGE                     26:26
#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_MSB                       MK_SHIFT_CONST(26)
#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_LSB                       MK_SHIFT_CONST(26)
#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_WOFFSET                   0x0
#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_DISABLE                   MK_ENUM_CONST(0)
#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_ENABLE                    MK_ENUM_CONST(1)

#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_SHIFT                     MK_SHIFT_CONST(25)
#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_FIELD                     MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_SHIFT)
#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_RANGE                     25:25
#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_MSB                       MK_SHIFT_CONST(25)
#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_LSB                       MK_SHIFT_CONST(25)
#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_WOFFSET                   0x0
#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_DISABLE                   MK_ENUM_CONST(0)
#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_ENABLE                    MK_ENUM_CONST(1)

#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_SHIFT                     MK_SHIFT_CONST(9)
#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_FIELD                     MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_SHIFT)
#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_RANGE                     9:9
#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_MSB                       MK_SHIFT_CONST(9)
#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_LSB                       MK_SHIFT_CONST(9)
#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_WOFFSET                   0x0
#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_DISABLE                   MK_ENUM_CONST(0)
#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_ENABLE                    MK_ENUM_CONST(1)

// Register SPI_SPARE_CTLR_0
#define SPI_SPARE_CTLR_0                        MK_ADDR_CONST(0x190)
#define SPI_SPARE_CTLR_0_SECURE                         0x0
#define SPI_SPARE_CTLR_0_DUAL                   0x0
#define SPI_SPARE_CTLR_0_SCR                    0
#define SPI_SPARE_CTLR_0_SCRREG                         0
#define SPI_SPARE_CTLR_0_WORD_COUNT                     0x1
#define SPI_SPARE_CTLR_0_RESET_VAL                      MK_MASK_CONST(0xfff0000)
#define SPI_SPARE_CTLR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define SPI_SPARE_CTLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define SPI_SPARE_CTLR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_SHIFT                     MK_SHIFT_CONST(24)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_FIELD                     MK_FIELD_CONST(0xff, SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_SHIFT)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_RANGE                     31:24
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_MSB                       MK_SHIFT_CONST(31)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_LSB                       MK_SHIFT_CONST(24)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_WOFFSET                   0x0
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_DEFAULT                   MK_MASK_CONST(0xf)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_SHIFT                     MK_SHIFT_CONST(16)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_FIELD                     MK_FIELD_CONST(0xff, SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_SHIFT)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_RANGE                     23:16
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_MSB                       MK_SHIFT_CONST(23)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_LSB                       MK_SHIFT_CONST(16)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_WOFFSET                   0x0
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_DEFAULT                   MK_MASK_CONST(0xff)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_SHIFT                     MK_SHIFT_CONST(8)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_FIELD                     MK_FIELD_CONST(0xff, SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_SHIFT)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_RANGE                     15:8
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_MSB                       MK_SHIFT_CONST(15)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_LSB                       MK_SHIFT_CONST(8)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_WOFFSET                   0x0
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_SHIFT                     MK_SHIFT_CONST(0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_FIELD                     MK_FIELD_CONST(0xff, SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_SHIFT)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_RANGE                     7:0
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_MSB                       MK_SHIFT_CONST(7)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_LSB                       MK_SHIFT_CONST(0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_WOFFSET                   0x0
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

// Register SPI_MISC_0
#define SPI_MISC_0                      MK_ADDR_CONST(0x194)
#define SPI_MISC_0_SECURE                       0x0
#define SPI_MISC_0_DUAL                         0x0
#define SPI_MISC_0_SCR                  0
#define SPI_MISC_0_SCRREG                       0
#define SPI_MISC_0_WORD_COUNT                   0x1
#define SPI_MISC_0_RESET_VAL                    MK_MASK_CONST(0x80000000)
#define SPI_MISC_0_RESET_MASK                   MK_MASK_CONST(0xc0000000)
#define SPI_MISC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define SPI_MISC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_MISC_0_READ_MASK                    MK_MASK_CONST(0xc0000000)
#define SPI_MISC_0_WRITE_MASK                   MK_MASK_CONST(0xc0000000)
#define SPI_MISC_0_CLKEN_OVERRIDE_SHIFT                 MK_SHIFT_CONST(31)
#define SPI_MISC_0_CLKEN_OVERRIDE_FIELD                 MK_FIELD_CONST(0x1, SPI_MISC_0_CLKEN_OVERRIDE_SHIFT)
#define SPI_MISC_0_CLKEN_OVERRIDE_RANGE                 31:31
#define SPI_MISC_0_CLKEN_OVERRIDE_MSB                   MK_SHIFT_CONST(31)
#define SPI_MISC_0_CLKEN_OVERRIDE_LSB                   MK_SHIFT_CONST(31)
#define SPI_MISC_0_CLKEN_OVERRIDE_WOFFSET                       0x0
#define SPI_MISC_0_CLKEN_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x1)
#define SPI_MISC_0_CLKEN_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define SPI_MISC_0_CLKEN_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_MISC_0_CLKEN_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define SPI_MISC_0_CLKEN_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define SPI_MISC_0_CLKEN_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define SPI_MISC_0_CLKEN_OVERRIDE__PROD                 MK_ENUM_CONST(0)

#define SPI_MISC_0_EXT_CLK_EN_SHIFT                     MK_SHIFT_CONST(30)
#define SPI_MISC_0_EXT_CLK_EN_FIELD                     MK_FIELD_CONST(0x1, SPI_MISC_0_EXT_CLK_EN_SHIFT)
#define SPI_MISC_0_EXT_CLK_EN_RANGE                     30:30
#define SPI_MISC_0_EXT_CLK_EN_MSB                       MK_SHIFT_CONST(30)
#define SPI_MISC_0_EXT_CLK_EN_LSB                       MK_SHIFT_CONST(30)
#define SPI_MISC_0_EXT_CLK_EN_WOFFSET                   0x0
#define SPI_MISC_0_EXT_CLK_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_MISC_0_EXT_CLK_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_MISC_0_EXT_CLK_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_MISC_0_EXT_CLK_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_MISC_0_EXT_CLK_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_MISC_0_EXT_CLK_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

// Register SPI_FATAL_INTR_EN_0
#define SPI_FATAL_INTR_EN_0                     MK_ADDR_CONST(0x198)
#define SPI_FATAL_INTR_EN_0_SECURE                      0x0
#define SPI_FATAL_INTR_EN_0_DUAL                        0x0
#define SPI_FATAL_INTR_EN_0_SCR                         0
#define SPI_FATAL_INTR_EN_0_SCRREG                      0
#define SPI_FATAL_INTR_EN_0_WORD_COUNT                  0x1
#define SPI_FATAL_INTR_EN_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_RESET_MASK                  MK_MASK_CONST(0xde000200)
#define SPI_FATAL_INTR_EN_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_READ_MASK                   MK_MASK_CONST(0xde000200)
#define SPI_FATAL_INTR_EN_0_WRITE_MASK                  MK_MASK_CONST(0xde000200)
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_SHIFT                      MK_SHIFT_CONST(31)
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_FIELD                      MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_SHIFT)
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_RANGE                      31:31
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_MSB                        MK_SHIFT_CONST(31)
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_LSB                        MK_SHIFT_CONST(31)
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_WOFFSET                    0x0
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_DISABLE                    MK_ENUM_CONST(0)
#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_ENABLE                     MK_ENUM_CONST(1)

#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_SHIFT                       MK_SHIFT_CONST(30)
#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_FIELD                       MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_SHIFT)
#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_RANGE                       30:30
#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_MSB                 MK_SHIFT_CONST(30)
#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_LSB                 MK_SHIFT_CONST(30)
#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_WOFFSET                     0x0
#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_DISABLE                     MK_ENUM_CONST(0)
#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_ENABLE                      MK_ENUM_CONST(1)

#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_SHIFT                     MK_SHIFT_CONST(28)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_FIELD                     MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_SHIFT)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_RANGE                     28:28
#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_MSB                       MK_SHIFT_CONST(28)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_LSB                       MK_SHIFT_CONST(28)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_WOFFSET                   0x0
#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_DISABLE                   MK_ENUM_CONST(0)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_ENABLE                    MK_ENUM_CONST(1)

#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_SHIFT                     MK_SHIFT_CONST(27)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_FIELD                     MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_SHIFT)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_RANGE                     27:27
#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_MSB                       MK_SHIFT_CONST(27)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_LSB                       MK_SHIFT_CONST(27)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_WOFFSET                   0x0
#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_DISABLE                   MK_ENUM_CONST(0)
#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_ENABLE                    MK_ENUM_CONST(1)

#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_SHIFT                     MK_SHIFT_CONST(26)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_FIELD                     MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_SHIFT)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_RANGE                     26:26
#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_MSB                       MK_SHIFT_CONST(26)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_LSB                       MK_SHIFT_CONST(26)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_WOFFSET                   0x0
#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_DISABLE                   MK_ENUM_CONST(0)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_ENABLE                    MK_ENUM_CONST(1)

#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_SHIFT                     MK_SHIFT_CONST(25)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_FIELD                     MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_SHIFT)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_RANGE                     25:25
#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_MSB                       MK_SHIFT_CONST(25)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_LSB                       MK_SHIFT_CONST(25)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_WOFFSET                   0x0
#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_DISABLE                   MK_ENUM_CONST(0)
#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_ENABLE                    MK_ENUM_CONST(1)

#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_SHIFT                     MK_SHIFT_CONST(9)
#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_FIELD                     MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_SHIFT)
#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_RANGE                     9:9
#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_MSB                       MK_SHIFT_CONST(9)
#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_LSB                       MK_SHIFT_CONST(9)
#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_WOFFSET                   0x0
#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_DISABLE                   MK_ENUM_CONST(0)
#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_ENABLE                    MK_ENUM_CONST(1)

// Register SPI_CS_BOUNDARY_TIMEOUT_0
#define SPI_CS_BOUNDARY_TIMEOUT_0                       MK_ADDR_CONST(0x19c)
#define SPI_CS_BOUNDARY_TIMEOUT_0_SECURE                        0x0
#define SPI_CS_BOUNDARY_TIMEOUT_0_DUAL                  0x0
#define SPI_CS_BOUNDARY_TIMEOUT_0_SCR                   0
#define SPI_CS_BOUNDARY_TIMEOUT_0_SCRREG                        0
#define SPI_CS_BOUNDARY_TIMEOUT_0_WORD_COUNT                    0x1
#define SPI_CS_BOUNDARY_TIMEOUT_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define SPI_CS_BOUNDARY_TIMEOUT_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define SPI_CS_BOUNDARY_TIMEOUT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define SPI_CS_BOUNDARY_TIMEOUT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define SPI_CS_BOUNDARY_TIMEOUT_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define SPI_CS_BOUNDARY_TIMEOUT_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_SHIFT                   MK_SHIFT_CONST(0)
#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_SHIFT)
#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_RANGE                   31:0
#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_MSB                     MK_SHIFT_CONST(31)
#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_LSB                     MK_SHIFT_CONST(0)
#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_WOFFSET                 0x0
#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

// Register SPI_TIMEOUT_BOUNDARY_STATUS_0
#define SPI_TIMEOUT_BOUNDARY_STATUS_0                   MK_ADDR_CONST(0x1a0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_SECURE                    0x0
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_DUAL                      0x0
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_SCR                       0
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_SCRREG                    0
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_WORD_COUNT                        0x1
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_SHIFT                        MK_SHIFT_CONST(28)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_FIELD                        MK_FIELD_CONST(0xf, SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_SHIFT)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_RANGE                        31:28
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_MSB                  MK_SHIFT_CONST(31)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_LSB                  MK_SHIFT_CONST(28)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_WOFFSET                      0x0
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_SHIFT                      MK_SHIFT_CONST(0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_FIELD                      MK_FIELD_CONST(0xfffffff, SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_SHIFT)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_RANGE                      27:0
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_MSB                        MK_SHIFT_CONST(27)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_LSB                        MK_SHIFT_CONST(0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_WOFFSET                    0x0
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_DEFAULT_MASK                       MK_MASK_CONST(0xfffffff)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

// Register SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0                      MK_ADDR_CONST(0x1a4)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_SECURE                       0x0
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_DUAL                         0x0
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_SCR                  0
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_SCRREG                       0
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_WORD_COUNT                   0x1
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7f010f)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7f010f)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x10c)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_SHIFT                        MK_SHIFT_CONST(16)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_FIELD                        MK_FIELD_CONST(0x7f, SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_SHIFT)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_RANGE                        22:16
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_MSB                  MK_SHIFT_CONST(22)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_LSB                  MK_SHIFT_CONST(16)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_WOFFSET                      0x0
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_SHIFT                     MK_SHIFT_CONST(8)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_FIELD                     MK_FIELD_CONST(0x1, SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_SHIFT)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_RANGE                     8:8
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_MSB                       MK_SHIFT_CONST(8)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_LSB                       MK_SHIFT_CONST(8)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_WOFFSET                   0x0
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_DEFAULT                   MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_NOP                       MK_ENUM_CONST(0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_FLUSH                     MK_ENUM_CONST(1)

#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_SHIFT                       MK_SHIFT_CONST(3)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_FIELD                       MK_FIELD_CONST(0x1, SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_SHIFT)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_RANGE                       3:3
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_MSB                 MK_SHIFT_CONST(3)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_LSB                 MK_SHIFT_CONST(3)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_WOFFSET                     0x0
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_OK                  MK_ENUM_CONST(0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_ERROR                       MK_ENUM_CONST(1)

#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_SHIFT                       MK_SHIFT_CONST(2)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_FIELD                       MK_FIELD_CONST(0x1, SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_SHIFT)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_RANGE                       2:2
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_MSB                 MK_SHIFT_CONST(2)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_LSB                 MK_SHIFT_CONST(2)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_WOFFSET                     0x0
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_DEFAULT                     MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_OK                  MK_ENUM_CONST(0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_ERROR                       MK_ENUM_CONST(1)

#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_SHIFT                      MK_SHIFT_CONST(1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_FIELD                      MK_FIELD_CONST(0x1, SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_SHIFT)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_RANGE                      1:1
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_MSB                        MK_SHIFT_CONST(1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_LSB                        MK_SHIFT_CONST(1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_WOFFSET                    0x0
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_DEFAULT                    MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_NOT_FULL                   MK_ENUM_CONST(0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_FULL                       MK_ENUM_CONST(1)

#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_SHIFT                     MK_SHIFT_CONST(0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_FIELD                     MK_FIELD_CONST(0x1, SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_SHIFT)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_RANGE                     0:0
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_MSB                       MK_SHIFT_CONST(0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_LSB                       MK_SHIFT_CONST(0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_WOFFSET                   0x0
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_DEFAULT                   MK_MASK_CONST(0x1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_NOT_EMPTY                 MK_ENUM_CONST(0)
#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_EMPTY                     MK_ENUM_CONST(1)

// Reserved address 0x1a8

// Reserved address 0x1ac

// Reserved address 0x1b0

// Reserved address 0x1b4

// Reserved address 0x1b8

// Reserved address 0x1bc

// Reserved address 0x1c0

// Reserved address 0x1c4

// Reserved address 0x1c8

// Reserved address 0x1cc

// Reserved address 0x1d0

// Reserved address 0x1d4

// Reserved address 0x1d8

// Reserved address 0x1dc

// Reserved address 0x1e0

// Reserved address 0x1e4

// Reserved address 0x1e8

// Reserved address 0x1ec

// Reserved address 0x1f0

// Reserved address 0x1f4

// Reserved address 0x1f8

// Reserved address 0x1fc

// Reserved address 0x200

// Reserved address 0x204

// Reserved address 0x208

// Reserved address 0x20c

// Reserved address 0x210

// Reserved address 0x214

// Reserved address 0x218

// Reserved address 0x21c

// Reserved address 0x220

// Reserved address 0x224

// Reserved address 0x228

// Reserved address 0x22c

// Reserved address 0x230

// Reserved address 0x234

// Reserved address 0x238

// Reserved address 0x23c

// Reserved address 0x240

// Reserved address 0x244

// Reserved address 0x248

// Reserved address 0x24c

// Reserved address 0x250

// Reserved address 0x254

// Reserved address 0x258

// Reserved address 0x25c

// Reserved address 0x260

// Reserved address 0x264

// Reserved address 0x268

// Reserved address 0x26c

// Reserved address 0x270

// Reserved address 0x274

// Reserved address 0x278

// Reserved address 0x27c

// Reserved address 0x280

// Reserved address 0x284

//
// REGISTER LIST
//
#define LIST_ARSPI_REGS(_op_) \
_op_(SPI_COMMAND_0) \
_op_(SPI_COMMAND2_0) \
_op_(SPI_TIMING_REG1_0) \
_op_(SPI_TIMING_REG2_0) \
_op_(SPI_TRANSFER_STATUS_0) \
_op_(SPI_FIFO_STATUS_0) \
_op_(SPI_TX_DATA_0) \
_op_(SPI_RX_DATA_0) \
_op_(SPI_DMA_CTL_0) \
_op_(SPI_DMA_BLK_SIZE_0) \
_op_(SPI_TX_FIFO_0) \
_op_(SPI_RX_FIFO_0) \
_op_(SPI_INTR_MASK_0) \
_op_(SPI_SPARE_CTLR_0) \
_op_(SPI_MISC_0) \
_op_(SPI_FATAL_INTR_EN_0) \
_op_(SPI_CS_BOUNDARY_TIMEOUT_0) \
_op_(SPI_TIMEOUT_BOUNDARY_STATUS_0) \
_op_(SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0) \

//
// ADDRESS SPACES
//

#define BASE_ADDRESS_SPI        0x00000000

//
// ARSPI REGISTER BANKS
//

#define SPI0_FIRST_REG 0x0000 // SPI_COMMAND_0
#define SPI0_LAST_REG 0x0024 // SPI_DMA_BLK_SIZE_0
#define SPI1_FIRST_REG 0x0108 // SPI_TX_FIFO_0
#define SPI1_LAST_REG 0x0108 // SPI_TX_FIFO_0
#define SPI2_FIRST_REG 0x0188 // SPI_RX_FIFO_0
#define SPI2_LAST_REG 0x01a4 // SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARSPI_H_INC
