//
// Copyright (c) 2021 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARPADCTL_AO_H_INC
#define ARPADCTL_AO_H_INC
#define NV_MOBILE_ARPADCTL_AO_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARPADCTL_AO_H_SCRREG_NOMENCLATURE INFERRED


// Register PADCTL_AO_TOUCH_CLK_0
#define PADCTL_AO_TOUCH_CLK_0                   MK_ADDR_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_SECURE                    0x0
#define PADCTL_AO_TOUCH_CLK_0_DUAL                      0x0
#define PADCTL_AO_TOUCH_CLK_0_SCR                       SCR_TOUCH_CLK_0
#define PADCTL_AO_TOUCH_CLK_0_SCRREG                    PADCTL_AO_SCR_SCR_TOUCH_CLK_0
#define PADCTL_AO_TOUCH_CLK_0_WORD_COUNT                        0x1
#define PADCTL_AO_TOUCH_CLK_0_RESET_VAL                         MK_MASK_CONST(0x430)
#define PADCTL_AO_TOUCH_CLK_0_RESET_MASK                        MK_MASK_CONST(0x15ff)
#define PADCTL_AO_TOUCH_CLK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_READ_MASK                         MK_MASK_CONST(0x15ff)
#define PADCTL_AO_TOUCH_CLK_0_WRITE_MASK                        MK_MASK_CONST(0x15ff)
#define PADCTL_AO_TOUCH_CLK_0_PM_SHIFT                  MK_SHIFT_CONST(0)
#define PADCTL_AO_TOUCH_CLK_0_PM_FIELD                  MK_FIELD_CONST(0x3, PADCTL_AO_TOUCH_CLK_0_PM_SHIFT)
#define PADCTL_AO_TOUCH_CLK_0_PM_RANGE                  1:0
#define PADCTL_AO_TOUCH_CLK_0_PM_MSB                    MK_SHIFT_CONST(1)
#define PADCTL_AO_TOUCH_CLK_0_PM_LSB                    MK_SHIFT_CONST(0)
#define PADCTL_AO_TOUCH_CLK_0_PM_WOFFSET                        0x0
#define PADCTL_AO_TOUCH_CLK_0_PM_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_PM_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define PADCTL_AO_TOUCH_CLK_0_PM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_PM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_PM_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_PM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_PM_INIT_ENUM                      GP
#define PADCTL_AO_TOUCH_CLK_0_PM_GP                     MK_ENUM_CONST(0)
#define PADCTL_AO_TOUCH_CLK_0_PM_TOUCH                  MK_ENUM_CONST(1)
#define PADCTL_AO_TOUCH_CLK_0_PM_RSVD2                  MK_ENUM_CONST(2)
#define PADCTL_AO_TOUCH_CLK_0_PM_RSVD3                  MK_ENUM_CONST(3)

#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_SHIFT                 MK_SHIFT_CONST(10)
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_RANGE                 10:10
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_MSB                   MK_SHIFT_CONST(10)
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_LSB                   MK_SHIFT_CONST(10)
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_WOFFSET                       0x0
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_DEFAULT                       MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_INIT_ENUM                     SFIO
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_GPIO                  MK_ENUM_CONST(0)
#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_SFIO                  MK_ENUM_CONST(1)

#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_SHIFT                    MK_SHIFT_CONST(4)
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_FIELD                    MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_TRISTATE_SHIFT)
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_RANGE                    4:4
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_MSB                      MK_SHIFT_CONST(4)
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_LSB                      MK_SHIFT_CONST(4)
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_WOFFSET                  0x0
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_DEFAULT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_INIT_ENUM                        TRISTATE
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_PASSTHROUGH                      MK_ENUM_CONST(0)
#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_TRISTATE                 MK_ENUM_CONST(1)

#define PADCTL_AO_TOUCH_CLK_0_PUPD_SHIFT                        MK_SHIFT_CONST(2)
#define PADCTL_AO_TOUCH_CLK_0_PUPD_FIELD                        MK_FIELD_CONST(0x3, PADCTL_AO_TOUCH_CLK_0_PUPD_SHIFT)
#define PADCTL_AO_TOUCH_CLK_0_PUPD_RANGE                        3:2
#define PADCTL_AO_TOUCH_CLK_0_PUPD_MSB                  MK_SHIFT_CONST(3)
#define PADCTL_AO_TOUCH_CLK_0_PUPD_LSB                  MK_SHIFT_CONST(2)
#define PADCTL_AO_TOUCH_CLK_0_PUPD_WOFFSET                      0x0
#define PADCTL_AO_TOUCH_CLK_0_PUPD_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_PUPD_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define PADCTL_AO_TOUCH_CLK_0_PUPD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_PUPD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_PUPD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_PUPD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_PUPD_INIT_ENUM                    NONE
#define PADCTL_AO_TOUCH_CLK_0_PUPD_NONE                 MK_ENUM_CONST(0)
#define PADCTL_AO_TOUCH_CLK_0_PUPD_PULL_DOWN                    MK_ENUM_CONST(1)
#define PADCTL_AO_TOUCH_CLK_0_PUPD_PULL_UP                      MK_ENUM_CONST(2)
#define PADCTL_AO_TOUCH_CLK_0_PUPD_RSVD                 MK_ENUM_CONST(3)

#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_SHIFT                     MK_SHIFT_CONST(6)
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_E_INPUT_SHIFT)
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_RANGE                     6:6
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_MSB                       MK_SHIFT_CONST(6)
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_LSB                       MK_SHIFT_CONST(6)
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_WOFFSET                   0x0
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_INIT_ENUM                 DISABLE
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_DISABLE                   MK_ENUM_CONST(0)
#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_ENABLE                    MK_ENUM_CONST(1)

#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_SHIFT                      MK_SHIFT_CONST(7)
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_E_LPBK_SHIFT)
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_RANGE                      7:7
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_MSB                        MK_SHIFT_CONST(7)
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_LSB                        MK_SHIFT_CONST(7)
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_WOFFSET                    0x0
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_INIT_ENUM                  DISABLE
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_SHIFT                      MK_SHIFT_CONST(8)
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_E_LPDR_SHIFT)
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_RANGE                      8:8
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_MSB                        MK_SHIFT_CONST(8)
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_LSB                        MK_SHIFT_CONST(8)
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_WOFFSET                    0x0
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_INIT_ENUM                  DISABLE
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_SHIFT                     MK_SHIFT_CONST(5)
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_E_IO_HV_SHIFT)
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_RANGE                     5:5
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_MSB                       MK_SHIFT_CONST(5)
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_LSB                       MK_SHIFT_CONST(5)
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_WOFFSET                   0x0
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_DEFAULT                   MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_INIT_ENUM                 ENABLE
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_DISABLE                   MK_ENUM_CONST(0)
#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_ENABLE                    MK_ENUM_CONST(1)

#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_SHIFT                     MK_SHIFT_CONST(12)
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_E_SCHMT_SHIFT)
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_RANGE                     12:12
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_MSB                       MK_SHIFT_CONST(12)
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_LSB                       MK_SHIFT_CONST(12)
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_WOFFSET                   0x0
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_INIT_ENUM                 DISABLE
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_DISABLE                   MK_ENUM_CONST(0)
#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_ENABLE                    MK_ENUM_CONST(1)


// Register PADCTL_AO_CFG2TMC_TOUCH_CLK_0
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0                   MK_ADDR_CONST(0x4)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_SECURE                    0x0
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_DUAL                      0x0
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_SCR                       SCR_TOUCH_CLK_0
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_SCRREG                    PADCTL_AO_SCR_SCR_TOUCH_CLK_0
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_WORD_COUNT                        0x1
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_RESET_MASK                        MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_READ_MASK                         MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_WRITE_MASK                        MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_SHIFT                       MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_FIELD                       MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_RANGE                       16:12
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_MSB                 MK_SHIFT_CONST(16)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_LSB                 MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_WOFFSET                     0x0
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_SHIFT                       MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_FIELD                       MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_RANGE                       24:20
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_MSB                 MK_SHIFT_CONST(24)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_LSB                 MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_WOFFSET                     0x0
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register PADCTL_AO_UART3_RX_0
#define PADCTL_AO_UART3_RX_0                    MK_ADDR_CONST(0x8)
#define PADCTL_AO_UART3_RX_0_SECURE                     0x0
#define PADCTL_AO_UART3_RX_0_DUAL                       0x0
#define PADCTL_AO_UART3_RX_0_SCR                        SCR_UART3_RX_0
#define PADCTL_AO_UART3_RX_0_SCRREG                     PADCTL_AO_SCR_SCR_UART3_RX_0
#define PADCTL_AO_UART3_RX_0_WORD_COUNT                         0x1
#define PADCTL_AO_UART3_RX_0_RESET_VAL                  MK_MASK_CONST(0x474)
#define PADCTL_AO_UART3_RX_0_RESET_MASK                         MK_MASK_CONST(0x15ff)
#define PADCTL_AO_UART3_RX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_READ_MASK                  MK_MASK_CONST(0x15ff)
#define PADCTL_AO_UART3_RX_0_WRITE_MASK                         MK_MASK_CONST(0x15ff)
#define PADCTL_AO_UART3_RX_0_PM_SHIFT                   MK_SHIFT_CONST(0)
#define PADCTL_AO_UART3_RX_0_PM_FIELD                   MK_FIELD_CONST(0x3, PADCTL_AO_UART3_RX_0_PM_SHIFT)
#define PADCTL_AO_UART3_RX_0_PM_RANGE                   1:0
#define PADCTL_AO_UART3_RX_0_PM_MSB                     MK_SHIFT_CONST(1)
#define PADCTL_AO_UART3_RX_0_PM_LSB                     MK_SHIFT_CONST(0)
#define PADCTL_AO_UART3_RX_0_PM_WOFFSET                 0x0
#define PADCTL_AO_UART3_RX_0_PM_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_PM_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define PADCTL_AO_UART3_RX_0_PM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_PM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_PM_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_PM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_PM_INIT_ENUM                       UARTC
#define PADCTL_AO_UART3_RX_0_PM_UARTC                   MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_RX_0_PM_UARTJ                   MK_ENUM_CONST(1)
#define PADCTL_AO_UART3_RX_0_PM_RSVD2                   MK_ENUM_CONST(2)
#define PADCTL_AO_UART3_RX_0_PM_RSVD3                   MK_ENUM_CONST(3)

#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_SHIFT                  MK_SHIFT_CONST(10)
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_RANGE                  10:10
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_MSB                    MK_SHIFT_CONST(10)
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_LSB                    MK_SHIFT_CONST(10)
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_WOFFSET                        0x0
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_INIT_ENUM                      SFIO
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_GPIO                   MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_SFIO                   MK_ENUM_CONST(1)

#define PADCTL_AO_UART3_RX_0_TRISTATE_SHIFT                     MK_SHIFT_CONST(4)
#define PADCTL_AO_UART3_RX_0_TRISTATE_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_TRISTATE_SHIFT)
#define PADCTL_AO_UART3_RX_0_TRISTATE_RANGE                     4:4
#define PADCTL_AO_UART3_RX_0_TRISTATE_MSB                       MK_SHIFT_CONST(4)
#define PADCTL_AO_UART3_RX_0_TRISTATE_LSB                       MK_SHIFT_CONST(4)
#define PADCTL_AO_UART3_RX_0_TRISTATE_WOFFSET                   0x0
#define PADCTL_AO_UART3_RX_0_TRISTATE_DEFAULT                   MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_TRISTATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_TRISTATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_TRISTATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_TRISTATE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_TRISTATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_TRISTATE_INIT_ENUM                 TRISTATE
#define PADCTL_AO_UART3_RX_0_TRISTATE_PASSTHROUGH                       MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_RX_0_TRISTATE_TRISTATE                  MK_ENUM_CONST(1)

#define PADCTL_AO_UART3_RX_0_PUPD_SHIFT                 MK_SHIFT_CONST(2)
#define PADCTL_AO_UART3_RX_0_PUPD_FIELD                 MK_FIELD_CONST(0x3, PADCTL_AO_UART3_RX_0_PUPD_SHIFT)
#define PADCTL_AO_UART3_RX_0_PUPD_RANGE                 3:2
#define PADCTL_AO_UART3_RX_0_PUPD_MSB                   MK_SHIFT_CONST(3)
#define PADCTL_AO_UART3_RX_0_PUPD_LSB                   MK_SHIFT_CONST(2)
#define PADCTL_AO_UART3_RX_0_PUPD_WOFFSET                       0x0
#define PADCTL_AO_UART3_RX_0_PUPD_DEFAULT                       MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_PUPD_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PADCTL_AO_UART3_RX_0_PUPD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_PUPD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_PUPD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_PUPD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_PUPD_INIT_ENUM                     PULL_DOWN
#define PADCTL_AO_UART3_RX_0_PUPD_NONE                  MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_RX_0_PUPD_PULL_DOWN                     MK_ENUM_CONST(1)
#define PADCTL_AO_UART3_RX_0_PUPD_PULL_UP                       MK_ENUM_CONST(2)
#define PADCTL_AO_UART3_RX_0_PUPD_RSVD                  MK_ENUM_CONST(3)

#define PADCTL_AO_UART3_RX_0_E_INPUT_SHIFT                      MK_SHIFT_CONST(6)
#define PADCTL_AO_UART3_RX_0_E_INPUT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_E_INPUT_SHIFT)
#define PADCTL_AO_UART3_RX_0_E_INPUT_RANGE                      6:6
#define PADCTL_AO_UART3_RX_0_E_INPUT_MSB                        MK_SHIFT_CONST(6)
#define PADCTL_AO_UART3_RX_0_E_INPUT_LSB                        MK_SHIFT_CONST(6)
#define PADCTL_AO_UART3_RX_0_E_INPUT_WOFFSET                    0x0
#define PADCTL_AO_UART3_RX_0_E_INPUT_DEFAULT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_INPUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_INPUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_E_INPUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_E_INPUT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_INPUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_INPUT_INIT_ENUM                  ENABLE
#define PADCTL_AO_UART3_RX_0_E_INPUT_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_RX_0_E_INPUT_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_UART3_RX_0_E_LPBK_SHIFT                       MK_SHIFT_CONST(7)
#define PADCTL_AO_UART3_RX_0_E_LPBK_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_E_LPBK_SHIFT)
#define PADCTL_AO_UART3_RX_0_E_LPBK_RANGE                       7:7
#define PADCTL_AO_UART3_RX_0_E_LPBK_MSB                 MK_SHIFT_CONST(7)
#define PADCTL_AO_UART3_RX_0_E_LPBK_LSB                 MK_SHIFT_CONST(7)
#define PADCTL_AO_UART3_RX_0_E_LPBK_WOFFSET                     0x0
#define PADCTL_AO_UART3_RX_0_E_LPBK_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_E_LPBK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_LPBK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_E_LPBK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_E_LPBK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_LPBK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_LPBK_INIT_ENUM                   DISABLE
#define PADCTL_AO_UART3_RX_0_E_LPBK_DISABLE                     MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_RX_0_E_LPBK_ENABLE                      MK_ENUM_CONST(1)

#define PADCTL_AO_UART3_RX_0_E_LPDR_SHIFT                       MK_SHIFT_CONST(8)
#define PADCTL_AO_UART3_RX_0_E_LPDR_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_E_LPDR_SHIFT)
#define PADCTL_AO_UART3_RX_0_E_LPDR_RANGE                       8:8
#define PADCTL_AO_UART3_RX_0_E_LPDR_MSB                 MK_SHIFT_CONST(8)
#define PADCTL_AO_UART3_RX_0_E_LPDR_LSB                 MK_SHIFT_CONST(8)
#define PADCTL_AO_UART3_RX_0_E_LPDR_WOFFSET                     0x0
#define PADCTL_AO_UART3_RX_0_E_LPDR_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_E_LPDR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_LPDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_E_LPDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_E_LPDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_LPDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_LPDR_INIT_ENUM                   DISABLE
#define PADCTL_AO_UART3_RX_0_E_LPDR_DISABLE                     MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_RX_0_E_LPDR_ENABLE                      MK_ENUM_CONST(1)

#define PADCTL_AO_UART3_RX_0_E_IO_HV_SHIFT                      MK_SHIFT_CONST(5)
#define PADCTL_AO_UART3_RX_0_E_IO_HV_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_E_IO_HV_SHIFT)
#define PADCTL_AO_UART3_RX_0_E_IO_HV_RANGE                      5:5
#define PADCTL_AO_UART3_RX_0_E_IO_HV_MSB                        MK_SHIFT_CONST(5)
#define PADCTL_AO_UART3_RX_0_E_IO_HV_LSB                        MK_SHIFT_CONST(5)
#define PADCTL_AO_UART3_RX_0_E_IO_HV_WOFFSET                    0x0
#define PADCTL_AO_UART3_RX_0_E_IO_HV_DEFAULT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_IO_HV_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_IO_HV_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_E_IO_HV_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_E_IO_HV_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_IO_HV_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_IO_HV_INIT_ENUM                  ENABLE
#define PADCTL_AO_UART3_RX_0_E_IO_HV_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_RX_0_E_IO_HV_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_UART3_RX_0_E_SCHMT_SHIFT                      MK_SHIFT_CONST(12)
#define PADCTL_AO_UART3_RX_0_E_SCHMT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_E_SCHMT_SHIFT)
#define PADCTL_AO_UART3_RX_0_E_SCHMT_RANGE                      12:12
#define PADCTL_AO_UART3_RX_0_E_SCHMT_MSB                        MK_SHIFT_CONST(12)
#define PADCTL_AO_UART3_RX_0_E_SCHMT_LSB                        MK_SHIFT_CONST(12)
#define PADCTL_AO_UART3_RX_0_E_SCHMT_WOFFSET                    0x0
#define PADCTL_AO_UART3_RX_0_E_SCHMT_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_E_SCHMT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_SCHMT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_E_SCHMT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_RX_0_E_SCHMT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_SCHMT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_RX_0_E_SCHMT_INIT_ENUM                  DISABLE
#define PADCTL_AO_UART3_RX_0_E_SCHMT_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_RX_0_E_SCHMT_ENABLE                     MK_ENUM_CONST(1)


// Register PADCTL_AO_CFG2TMC_UART3_RX_0
#define PADCTL_AO_CFG2TMC_UART3_RX_0                    MK_ADDR_CONST(0xc)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_SECURE                     0x0
#define PADCTL_AO_CFG2TMC_UART3_RX_0_DUAL                       0x0
#define PADCTL_AO_CFG2TMC_UART3_RX_0_SCR                        SCR_UART3_RX_0
#define PADCTL_AO_CFG2TMC_UART3_RX_0_SCRREG                     PADCTL_AO_SCR_SCR_UART3_RX_0
#define PADCTL_AO_CFG2TMC_UART3_RX_0_WORD_COUNT                         0x1
#define PADCTL_AO_CFG2TMC_UART3_RX_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_RESET_MASK                         MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_READ_MASK                  MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_WRITE_MASK                         MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_SHIFT                        MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_RANGE                        16:12
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_MSB                  MK_SHIFT_CONST(16)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_LSB                  MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_WOFFSET                      0x0
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_SHIFT                        MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_RANGE                        24:20
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_MSB                  MK_SHIFT_CONST(24)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_LSB                  MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_WOFFSET                      0x0
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register PADCTL_AO_UART3_TX_0
#define PADCTL_AO_UART3_TX_0                    MK_ADDR_CONST(0x10)
#define PADCTL_AO_UART3_TX_0_SECURE                     0x0
#define PADCTL_AO_UART3_TX_0_DUAL                       0x0
#define PADCTL_AO_UART3_TX_0_SCR                        SCR_UART3_TX_0
#define PADCTL_AO_UART3_TX_0_SCRREG                     PADCTL_AO_SCR_SCR_UART3_TX_0
#define PADCTL_AO_UART3_TX_0_WORD_COUNT                         0x1
#define PADCTL_AO_UART3_TX_0_RESET_VAL                  MK_MASK_CONST(0x434)
#define PADCTL_AO_UART3_TX_0_RESET_MASK                         MK_MASK_CONST(0x15ff)
#define PADCTL_AO_UART3_TX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_READ_MASK                  MK_MASK_CONST(0x15ff)
#define PADCTL_AO_UART3_TX_0_WRITE_MASK                         MK_MASK_CONST(0x15ff)
#define PADCTL_AO_UART3_TX_0_PM_SHIFT                   MK_SHIFT_CONST(0)
#define PADCTL_AO_UART3_TX_0_PM_FIELD                   MK_FIELD_CONST(0x3, PADCTL_AO_UART3_TX_0_PM_SHIFT)
#define PADCTL_AO_UART3_TX_0_PM_RANGE                   1:0
#define PADCTL_AO_UART3_TX_0_PM_MSB                     MK_SHIFT_CONST(1)
#define PADCTL_AO_UART3_TX_0_PM_LSB                     MK_SHIFT_CONST(0)
#define PADCTL_AO_UART3_TX_0_PM_WOFFSET                 0x0
#define PADCTL_AO_UART3_TX_0_PM_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_PM_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define PADCTL_AO_UART3_TX_0_PM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_PM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_PM_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_PM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_PM_INIT_ENUM                       UARTC
#define PADCTL_AO_UART3_TX_0_PM_UARTC                   MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_TX_0_PM_UARTJ                   MK_ENUM_CONST(1)
#define PADCTL_AO_UART3_TX_0_PM_RSVD2                   MK_ENUM_CONST(2)
#define PADCTL_AO_UART3_TX_0_PM_RSVD3                   MK_ENUM_CONST(3)

#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_SHIFT                  MK_SHIFT_CONST(10)
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_RANGE                  10:10
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_MSB                    MK_SHIFT_CONST(10)
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_LSB                    MK_SHIFT_CONST(10)
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_WOFFSET                        0x0
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_INIT_ENUM                      SFIO
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_GPIO                   MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_SFIO                   MK_ENUM_CONST(1)

#define PADCTL_AO_UART3_TX_0_TRISTATE_SHIFT                     MK_SHIFT_CONST(4)
#define PADCTL_AO_UART3_TX_0_TRISTATE_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_TRISTATE_SHIFT)
#define PADCTL_AO_UART3_TX_0_TRISTATE_RANGE                     4:4
#define PADCTL_AO_UART3_TX_0_TRISTATE_MSB                       MK_SHIFT_CONST(4)
#define PADCTL_AO_UART3_TX_0_TRISTATE_LSB                       MK_SHIFT_CONST(4)
#define PADCTL_AO_UART3_TX_0_TRISTATE_WOFFSET                   0x0
#define PADCTL_AO_UART3_TX_0_TRISTATE_DEFAULT                   MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_TRISTATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_TRISTATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_TRISTATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_TRISTATE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_TRISTATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_TRISTATE_INIT_ENUM                 TRISTATE
#define PADCTL_AO_UART3_TX_0_TRISTATE_PASSTHROUGH                       MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_TX_0_TRISTATE_TRISTATE                  MK_ENUM_CONST(1)

#define PADCTL_AO_UART3_TX_0_PUPD_SHIFT                 MK_SHIFT_CONST(2)
#define PADCTL_AO_UART3_TX_0_PUPD_FIELD                 MK_FIELD_CONST(0x3, PADCTL_AO_UART3_TX_0_PUPD_SHIFT)
#define PADCTL_AO_UART3_TX_0_PUPD_RANGE                 3:2
#define PADCTL_AO_UART3_TX_0_PUPD_MSB                   MK_SHIFT_CONST(3)
#define PADCTL_AO_UART3_TX_0_PUPD_LSB                   MK_SHIFT_CONST(2)
#define PADCTL_AO_UART3_TX_0_PUPD_WOFFSET                       0x0
#define PADCTL_AO_UART3_TX_0_PUPD_DEFAULT                       MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_PUPD_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PADCTL_AO_UART3_TX_0_PUPD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_PUPD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_PUPD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_PUPD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_PUPD_INIT_ENUM                     PULL_DOWN
#define PADCTL_AO_UART3_TX_0_PUPD_NONE                  MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_TX_0_PUPD_PULL_DOWN                     MK_ENUM_CONST(1)
#define PADCTL_AO_UART3_TX_0_PUPD_PULL_UP                       MK_ENUM_CONST(2)
#define PADCTL_AO_UART3_TX_0_PUPD_RSVD                  MK_ENUM_CONST(3)

#define PADCTL_AO_UART3_TX_0_E_INPUT_SHIFT                      MK_SHIFT_CONST(6)
#define PADCTL_AO_UART3_TX_0_E_INPUT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_E_INPUT_SHIFT)
#define PADCTL_AO_UART3_TX_0_E_INPUT_RANGE                      6:6
#define PADCTL_AO_UART3_TX_0_E_INPUT_MSB                        MK_SHIFT_CONST(6)
#define PADCTL_AO_UART3_TX_0_E_INPUT_LSB                        MK_SHIFT_CONST(6)
#define PADCTL_AO_UART3_TX_0_E_INPUT_WOFFSET                    0x0
#define PADCTL_AO_UART3_TX_0_E_INPUT_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_INPUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_INPUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_INPUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_INPUT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_INPUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_INPUT_INIT_ENUM                  DISABLE
#define PADCTL_AO_UART3_TX_0_E_INPUT_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_TX_0_E_INPUT_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_UART3_TX_0_E_LPBK_SHIFT                       MK_SHIFT_CONST(7)
#define PADCTL_AO_UART3_TX_0_E_LPBK_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_E_LPBK_SHIFT)
#define PADCTL_AO_UART3_TX_0_E_LPBK_RANGE                       7:7
#define PADCTL_AO_UART3_TX_0_E_LPBK_MSB                 MK_SHIFT_CONST(7)
#define PADCTL_AO_UART3_TX_0_E_LPBK_LSB                 MK_SHIFT_CONST(7)
#define PADCTL_AO_UART3_TX_0_E_LPBK_WOFFSET                     0x0
#define PADCTL_AO_UART3_TX_0_E_LPBK_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_LPBK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_LPBK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_LPBK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_LPBK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_LPBK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_LPBK_INIT_ENUM                   DISABLE
#define PADCTL_AO_UART3_TX_0_E_LPBK_DISABLE                     MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_TX_0_E_LPBK_ENABLE                      MK_ENUM_CONST(1)

#define PADCTL_AO_UART3_TX_0_E_LPDR_SHIFT                       MK_SHIFT_CONST(8)
#define PADCTL_AO_UART3_TX_0_E_LPDR_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_E_LPDR_SHIFT)
#define PADCTL_AO_UART3_TX_0_E_LPDR_RANGE                       8:8
#define PADCTL_AO_UART3_TX_0_E_LPDR_MSB                 MK_SHIFT_CONST(8)
#define PADCTL_AO_UART3_TX_0_E_LPDR_LSB                 MK_SHIFT_CONST(8)
#define PADCTL_AO_UART3_TX_0_E_LPDR_WOFFSET                     0x0
#define PADCTL_AO_UART3_TX_0_E_LPDR_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_LPDR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_LPDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_LPDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_LPDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_LPDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_LPDR_INIT_ENUM                   DISABLE
#define PADCTL_AO_UART3_TX_0_E_LPDR_DISABLE                     MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_TX_0_E_LPDR_ENABLE                      MK_ENUM_CONST(1)

#define PADCTL_AO_UART3_TX_0_E_IO_HV_SHIFT                      MK_SHIFT_CONST(5)
#define PADCTL_AO_UART3_TX_0_E_IO_HV_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_E_IO_HV_SHIFT)
#define PADCTL_AO_UART3_TX_0_E_IO_HV_RANGE                      5:5
#define PADCTL_AO_UART3_TX_0_E_IO_HV_MSB                        MK_SHIFT_CONST(5)
#define PADCTL_AO_UART3_TX_0_E_IO_HV_LSB                        MK_SHIFT_CONST(5)
#define PADCTL_AO_UART3_TX_0_E_IO_HV_WOFFSET                    0x0
#define PADCTL_AO_UART3_TX_0_E_IO_HV_DEFAULT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_IO_HV_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_IO_HV_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_IO_HV_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_IO_HV_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_IO_HV_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_IO_HV_INIT_ENUM                  ENABLE
#define PADCTL_AO_UART3_TX_0_E_IO_HV_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_TX_0_E_IO_HV_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_UART3_TX_0_E_SCHMT_SHIFT                      MK_SHIFT_CONST(12)
#define PADCTL_AO_UART3_TX_0_E_SCHMT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_E_SCHMT_SHIFT)
#define PADCTL_AO_UART3_TX_0_E_SCHMT_RANGE                      12:12
#define PADCTL_AO_UART3_TX_0_E_SCHMT_MSB                        MK_SHIFT_CONST(12)
#define PADCTL_AO_UART3_TX_0_E_SCHMT_LSB                        MK_SHIFT_CONST(12)
#define PADCTL_AO_UART3_TX_0_E_SCHMT_WOFFSET                    0x0
#define PADCTL_AO_UART3_TX_0_E_SCHMT_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_SCHMT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_SCHMT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_SCHMT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_UART3_TX_0_E_SCHMT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_SCHMT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_UART3_TX_0_E_SCHMT_INIT_ENUM                  DISABLE
#define PADCTL_AO_UART3_TX_0_E_SCHMT_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_UART3_TX_0_E_SCHMT_ENABLE                     MK_ENUM_CONST(1)


// Register PADCTL_AO_CFG2TMC_UART3_TX_0
#define PADCTL_AO_CFG2TMC_UART3_TX_0                    MK_ADDR_CONST(0x14)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_SECURE                     0x0
#define PADCTL_AO_CFG2TMC_UART3_TX_0_DUAL                       0x0
#define PADCTL_AO_CFG2TMC_UART3_TX_0_SCR                        SCR_UART3_TX_0
#define PADCTL_AO_CFG2TMC_UART3_TX_0_SCRREG                     PADCTL_AO_SCR_SCR_UART3_TX_0
#define PADCTL_AO_CFG2TMC_UART3_TX_0_WORD_COUNT                         0x1
#define PADCTL_AO_CFG2TMC_UART3_TX_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_RESET_MASK                         MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_READ_MASK                  MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_WRITE_MASK                         MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_SHIFT                        MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_RANGE                        16:12
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_MSB                  MK_SHIFT_CONST(16)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_LSB                  MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_WOFFSET                      0x0
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_SHIFT                        MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_RANGE                        24:20
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_MSB                  MK_SHIFT_CONST(24)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_LSB                  MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_WOFFSET                      0x0
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register PADCTL_AO_GEN8_I2C_SDA_0
#define PADCTL_AO_GEN8_I2C_SDA_0                        MK_ADDR_CONST(0x18)
#define PADCTL_AO_GEN8_I2C_SDA_0_SECURE                         0x0
#define PADCTL_AO_GEN8_I2C_SDA_0_DUAL                   0x0
#define PADCTL_AO_GEN8_I2C_SDA_0_SCR                    SCR_GEN8_I2C_SDA_0
#define PADCTL_AO_GEN8_I2C_SDA_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN8_I2C_SDA_0
#define PADCTL_AO_GEN8_I2C_SDA_0_WORD_COUNT                     0x1
#define PADCTL_AO_GEN8_I2C_SDA_0_RESET_VAL                      MK_MASK_CONST(0x570)
#define PADCTL_AO_GEN8_I2C_SDA_0_RESET_MASK                     MK_MASK_CONST(0x15ff)
#define PADCTL_AO_GEN8_I2C_SDA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_READ_MASK                      MK_MASK_CONST(0x15ff)
#define PADCTL_AO_GEN8_I2C_SDA_0_WRITE_MASK                     MK_MASK_CONST(0x15ff)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_SHIFT                       MK_SHIFT_CONST(0)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_FIELD                       MK_FIELD_CONST(0x3, PADCTL_AO_GEN8_I2C_SDA_0_PM_SHIFT)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_RANGE                       1:0
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_MSB                 MK_SHIFT_CONST(1)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_LSB                 MK_SHIFT_CONST(0)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_WOFFSET                     0x0
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_INIT_ENUM                   I2C8
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_I2C8                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_RSVD1                       MK_ENUM_CONST(1)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_RSVD2                       MK_ENUM_CONST(2)
#define PADCTL_AO_GEN8_I2C_SDA_0_PM_RSVD3                       MK_ENUM_CONST(3)

#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_SHIFT                      MK_SHIFT_CONST(10)
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_MSB                        MK_SHIFT_CONST(10)
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_LSB                        MK_SHIFT_CONST(10)
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_DEFAULT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_GPIO                       MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_SFIO                       MK_ENUM_CONST(1)

#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_SHIFT                 MK_SHIFT_CONST(4)
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_SHIFT)
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_RANGE                 4:4
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_MSB                   MK_SHIFT_CONST(4)
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_LSB                   MK_SHIFT_CONST(4)
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_DEFAULT                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_PASSTHROUGH                   MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_TRISTATE                      MK_ENUM_CONST(1)

#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_SHIFT                     MK_SHIFT_CONST(2)
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_FIELD                     MK_FIELD_CONST(0x3, PADCTL_AO_GEN8_I2C_SDA_0_PUPD_SHIFT)
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_RANGE                     3:2
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_MSB                       MK_SHIFT_CONST(3)
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_LSB                       MK_SHIFT_CONST(2)
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_WOFFSET                   0x0
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_INIT_ENUM                 NONE
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_NONE                      MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_PULL_DOWN                 MK_ENUM_CONST(1)
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_PULL_UP                   MK_ENUM_CONST(2)
#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_RSVD                      MK_ENUM_CONST(3)

#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_SHIFT                  MK_SHIFT_CONST(6)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_SHIFT)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_RANGE                  6:6
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_MSB                    MK_SHIFT_CONST(6)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_LSB                    MK_SHIFT_CONST(6)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_INIT_ENUM                      ENABLE
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_DISABLE                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_ENABLE                 MK_ENUM_CONST(1)

#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_SHIFT                   MK_SHIFT_CONST(7)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_SHIFT)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_RANGE                   7:7
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_MSB                     MK_SHIFT_CONST(7)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_LSB                     MK_SHIFT_CONST(7)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_WOFFSET                 0x0
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_INIT_ENUM                       DISABLE
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_DISABLE                 MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_ENABLE                  MK_ENUM_CONST(1)

#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_SHIFT                   MK_SHIFT_CONST(8)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_SHIFT)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_RANGE                   8:8
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_MSB                     MK_SHIFT_CONST(8)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_LSB                     MK_SHIFT_CONST(8)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_DEFAULT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_INIT_ENUM                       ENABLE
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_DISABLE                 MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_ENABLE                  MK_ENUM_CONST(1)

#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_SHIFT                  MK_SHIFT_CONST(5)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_SHIFT)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_RANGE                  5:5
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_MSB                    MK_SHIFT_CONST(5)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_LSB                    MK_SHIFT_CONST(5)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_WOFFSET                        0x0
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_INIT_ENUM                      ENABLE
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_DISABLE                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_ENABLE                 MK_ENUM_CONST(1)

#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_SHIFT                  MK_SHIFT_CONST(12)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_SHIFT)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_RANGE                  12:12
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_MSB                    MK_SHIFT_CONST(12)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_LSB                    MK_SHIFT_CONST(12)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_INIT_ENUM                      DISABLE
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_DISABLE                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_ENABLE                 MK_ENUM_CONST(1)


// Register PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0                        MK_ADDR_CONST(0x1c)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_SECURE                         0x0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_DUAL                   0x0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_SCR                    SCR_GEN8_I2C_SDA_0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN8_I2C_SDA_0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_WORD_COUNT                     0x1
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_RESET_MASK                     MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_READ_MASK                      MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_WRITE_MASK                     MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_SHIFT                    MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_MSB                      MK_SHIFT_CONST(16)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_LSB                      MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_SHIFT                    MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_MSB                      MK_SHIFT_CONST(24)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_LSB                      MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register PADCTL_AO_GEN8_I2C_SCL_0
#define PADCTL_AO_GEN8_I2C_SCL_0                        MK_ADDR_CONST(0x20)
#define PADCTL_AO_GEN8_I2C_SCL_0_SECURE                         0x0
#define PADCTL_AO_GEN8_I2C_SCL_0_DUAL                   0x0
#define PADCTL_AO_GEN8_I2C_SCL_0_SCR                    SCR_GEN8_I2C_SCL_0
#define PADCTL_AO_GEN8_I2C_SCL_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN8_I2C_SCL_0
#define PADCTL_AO_GEN8_I2C_SCL_0_WORD_COUNT                     0x1
#define PADCTL_AO_GEN8_I2C_SCL_0_RESET_VAL                      MK_MASK_CONST(0x1570)
#define PADCTL_AO_GEN8_I2C_SCL_0_RESET_MASK                     MK_MASK_CONST(0x15ff)
#define PADCTL_AO_GEN8_I2C_SCL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_READ_MASK                      MK_MASK_CONST(0x15ff)
#define PADCTL_AO_GEN8_I2C_SCL_0_WRITE_MASK                     MK_MASK_CONST(0x15ff)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_SHIFT                       MK_SHIFT_CONST(0)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_FIELD                       MK_FIELD_CONST(0x3, PADCTL_AO_GEN8_I2C_SCL_0_PM_SHIFT)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_RANGE                       1:0
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_MSB                 MK_SHIFT_CONST(1)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_LSB                 MK_SHIFT_CONST(0)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_WOFFSET                     0x0
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_INIT_ENUM                   I2C8
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_I2C8                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_RSVD1                       MK_ENUM_CONST(1)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_RSVD2                       MK_ENUM_CONST(2)
#define PADCTL_AO_GEN8_I2C_SCL_0_PM_RSVD3                       MK_ENUM_CONST(3)

#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_SHIFT                      MK_SHIFT_CONST(10)
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_MSB                        MK_SHIFT_CONST(10)
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_LSB                        MK_SHIFT_CONST(10)
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_DEFAULT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_GPIO                       MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_SFIO                       MK_ENUM_CONST(1)

#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_SHIFT                 MK_SHIFT_CONST(4)
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_SHIFT)
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_RANGE                 4:4
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_MSB                   MK_SHIFT_CONST(4)
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_LSB                   MK_SHIFT_CONST(4)
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_DEFAULT                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_PASSTHROUGH                   MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_TRISTATE                      MK_ENUM_CONST(1)

#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_SHIFT                     MK_SHIFT_CONST(2)
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_FIELD                     MK_FIELD_CONST(0x3, PADCTL_AO_GEN8_I2C_SCL_0_PUPD_SHIFT)
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_RANGE                     3:2
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_MSB                       MK_SHIFT_CONST(3)
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_LSB                       MK_SHIFT_CONST(2)
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_WOFFSET                   0x0
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_INIT_ENUM                 NONE
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_NONE                      MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_PULL_DOWN                 MK_ENUM_CONST(1)
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_PULL_UP                   MK_ENUM_CONST(2)
#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_RSVD                      MK_ENUM_CONST(3)

#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_SHIFT                  MK_SHIFT_CONST(6)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_SHIFT)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_RANGE                  6:6
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_MSB                    MK_SHIFT_CONST(6)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_LSB                    MK_SHIFT_CONST(6)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_INIT_ENUM                      ENABLE
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_DISABLE                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_ENABLE                 MK_ENUM_CONST(1)

#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_SHIFT                   MK_SHIFT_CONST(7)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_SHIFT)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_RANGE                   7:7
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_MSB                     MK_SHIFT_CONST(7)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_LSB                     MK_SHIFT_CONST(7)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_WOFFSET                 0x0
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_INIT_ENUM                       DISABLE
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_DISABLE                 MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_ENABLE                  MK_ENUM_CONST(1)

#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_SHIFT                   MK_SHIFT_CONST(8)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_SHIFT)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_RANGE                   8:8
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_MSB                     MK_SHIFT_CONST(8)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_LSB                     MK_SHIFT_CONST(8)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_DEFAULT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_INIT_ENUM                       ENABLE
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_DISABLE                 MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_ENABLE                  MK_ENUM_CONST(1)

#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_SHIFT                  MK_SHIFT_CONST(5)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_SHIFT)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_RANGE                  5:5
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_MSB                    MK_SHIFT_CONST(5)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_LSB                    MK_SHIFT_CONST(5)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_WOFFSET                        0x0
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_INIT_ENUM                      ENABLE
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_DISABLE                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_ENABLE                 MK_ENUM_CONST(1)

#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_SHIFT                  MK_SHIFT_CONST(12)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_SHIFT)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_RANGE                  12:12
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_MSB                    MK_SHIFT_CONST(12)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_LSB                    MK_SHIFT_CONST(12)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_INIT_ENUM                      ENABLE
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_DISABLE                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_ENABLE                 MK_ENUM_CONST(1)


// Register PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0                        MK_ADDR_CONST(0x24)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_SECURE                         0x0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_DUAL                   0x0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_SCR                    SCR_GEN8_I2C_SCL_0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN8_I2C_SCL_0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_WORD_COUNT                     0x1
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_RESET_MASK                     MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_READ_MASK                      MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_WRITE_MASK                     MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_SHIFT                    MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_MSB                      MK_SHIFT_CONST(16)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_LSB                      MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_SHIFT                    MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_MSB                      MK_SHIFT_CONST(24)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_LSB                      MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register PADCTL_AO_SPI2_MOSI_0
#define PADCTL_AO_SPI2_MOSI_0                   MK_ADDR_CONST(0x28)
#define PADCTL_AO_SPI2_MOSI_0_SECURE                    0x0
#define PADCTL_AO_SPI2_MOSI_0_DUAL                      0x0
#define PADCTL_AO_SPI2_MOSI_0_SCR                       SCR_SPI2_MOSI_0
#define PADCTL_AO_SPI2_MOSI_0_SCRREG                    PADCTL_AO_SCR_SCR_SPI2_MOSI_0
#define PADCTL_AO_SPI2_MOSI_0_WORD_COUNT                        0x1
#define PADCTL_AO_SPI2_MOSI_0_RESET_VAL                         MK_MASK_CONST(0x474)
#define PADCTL_AO_SPI2_MOSI_0_RESET_MASK                        MK_MASK_CONST(0x15ff)
#define PADCTL_AO_SPI2_MOSI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_READ_MASK                         MK_MASK_CONST(0x15ff)
#define PADCTL_AO_SPI2_MOSI_0_WRITE_MASK                        MK_MASK_CONST(0x15ff)
#define PADCTL_AO_SPI2_MOSI_0_PM_SHIFT                  MK_SHIFT_CONST(0)
#define PADCTL_AO_SPI2_MOSI_0_PM_FIELD                  MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_MOSI_0_PM_SHIFT)
#define PADCTL_AO_SPI2_MOSI_0_PM_RANGE                  1:0
#define PADCTL_AO_SPI2_MOSI_0_PM_MSB                    MK_SHIFT_CONST(1)
#define PADCTL_AO_SPI2_MOSI_0_PM_LSB                    MK_SHIFT_CONST(0)
#define PADCTL_AO_SPI2_MOSI_0_PM_WOFFSET                        0x0
#define PADCTL_AO_SPI2_MOSI_0_PM_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_PM_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define PADCTL_AO_SPI2_MOSI_0_PM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_PM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_PM_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_PM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_PM_INIT_ENUM                      SPI2
#define PADCTL_AO_SPI2_MOSI_0_PM_SPI2                   MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MOSI_0_PM_RSVD1                  MK_ENUM_CONST(1)
#define PADCTL_AO_SPI2_MOSI_0_PM_RSVD2                  MK_ENUM_CONST(2)
#define PADCTL_AO_SPI2_MOSI_0_PM_RSVD3                  MK_ENUM_CONST(3)

#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_SHIFT                 MK_SHIFT_CONST(10)
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_RANGE                 10:10
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_MSB                   MK_SHIFT_CONST(10)
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_LSB                   MK_SHIFT_CONST(10)
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_WOFFSET                       0x0
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_DEFAULT                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_INIT_ENUM                     SFIO
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_GPIO                  MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_SFIO                  MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_SHIFT                    MK_SHIFT_CONST(4)
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_FIELD                    MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_TRISTATE_SHIFT)
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_RANGE                    4:4
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_MSB                      MK_SHIFT_CONST(4)
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_LSB                      MK_SHIFT_CONST(4)
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_WOFFSET                  0x0
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_DEFAULT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_INIT_ENUM                        TRISTATE
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_PASSTHROUGH                      MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_TRISTATE                 MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_MOSI_0_PUPD_SHIFT                        MK_SHIFT_CONST(2)
#define PADCTL_AO_SPI2_MOSI_0_PUPD_FIELD                        MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_MOSI_0_PUPD_SHIFT)
#define PADCTL_AO_SPI2_MOSI_0_PUPD_RANGE                        3:2
#define PADCTL_AO_SPI2_MOSI_0_PUPD_MSB                  MK_SHIFT_CONST(3)
#define PADCTL_AO_SPI2_MOSI_0_PUPD_LSB                  MK_SHIFT_CONST(2)
#define PADCTL_AO_SPI2_MOSI_0_PUPD_WOFFSET                      0x0
#define PADCTL_AO_SPI2_MOSI_0_PUPD_DEFAULT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_PUPD_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define PADCTL_AO_SPI2_MOSI_0_PUPD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_PUPD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_PUPD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_PUPD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_PUPD_INIT_ENUM                    PULL_DOWN
#define PADCTL_AO_SPI2_MOSI_0_PUPD_NONE                 MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MOSI_0_PUPD_PULL_DOWN                    MK_ENUM_CONST(1)
#define PADCTL_AO_SPI2_MOSI_0_PUPD_PULL_UP                      MK_ENUM_CONST(2)
#define PADCTL_AO_SPI2_MOSI_0_PUPD_RSVD                 MK_ENUM_CONST(3)

#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_SHIFT                     MK_SHIFT_CONST(6)
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_E_INPUT_SHIFT)
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_RANGE                     6:6
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_MSB                       MK_SHIFT_CONST(6)
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_LSB                       MK_SHIFT_CONST(6)
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_WOFFSET                   0x0
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_DEFAULT                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_INIT_ENUM                 ENABLE
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_DISABLE                   MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_ENABLE                    MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_SHIFT                      MK_SHIFT_CONST(7)
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_E_LPBK_SHIFT)
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_RANGE                      7:7
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_MSB                        MK_SHIFT_CONST(7)
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_LSB                        MK_SHIFT_CONST(7)
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_WOFFSET                    0x0
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_INIT_ENUM                  DISABLE
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_SHIFT                      MK_SHIFT_CONST(8)
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_E_LPDR_SHIFT)
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_RANGE                      8:8
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_MSB                        MK_SHIFT_CONST(8)
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_LSB                        MK_SHIFT_CONST(8)
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_WOFFSET                    0x0
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_INIT_ENUM                  DISABLE
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_SHIFT                     MK_SHIFT_CONST(5)
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_E_IO_HV_SHIFT)
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_RANGE                     5:5
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_MSB                       MK_SHIFT_CONST(5)
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_LSB                       MK_SHIFT_CONST(5)
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_WOFFSET                   0x0
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_DEFAULT                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_INIT_ENUM                 ENABLE
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_DISABLE                   MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_ENABLE                    MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_SHIFT                     MK_SHIFT_CONST(12)
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_E_SCHMT_SHIFT)
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_RANGE                     12:12
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_MSB                       MK_SHIFT_CONST(12)
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_LSB                       MK_SHIFT_CONST(12)
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_WOFFSET                   0x0
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_INIT_ENUM                 DISABLE
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_DISABLE                   MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_ENABLE                    MK_ENUM_CONST(1)


// Register PADCTL_AO_CFG2TMC_SPI2_MOSI_0
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0                   MK_ADDR_CONST(0x2c)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_SECURE                    0x0
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_DUAL                      0x0
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_SCR                       SCR_SPI2_MOSI_0
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_SCRREG                    PADCTL_AO_SCR_SCR_SPI2_MOSI_0
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_WORD_COUNT                        0x1
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_RESET_MASK                        MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_READ_MASK                         MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_WRITE_MASK                        MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_SHIFT                       MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_FIELD                       MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_RANGE                       16:12
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_MSB                 MK_SHIFT_CONST(16)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_LSB                 MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_WOFFSET                     0x0
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_SHIFT                       MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_FIELD                       MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_RANGE                       24:20
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_MSB                 MK_SHIFT_CONST(24)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_LSB                 MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_WOFFSET                     0x0
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register PADCTL_AO_GEN2_I2C_SCL_0
#define PADCTL_AO_GEN2_I2C_SCL_0                        MK_ADDR_CONST(0x30)
#define PADCTL_AO_GEN2_I2C_SCL_0_SECURE                         0x0
#define PADCTL_AO_GEN2_I2C_SCL_0_DUAL                   0x0
#define PADCTL_AO_GEN2_I2C_SCL_0_SCR                    SCR_GEN2_I2C_SCL_0
#define PADCTL_AO_GEN2_I2C_SCL_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN2_I2C_SCL_0
#define PADCTL_AO_GEN2_I2C_SCL_0_WORD_COUNT                     0x1
#define PADCTL_AO_GEN2_I2C_SCL_0_RESET_VAL                      MK_MASK_CONST(0x1570)
#define PADCTL_AO_GEN2_I2C_SCL_0_RESET_MASK                     MK_MASK_CONST(0x15ff)
#define PADCTL_AO_GEN2_I2C_SCL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_READ_MASK                      MK_MASK_CONST(0x15ff)
#define PADCTL_AO_GEN2_I2C_SCL_0_WRITE_MASK                     MK_MASK_CONST(0x15ff)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_SHIFT                       MK_SHIFT_CONST(0)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_FIELD                       MK_FIELD_CONST(0x3, PADCTL_AO_GEN2_I2C_SCL_0_PM_SHIFT)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_RANGE                       1:0
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_MSB                 MK_SHIFT_CONST(1)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_LSB                 MK_SHIFT_CONST(0)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_WOFFSET                     0x0
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_INIT_ENUM                   I2C2
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_I2C2                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_RSVD1                       MK_ENUM_CONST(1)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_RSVD2                       MK_ENUM_CONST(2)
#define PADCTL_AO_GEN2_I2C_SCL_0_PM_RSVD3                       MK_ENUM_CONST(3)

#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_SHIFT                      MK_SHIFT_CONST(10)
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_MSB                        MK_SHIFT_CONST(10)
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_LSB                        MK_SHIFT_CONST(10)
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_DEFAULT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_GPIO                       MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_SFIO                       MK_ENUM_CONST(1)

#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_SHIFT                 MK_SHIFT_CONST(4)
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_SHIFT)
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_RANGE                 4:4
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_MSB                   MK_SHIFT_CONST(4)
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_LSB                   MK_SHIFT_CONST(4)
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_DEFAULT                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_PASSTHROUGH                   MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_TRISTATE                      MK_ENUM_CONST(1)

#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_SHIFT                     MK_SHIFT_CONST(2)
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_FIELD                     MK_FIELD_CONST(0x3, PADCTL_AO_GEN2_I2C_SCL_0_PUPD_SHIFT)
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_RANGE                     3:2
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_MSB                       MK_SHIFT_CONST(3)
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_LSB                       MK_SHIFT_CONST(2)
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_WOFFSET                   0x0
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_INIT_ENUM                 NONE
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_NONE                      MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_PULL_DOWN                 MK_ENUM_CONST(1)
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_PULL_UP                   MK_ENUM_CONST(2)
#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_RSVD                      MK_ENUM_CONST(3)

#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_SHIFT                  MK_SHIFT_CONST(6)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_SHIFT)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_RANGE                  6:6
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_MSB                    MK_SHIFT_CONST(6)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_LSB                    MK_SHIFT_CONST(6)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_INIT_ENUM                      ENABLE
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_DISABLE                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_ENABLE                 MK_ENUM_CONST(1)

#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_SHIFT                   MK_SHIFT_CONST(7)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_SHIFT)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_RANGE                   7:7
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_MSB                     MK_SHIFT_CONST(7)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_LSB                     MK_SHIFT_CONST(7)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_WOFFSET                 0x0
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_INIT_ENUM                       DISABLE
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_DISABLE                 MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_ENABLE                  MK_ENUM_CONST(1)

#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_SHIFT                   MK_SHIFT_CONST(8)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_SHIFT)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_RANGE                   8:8
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_MSB                     MK_SHIFT_CONST(8)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_LSB                     MK_SHIFT_CONST(8)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_DEFAULT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_INIT_ENUM                       ENABLE
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_DISABLE                 MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_ENABLE                  MK_ENUM_CONST(1)

#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_SHIFT                  MK_SHIFT_CONST(5)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_SHIFT)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_RANGE                  5:5
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_MSB                    MK_SHIFT_CONST(5)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_LSB                    MK_SHIFT_CONST(5)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_WOFFSET                        0x0
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_INIT_ENUM                      ENABLE
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_DISABLE                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_ENABLE                 MK_ENUM_CONST(1)

#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_SHIFT                  MK_SHIFT_CONST(12)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_SHIFT)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_RANGE                  12:12
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_MSB                    MK_SHIFT_CONST(12)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_LSB                    MK_SHIFT_CONST(12)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_INIT_ENUM                      ENABLE
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_DISABLE                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_ENABLE                 MK_ENUM_CONST(1)


// Register PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0                        MK_ADDR_CONST(0x34)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_SECURE                         0x0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_DUAL                   0x0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_SCR                    SCR_GEN2_I2C_SCL_0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN2_I2C_SCL_0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_WORD_COUNT                     0x1
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_RESET_MASK                     MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_READ_MASK                      MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_WRITE_MASK                     MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_SHIFT                    MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_MSB                      MK_SHIFT_CONST(16)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_LSB                      MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_SHIFT                    MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_MSB                      MK_SHIFT_CONST(24)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_LSB                      MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register PADCTL_AO_SPI2_CS0_0
#define PADCTL_AO_SPI2_CS0_0                    MK_ADDR_CONST(0x38)
#define PADCTL_AO_SPI2_CS0_0_SECURE                     0x0
#define PADCTL_AO_SPI2_CS0_0_DUAL                       0x0
#define PADCTL_AO_SPI2_CS0_0_SCR                        SCR_SPI2_CS0_0
#define PADCTL_AO_SPI2_CS0_0_SCRREG                     PADCTL_AO_SCR_SCR_SPI2_CS0_0
#define PADCTL_AO_SPI2_CS0_0_WORD_COUNT                         0x1
#define PADCTL_AO_SPI2_CS0_0_RESET_VAL                  MK_MASK_CONST(0x470)
#define PADCTL_AO_SPI2_CS0_0_RESET_MASK                         MK_MASK_CONST(0x15ff)
#define PADCTL_AO_SPI2_CS0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_READ_MASK                  MK_MASK_CONST(0x15ff)
#define PADCTL_AO_SPI2_CS0_0_WRITE_MASK                         MK_MASK_CONST(0x15ff)
#define PADCTL_AO_SPI2_CS0_0_PM_SHIFT                   MK_SHIFT_CONST(0)
#define PADCTL_AO_SPI2_CS0_0_PM_FIELD                   MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_CS0_0_PM_SHIFT)
#define PADCTL_AO_SPI2_CS0_0_PM_RANGE                   1:0
#define PADCTL_AO_SPI2_CS0_0_PM_MSB                     MK_SHIFT_CONST(1)
#define PADCTL_AO_SPI2_CS0_0_PM_LSB                     MK_SHIFT_CONST(0)
#define PADCTL_AO_SPI2_CS0_0_PM_WOFFSET                 0x0
#define PADCTL_AO_SPI2_CS0_0_PM_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_PM_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define PADCTL_AO_SPI2_CS0_0_PM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_PM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_PM_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_PM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_PM_INIT_ENUM                       SPI2
#define PADCTL_AO_SPI2_CS0_0_PM_SPI2                    MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_CS0_0_PM_RSVD1                   MK_ENUM_CONST(1)
#define PADCTL_AO_SPI2_CS0_0_PM_RSVD2                   MK_ENUM_CONST(2)
#define PADCTL_AO_SPI2_CS0_0_PM_RSVD3                   MK_ENUM_CONST(3)

#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_SHIFT                  MK_SHIFT_CONST(10)
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_RANGE                  10:10
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_MSB                    MK_SHIFT_CONST(10)
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_LSB                    MK_SHIFT_CONST(10)
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_WOFFSET                        0x0
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_INIT_ENUM                      SFIO
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_GPIO                   MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_SFIO                   MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_CS0_0_TRISTATE_SHIFT                     MK_SHIFT_CONST(4)
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_TRISTATE_SHIFT)
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_RANGE                     4:4
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_MSB                       MK_SHIFT_CONST(4)
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_LSB                       MK_SHIFT_CONST(4)
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_WOFFSET                   0x0
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_DEFAULT                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_INIT_ENUM                 TRISTATE
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_PASSTHROUGH                       MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_CS0_0_TRISTATE_TRISTATE                  MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_CS0_0_PUPD_SHIFT                 MK_SHIFT_CONST(2)
#define PADCTL_AO_SPI2_CS0_0_PUPD_FIELD                 MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_CS0_0_PUPD_SHIFT)
#define PADCTL_AO_SPI2_CS0_0_PUPD_RANGE                 3:2
#define PADCTL_AO_SPI2_CS0_0_PUPD_MSB                   MK_SHIFT_CONST(3)
#define PADCTL_AO_SPI2_CS0_0_PUPD_LSB                   MK_SHIFT_CONST(2)
#define PADCTL_AO_SPI2_CS0_0_PUPD_WOFFSET                       0x0
#define PADCTL_AO_SPI2_CS0_0_PUPD_DEFAULT                       MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_PUPD_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PADCTL_AO_SPI2_CS0_0_PUPD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_PUPD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_PUPD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_PUPD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_PUPD_INIT_ENUM                     NONE
#define PADCTL_AO_SPI2_CS0_0_PUPD_NONE                  MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_CS0_0_PUPD_PULL_DOWN                     MK_ENUM_CONST(1)
#define PADCTL_AO_SPI2_CS0_0_PUPD_PULL_UP                       MK_ENUM_CONST(2)
#define PADCTL_AO_SPI2_CS0_0_PUPD_RSVD                  MK_ENUM_CONST(3)

#define PADCTL_AO_SPI2_CS0_0_E_INPUT_SHIFT                      MK_SHIFT_CONST(6)
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_E_INPUT_SHIFT)
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_RANGE                      6:6
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_MSB                        MK_SHIFT_CONST(6)
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_LSB                        MK_SHIFT_CONST(6)
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_WOFFSET                    0x0
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_DEFAULT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_INIT_ENUM                  ENABLE
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_CS0_0_E_INPUT_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_CS0_0_E_LPBK_SHIFT                       MK_SHIFT_CONST(7)
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_E_LPBK_SHIFT)
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_RANGE                       7:7
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_MSB                 MK_SHIFT_CONST(7)
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_LSB                 MK_SHIFT_CONST(7)
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_WOFFSET                     0x0
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_INIT_ENUM                   DISABLE
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_DISABLE                     MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_CS0_0_E_LPBK_ENABLE                      MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_CS0_0_E_LPDR_SHIFT                       MK_SHIFT_CONST(8)
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_E_LPDR_SHIFT)
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_RANGE                       8:8
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_MSB                 MK_SHIFT_CONST(8)
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_LSB                 MK_SHIFT_CONST(8)
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_WOFFSET                     0x0
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_INIT_ENUM                   DISABLE
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_DISABLE                     MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_CS0_0_E_LPDR_ENABLE                      MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_SHIFT                      MK_SHIFT_CONST(5)
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_E_IO_HV_SHIFT)
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_RANGE                      5:5
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_MSB                        MK_SHIFT_CONST(5)
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_LSB                        MK_SHIFT_CONST(5)
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_WOFFSET                    0x0
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_DEFAULT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_INIT_ENUM                  ENABLE
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_SHIFT                      MK_SHIFT_CONST(12)
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_E_SCHMT_SHIFT)
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_RANGE                      12:12
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_MSB                        MK_SHIFT_CONST(12)
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_LSB                        MK_SHIFT_CONST(12)
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_WOFFSET                    0x0
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_INIT_ENUM                  DISABLE
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_ENABLE                     MK_ENUM_CONST(1)


// Register PADCTL_AO_CFG2TMC_SPI2_CS0_0
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0                    MK_ADDR_CONST(0x3c)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_SECURE                     0x0
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_DUAL                       0x0
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_SCR                        SCR_SPI2_CS0_0
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_SCRREG                     PADCTL_AO_SCR_SCR_SPI2_CS0_0
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_WORD_COUNT                         0x1
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_RESET_MASK                         MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_READ_MASK                  MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_WRITE_MASK                         MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_SHIFT                        MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_RANGE                        16:12
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_MSB                  MK_SHIFT_CONST(16)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_LSB                  MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_WOFFSET                      0x0
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_SHIFT                        MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_RANGE                        24:20
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_MSB                  MK_SHIFT_CONST(24)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_LSB                  MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_WOFFSET                      0x0
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register PADCTL_AO_GEN2_I2C_SDA_0
#define PADCTL_AO_GEN2_I2C_SDA_0                        MK_ADDR_CONST(0x40)
#define PADCTL_AO_GEN2_I2C_SDA_0_SECURE                         0x0
#define PADCTL_AO_GEN2_I2C_SDA_0_DUAL                   0x0
#define PADCTL_AO_GEN2_I2C_SDA_0_SCR                    SCR_GEN2_I2C_SDA_0
#define PADCTL_AO_GEN2_I2C_SDA_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN2_I2C_SDA_0
#define PADCTL_AO_GEN2_I2C_SDA_0_WORD_COUNT                     0x1
#define PADCTL_AO_GEN2_I2C_SDA_0_RESET_VAL                      MK_MASK_CONST(0x570)
#define PADCTL_AO_GEN2_I2C_SDA_0_RESET_MASK                     MK_MASK_CONST(0x15ff)
#define PADCTL_AO_GEN2_I2C_SDA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_READ_MASK                      MK_MASK_CONST(0x15ff)
#define PADCTL_AO_GEN2_I2C_SDA_0_WRITE_MASK                     MK_MASK_CONST(0x15ff)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_SHIFT                       MK_SHIFT_CONST(0)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_FIELD                       MK_FIELD_CONST(0x3, PADCTL_AO_GEN2_I2C_SDA_0_PM_SHIFT)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_RANGE                       1:0
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_MSB                 MK_SHIFT_CONST(1)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_LSB                 MK_SHIFT_CONST(0)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_WOFFSET                     0x0
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_INIT_ENUM                   I2C2
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_I2C2                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_RSVD1                       MK_ENUM_CONST(1)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_RSVD2                       MK_ENUM_CONST(2)
#define PADCTL_AO_GEN2_I2C_SDA_0_PM_RSVD3                       MK_ENUM_CONST(3)

#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_SHIFT                      MK_SHIFT_CONST(10)
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_MSB                        MK_SHIFT_CONST(10)
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_LSB                        MK_SHIFT_CONST(10)
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_DEFAULT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_GPIO                       MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_SFIO                       MK_ENUM_CONST(1)

#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_SHIFT                 MK_SHIFT_CONST(4)
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_SHIFT)
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_RANGE                 4:4
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_MSB                   MK_SHIFT_CONST(4)
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_LSB                   MK_SHIFT_CONST(4)
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_DEFAULT                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_PASSTHROUGH                   MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_TRISTATE                      MK_ENUM_CONST(1)

#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_SHIFT                     MK_SHIFT_CONST(2)
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_FIELD                     MK_FIELD_CONST(0x3, PADCTL_AO_GEN2_I2C_SDA_0_PUPD_SHIFT)
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_RANGE                     3:2
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_MSB                       MK_SHIFT_CONST(3)
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_LSB                       MK_SHIFT_CONST(2)
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_WOFFSET                   0x0
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_INIT_ENUM                 NONE
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_NONE                      MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_PULL_DOWN                 MK_ENUM_CONST(1)
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_PULL_UP                   MK_ENUM_CONST(2)
#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_RSVD                      MK_ENUM_CONST(3)

#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_SHIFT                  MK_SHIFT_CONST(6)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_SHIFT)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_RANGE                  6:6
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_MSB                    MK_SHIFT_CONST(6)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_LSB                    MK_SHIFT_CONST(6)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_INIT_ENUM                      ENABLE
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_DISABLE                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_ENABLE                 MK_ENUM_CONST(1)

#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_SHIFT                   MK_SHIFT_CONST(7)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_SHIFT)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_RANGE                   7:7
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_MSB                     MK_SHIFT_CONST(7)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_LSB                     MK_SHIFT_CONST(7)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_WOFFSET                 0x0
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_INIT_ENUM                       DISABLE
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_DISABLE                 MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_ENABLE                  MK_ENUM_CONST(1)

#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_SHIFT                   MK_SHIFT_CONST(8)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_SHIFT)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_RANGE                   8:8
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_MSB                     MK_SHIFT_CONST(8)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_LSB                     MK_SHIFT_CONST(8)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_DEFAULT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_INIT_ENUM                       ENABLE
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_DISABLE                 MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_ENABLE                  MK_ENUM_CONST(1)

#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_SHIFT                  MK_SHIFT_CONST(5)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_SHIFT)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_RANGE                  5:5
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_MSB                    MK_SHIFT_CONST(5)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_LSB                    MK_SHIFT_CONST(5)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_WOFFSET                        0x0
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_INIT_ENUM                      ENABLE
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_DISABLE                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_ENABLE                 MK_ENUM_CONST(1)

#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_SHIFT                  MK_SHIFT_CONST(12)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_SHIFT)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_RANGE                  12:12
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_MSB                    MK_SHIFT_CONST(12)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_LSB                    MK_SHIFT_CONST(12)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_INIT_ENUM                      DISABLE
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_DISABLE                        MK_ENUM_CONST(0)
#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_ENABLE                 MK_ENUM_CONST(1)


// Register PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0                        MK_ADDR_CONST(0x44)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_SECURE                         0x0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_DUAL                   0x0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_SCR                    SCR_GEN2_I2C_SDA_0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN2_I2C_SDA_0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_WORD_COUNT                     0x1
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_RESET_MASK                     MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_READ_MASK                      MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_WRITE_MASK                     MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_SHIFT                    MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_MSB                      MK_SHIFT_CONST(16)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_LSB                      MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_SHIFT                    MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_MSB                      MK_SHIFT_CONST(24)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_LSB                      MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register PADCTL_AO_SPI2_SCK_0
#define PADCTL_AO_SPI2_SCK_0                    MK_ADDR_CONST(0x48)
#define PADCTL_AO_SPI2_SCK_0_SECURE                     0x0
#define PADCTL_AO_SPI2_SCK_0_DUAL                       0x0
#define PADCTL_AO_SPI2_SCK_0_SCR                        SCR_SPI2_SCK_0
#define PADCTL_AO_SPI2_SCK_0_SCRREG                     PADCTL_AO_SCR_SCR_SPI2_SCK_0
#define PADCTL_AO_SPI2_SCK_0_WORD_COUNT                         0x1
#define PADCTL_AO_SPI2_SCK_0_RESET_VAL                  MK_MASK_CONST(0x1474)
#define PADCTL_AO_SPI2_SCK_0_RESET_MASK                         MK_MASK_CONST(0x15ff)
#define PADCTL_AO_SPI2_SCK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_READ_MASK                  MK_MASK_CONST(0x15ff)
#define PADCTL_AO_SPI2_SCK_0_WRITE_MASK                         MK_MASK_CONST(0x15ff)
#define PADCTL_AO_SPI2_SCK_0_PM_SHIFT                   MK_SHIFT_CONST(0)
#define PADCTL_AO_SPI2_SCK_0_PM_FIELD                   MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_SCK_0_PM_SHIFT)
#define PADCTL_AO_SPI2_SCK_0_PM_RANGE                   1:0
#define PADCTL_AO_SPI2_SCK_0_PM_MSB                     MK_SHIFT_CONST(1)
#define PADCTL_AO_SPI2_SCK_0_PM_LSB                     MK_SHIFT_CONST(0)
#define PADCTL_AO_SPI2_SCK_0_PM_WOFFSET                 0x0
#define PADCTL_AO_SPI2_SCK_0_PM_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_PM_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define PADCTL_AO_SPI2_SCK_0_PM_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_PM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_PM_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_PM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_PM_INIT_ENUM                       SPI2
#define PADCTL_AO_SPI2_SCK_0_PM_SPI2                    MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_SCK_0_PM_RSVD1                   MK_ENUM_CONST(1)
#define PADCTL_AO_SPI2_SCK_0_PM_RSVD2                   MK_ENUM_CONST(2)
#define PADCTL_AO_SPI2_SCK_0_PM_RSVD3                   MK_ENUM_CONST(3)

#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_SHIFT                  MK_SHIFT_CONST(10)
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_RANGE                  10:10
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_MSB                    MK_SHIFT_CONST(10)
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_LSB                    MK_SHIFT_CONST(10)
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_WOFFSET                        0x0
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_DEFAULT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_INIT_ENUM                      SFIO
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_GPIO                   MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_SFIO                   MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_SCK_0_TRISTATE_SHIFT                     MK_SHIFT_CONST(4)
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_TRISTATE_SHIFT)
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_RANGE                     4:4
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_MSB                       MK_SHIFT_CONST(4)
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_LSB                       MK_SHIFT_CONST(4)
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_WOFFSET                   0x0
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_DEFAULT                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_INIT_ENUM                 TRISTATE
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_PASSTHROUGH                       MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_SCK_0_TRISTATE_TRISTATE                  MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_SCK_0_PUPD_SHIFT                 MK_SHIFT_CONST(2)
#define PADCTL_AO_SPI2_SCK_0_PUPD_FIELD                 MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_SCK_0_PUPD_SHIFT)
#define PADCTL_AO_SPI2_SCK_0_PUPD_RANGE                 3:2
#define PADCTL_AO_SPI2_SCK_0_PUPD_MSB                   MK_SHIFT_CONST(3)
#define PADCTL_AO_SPI2_SCK_0_PUPD_LSB                   MK_SHIFT_CONST(2)
#define PADCTL_AO_SPI2_SCK_0_PUPD_WOFFSET                       0x0
#define PADCTL_AO_SPI2_SCK_0_PUPD_DEFAULT                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_PUPD_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define PADCTL_AO_SPI2_SCK_0_PUPD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_PUPD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_PUPD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_PUPD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_PUPD_INIT_ENUM                     PULL_DOWN
#define PADCTL_AO_SPI2_SCK_0_PUPD_NONE                  MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_SCK_0_PUPD_PULL_DOWN                     MK_ENUM_CONST(1)
#define PADCTL_AO_SPI2_SCK_0_PUPD_PULL_UP                       MK_ENUM_CONST(2)
#define PADCTL_AO_SPI2_SCK_0_PUPD_RSVD                  MK_ENUM_CONST(3)

#define PADCTL_AO_SPI2_SCK_0_E_INPUT_SHIFT                      MK_SHIFT_CONST(6)
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_E_INPUT_SHIFT)
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_RANGE                      6:6
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_MSB                        MK_SHIFT_CONST(6)
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_LSB                        MK_SHIFT_CONST(6)
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_WOFFSET                    0x0
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_DEFAULT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_INIT_ENUM                  ENABLE
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_SCK_0_E_INPUT_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_SCK_0_E_LPBK_SHIFT                       MK_SHIFT_CONST(7)
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_E_LPBK_SHIFT)
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_RANGE                       7:7
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_MSB                 MK_SHIFT_CONST(7)
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_LSB                 MK_SHIFT_CONST(7)
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_WOFFSET                     0x0
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_INIT_ENUM                   DISABLE
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_DISABLE                     MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_SCK_0_E_LPBK_ENABLE                      MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_SCK_0_E_LPDR_SHIFT                       MK_SHIFT_CONST(8)
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_E_LPDR_SHIFT)
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_RANGE                       8:8
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_MSB                 MK_SHIFT_CONST(8)
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_LSB                 MK_SHIFT_CONST(8)
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_WOFFSET                     0x0
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_INIT_ENUM                   DISABLE
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_DISABLE                     MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_SCK_0_E_LPDR_ENABLE                      MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_SHIFT                      MK_SHIFT_CONST(5)
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_E_IO_HV_SHIFT)
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_RANGE                      5:5
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_MSB                        MK_SHIFT_CONST(5)
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_LSB                        MK_SHIFT_CONST(5)
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_WOFFSET                    0x0
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_DEFAULT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_INIT_ENUM                  ENABLE
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_SHIFT                      MK_SHIFT_CONST(12)
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_E_SCHMT_SHIFT)
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_RANGE                      12:12
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_MSB                        MK_SHIFT_CONST(12)
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_LSB                        MK_SHIFT_CONST(12)
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_WOFFSET                    0x0
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_DEFAULT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_INIT_ENUM                  ENABLE
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_ENABLE                     MK_ENUM_CONST(1)


// Register PADCTL_AO_CFG2TMC_SPI2_SCK_0
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0                    MK_ADDR_CONST(0x4c)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_SECURE                     0x0
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_DUAL                       0x0
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_SCR                        SCR_SPI2_SCK_0
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_SCRREG                     PADCTL_AO_SCR_SCR_SPI2_SCK_0
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_WORD_COUNT                         0x1
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_RESET_MASK                         MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_READ_MASK                  MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_WRITE_MASK                         MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_SHIFT                        MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_RANGE                        16:12
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_MSB                  MK_SHIFT_CONST(16)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_LSB                  MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_WOFFSET                      0x0
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_SHIFT                        MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_RANGE                        24:20
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_MSB                  MK_SHIFT_CONST(24)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_LSB                  MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_WOFFSET                      0x0
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_DEFAULT                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register PADCTL_AO_SPI2_MISO_0
#define PADCTL_AO_SPI2_MISO_0                   MK_ADDR_CONST(0x50)
#define PADCTL_AO_SPI2_MISO_0_SECURE                    0x0
#define PADCTL_AO_SPI2_MISO_0_DUAL                      0x0
#define PADCTL_AO_SPI2_MISO_0_SCR                       SCR_SPI2_MISO_0
#define PADCTL_AO_SPI2_MISO_0_SCRREG                    PADCTL_AO_SCR_SCR_SPI2_MISO_0
#define PADCTL_AO_SPI2_MISO_0_WORD_COUNT                        0x1
#define PADCTL_AO_SPI2_MISO_0_RESET_VAL                         MK_MASK_CONST(0x474)
#define PADCTL_AO_SPI2_MISO_0_RESET_MASK                        MK_MASK_CONST(0x15ff)
#define PADCTL_AO_SPI2_MISO_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_READ_MASK                         MK_MASK_CONST(0x15ff)
#define PADCTL_AO_SPI2_MISO_0_WRITE_MASK                        MK_MASK_CONST(0x15ff)
#define PADCTL_AO_SPI2_MISO_0_PM_SHIFT                  MK_SHIFT_CONST(0)
#define PADCTL_AO_SPI2_MISO_0_PM_FIELD                  MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_MISO_0_PM_SHIFT)
#define PADCTL_AO_SPI2_MISO_0_PM_RANGE                  1:0
#define PADCTL_AO_SPI2_MISO_0_PM_MSB                    MK_SHIFT_CONST(1)
#define PADCTL_AO_SPI2_MISO_0_PM_LSB                    MK_SHIFT_CONST(0)
#define PADCTL_AO_SPI2_MISO_0_PM_WOFFSET                        0x0
#define PADCTL_AO_SPI2_MISO_0_PM_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_PM_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define PADCTL_AO_SPI2_MISO_0_PM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_PM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_PM_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_PM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_PM_INIT_ENUM                      SPI2
#define PADCTL_AO_SPI2_MISO_0_PM_SPI2                   MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MISO_0_PM_RSVD1                  MK_ENUM_CONST(1)
#define PADCTL_AO_SPI2_MISO_0_PM_RSVD2                  MK_ENUM_CONST(2)
#define PADCTL_AO_SPI2_MISO_0_PM_RSVD3                  MK_ENUM_CONST(3)

#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_SHIFT                 MK_SHIFT_CONST(10)
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_RANGE                 10:10
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_MSB                   MK_SHIFT_CONST(10)
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_LSB                   MK_SHIFT_CONST(10)
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_WOFFSET                       0x0
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_DEFAULT                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_INIT_ENUM                     SFIO
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_GPIO                  MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_SFIO                  MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_MISO_0_TRISTATE_SHIFT                    MK_SHIFT_CONST(4)
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_FIELD                    MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_TRISTATE_SHIFT)
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_RANGE                    4:4
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_MSB                      MK_SHIFT_CONST(4)
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_LSB                      MK_SHIFT_CONST(4)
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_WOFFSET                  0x0
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_DEFAULT                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_INIT_ENUM                        TRISTATE
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_PASSTHROUGH                      MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MISO_0_TRISTATE_TRISTATE                 MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_MISO_0_PUPD_SHIFT                        MK_SHIFT_CONST(2)
#define PADCTL_AO_SPI2_MISO_0_PUPD_FIELD                        MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_MISO_0_PUPD_SHIFT)
#define PADCTL_AO_SPI2_MISO_0_PUPD_RANGE                        3:2
#define PADCTL_AO_SPI2_MISO_0_PUPD_MSB                  MK_SHIFT_CONST(3)
#define PADCTL_AO_SPI2_MISO_0_PUPD_LSB                  MK_SHIFT_CONST(2)
#define PADCTL_AO_SPI2_MISO_0_PUPD_WOFFSET                      0x0
#define PADCTL_AO_SPI2_MISO_0_PUPD_DEFAULT                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_PUPD_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define PADCTL_AO_SPI2_MISO_0_PUPD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_PUPD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_PUPD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_PUPD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_PUPD_INIT_ENUM                    PULL_DOWN
#define PADCTL_AO_SPI2_MISO_0_PUPD_NONE                 MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MISO_0_PUPD_PULL_DOWN                    MK_ENUM_CONST(1)
#define PADCTL_AO_SPI2_MISO_0_PUPD_PULL_UP                      MK_ENUM_CONST(2)
#define PADCTL_AO_SPI2_MISO_0_PUPD_RSVD                 MK_ENUM_CONST(3)

#define PADCTL_AO_SPI2_MISO_0_E_INPUT_SHIFT                     MK_SHIFT_CONST(6)
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_E_INPUT_SHIFT)
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_RANGE                     6:6
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_MSB                       MK_SHIFT_CONST(6)
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_LSB                       MK_SHIFT_CONST(6)
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_WOFFSET                   0x0
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_DEFAULT                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_INIT_ENUM                 ENABLE
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_DISABLE                   MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MISO_0_E_INPUT_ENABLE                    MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_MISO_0_E_LPBK_SHIFT                      MK_SHIFT_CONST(7)
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_E_LPBK_SHIFT)
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_RANGE                      7:7
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_MSB                        MK_SHIFT_CONST(7)
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_LSB                        MK_SHIFT_CONST(7)
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_WOFFSET                    0x0
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_INIT_ENUM                  DISABLE
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MISO_0_E_LPBK_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_MISO_0_E_LPDR_SHIFT                      MK_SHIFT_CONST(8)
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_E_LPDR_SHIFT)
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_RANGE                      8:8
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_MSB                        MK_SHIFT_CONST(8)
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_LSB                        MK_SHIFT_CONST(8)
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_WOFFSET                    0x0
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_DEFAULT                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_INIT_ENUM                  DISABLE
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_DISABLE                    MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MISO_0_E_LPDR_ENABLE                     MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_SHIFT                     MK_SHIFT_CONST(5)
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_E_IO_HV_SHIFT)
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_RANGE                     5:5
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_MSB                       MK_SHIFT_CONST(5)
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_LSB                       MK_SHIFT_CONST(5)
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_WOFFSET                   0x0
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_DEFAULT                   MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_INIT_ENUM                 ENABLE
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_DISABLE                   MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_ENABLE                    MK_ENUM_CONST(1)

#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_SHIFT                     MK_SHIFT_CONST(12)
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_E_SCHMT_SHIFT)
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_RANGE                     12:12
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_MSB                       MK_SHIFT_CONST(12)
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_LSB                       MK_SHIFT_CONST(12)
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_WOFFSET                   0x0
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_DEFAULT                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_INIT_ENUM                 DISABLE
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_DISABLE                   MK_ENUM_CONST(0)
#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_ENABLE                    MK_ENUM_CONST(1)


// Register PADCTL_AO_CFG2TMC_SPI2_MISO_0
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0                   MK_ADDR_CONST(0x54)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_SECURE                    0x0
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_DUAL                      0x0
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_SCR                       SCR_SPI2_MISO_0
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_SCRREG                    PADCTL_AO_SCR_SCR_SPI2_MISO_0
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_WORD_COUNT                        0x1
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_RESET_MASK                        MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_READ_MASK                         MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_WRITE_MASK                        MK_MASK_CONST(0x1f1f000)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_SHIFT                       MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_FIELD                       MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_RANGE                       16:12
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_MSB                 MK_SHIFT_CONST(16)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_LSB                 MK_SHIFT_CONST(12)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_WOFFSET                     0x0
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_SHIFT                       MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_FIELD                       MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_RANGE                       24:20
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_MSB                 MK_SHIFT_CONST(24)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_LSB                 MK_SHIFT_CONST(20)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_WOFFSET                     0x0
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_DEFAULT                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARPADCTL_AO_REGS(_op_) \
_op_(PADCTL_AO_TOUCH_CLK_0) \
_op_(PADCTL_AO_CFG2TMC_TOUCH_CLK_0) \
_op_(PADCTL_AO_UART3_RX_0) \
_op_(PADCTL_AO_CFG2TMC_UART3_RX_0) \
_op_(PADCTL_AO_UART3_TX_0) \
_op_(PADCTL_AO_CFG2TMC_UART3_TX_0) \
_op_(PADCTL_AO_GEN8_I2C_SDA_0) \
_op_(PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0) \
_op_(PADCTL_AO_GEN8_I2C_SCL_0) \
_op_(PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0) \
_op_(PADCTL_AO_SPI2_MOSI_0) \
_op_(PADCTL_AO_CFG2TMC_SPI2_MOSI_0) \
_op_(PADCTL_AO_GEN2_I2C_SCL_0) \
_op_(PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0) \
_op_(PADCTL_AO_SPI2_CS0_0) \
_op_(PADCTL_AO_CFG2TMC_SPI2_CS0_0) \
_op_(PADCTL_AO_GEN2_I2C_SDA_0) \
_op_(PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0) \
_op_(PADCTL_AO_SPI2_SCK_0) \
_op_(PADCTL_AO_CFG2TMC_SPI2_SCK_0) \
_op_(PADCTL_AO_SPI2_MISO_0) \
_op_(PADCTL_AO_CFG2TMC_SPI2_MISO_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_PADCTL_AO  0x00000000

//
// ARPADCTL_AO REGISTER BANKS
//

#define PADCTL_AO0_FIRST_REG 0x0000 // PADCTL_AO_TOUCH_CLK_0
#define PADCTL_AO0_LAST_REG 0x0054 // PADCTL_AO_CFG2TMC_SPI2_MISO_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARPADCTL_AO_H_INC
