/* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *  * Neither the name of NVIDIA CORPORATION nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _GPIO_AON_T23X_H
#define _GPIO_AON_T23X_H

#include <processor/tegra-gpio-hw.h>

#define TEGRA_AON_GPIO_CHIP_ID 0
#define TEGRA_AON_GPIO_ID(bank, gpio) \
		gpio_global_id(TEGRA_AON_GPIO_CHIP_ID, TEGRA_GPIO(bank, gpio))

#ifdef ENABLE_SPE_FOR_ORIN_NANO
#define GPIO_APP_OUT TEGRA_AON_GPIO_ID(DD, 1) /* GPIO_DD 1, pin 5, J12 */
#define GPIO_APP_IN  TEGRA_AON_GPIO_ID(DD, 2) /* GPIO_DD 2, pin 3, J12 */

#else /* SPE for AGX Orin */

#define GPIO_APP_OUT TEGRA_AON_GPIO_ID(BB, 1) /* GPIO_BB 1, pin 16, J30 */
#define GPIO_APP_IN  TEGRA_AON_GPIO_ID(BB, 0) /* GPIO_BB 0, pin 32, J30 */
#endif /* ENABLE_SPE_FOR_ORIN_NANO */

#endif
