//
// Copyright (c) 2021 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARAODMIC_H_INC
#define ARAODMIC_H_INC
#define NV_MOBILE_ARAODMIC_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARAODMIC_H_SCRREG_NOMENCLATURE INFERRED


// Register AODMIC_APB_FIFO_CTRL_0
#define AODMIC_APB_FIFO_CTRL_0                  MK_ADDR_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_0_SECURE                   0x0
#define AODMIC_APB_FIFO_CTRL_0_DUAL                     0x0
#define AODMIC_APB_FIFO_CTRL_0_SCR                      0
#define AODMIC_APB_FIFO_CTRL_0_SCRREG                   0
#define AODMIC_APB_FIFO_CTRL_0_WORD_COUNT                       0x1
#define AODMIC_APB_FIFO_CTRL_0_RESET_VAL                        MK_MASK_CONST(0x1000)
#define AODMIC_APB_FIFO_CTRL_0_RESET_MASK                       MK_MASK_CONST(0x3f00)
#define AODMIC_APB_FIFO_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_0_READ_MASK                        MK_MASK_CONST(0x3f00)
#define AODMIC_APB_FIFO_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0x3f00)
#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_SHIFT                  MK_SHIFT_CONST(8)
#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_FIELD                  MK_FIELD_CONST(0x3f, AODMIC_APB_FIFO_CTRL_0_THRESHOLD_SHIFT)
#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_RANGE                  13:8
#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_MSB                    MK_SHIFT_CONST(13)
#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_LSB                    MK_SHIFT_CONST(8)
#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_WOFFSET                        0x0
#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_DEFAULT                        MK_MASK_CONST(0x10)
#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_DEFAULT_MASK                   MK_MASK_CONST(0x3f)
#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register AODMIC_APB_FIFO_CTRL_RD_DATA_0
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0                  MK_ADDR_CONST(0x4)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_SECURE                   0x0
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DUAL                     0x0
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_SCR                      0
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_SCRREG                   0
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_WORD_COUNT                       0x1
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_SHIFT)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_RANGE                       31:0
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_MSB                 MK_SHIFT_CONST(31)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_LSB                 MK_SHIFT_CONST(0)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_WOFFSET                     0x0
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register AODMIC_APB_FIFO_STATUS_0
#define AODMIC_APB_FIFO_STATUS_0                        MK_ADDR_CONST(0x8)
#define AODMIC_APB_FIFO_STATUS_0_SECURE                         0x0
#define AODMIC_APB_FIFO_STATUS_0_DUAL                   0x0
#define AODMIC_APB_FIFO_STATUS_0_SCR                    0
#define AODMIC_APB_FIFO_STATUS_0_SCRREG                         0
#define AODMIC_APB_FIFO_STATUS_0_WORD_COUNT                     0x1
#define AODMIC_APB_FIFO_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x40)
#define AODMIC_APB_FIFO_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1ff)
#define AODMIC_APB_FIFO_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1ff)
#define AODMIC_APB_FIFO_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_SHIFT                   MK_SHIFT_CONST(8)
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_FIELD                   MK_FIELD_CONST(0x1, AODMIC_APB_FIFO_STATUS_0_RX_REQ_SHIFT)
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_RANGE                   8:8
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_MSB                     MK_SHIFT_CONST(8)
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_LSB                     MK_SHIFT_CONST(8)
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_WOFFSET                 0x0
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_DEFAULT                 MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_INIT_ENUM                       FALSE
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_FALSE                   MK_ENUM_CONST(0)
#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_TRUE                    MK_ENUM_CONST(1)

#define AODMIC_APB_FIFO_STATUS_0_FULL_SHIFT                     MK_SHIFT_CONST(7)
#define AODMIC_APB_FIFO_STATUS_0_FULL_FIELD                     MK_FIELD_CONST(0x1, AODMIC_APB_FIFO_STATUS_0_FULL_SHIFT)
#define AODMIC_APB_FIFO_STATUS_0_FULL_RANGE                     7:7
#define AODMIC_APB_FIFO_STATUS_0_FULL_MSB                       MK_SHIFT_CONST(7)
#define AODMIC_APB_FIFO_STATUS_0_FULL_LSB                       MK_SHIFT_CONST(7)
#define AODMIC_APB_FIFO_STATUS_0_FULL_WOFFSET                   0x0
#define AODMIC_APB_FIFO_STATUS_0_FULL_DEFAULT                   MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_FULL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define AODMIC_APB_FIFO_STATUS_0_FULL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_FULL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_FULL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_FULL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define AODMIC_APB_FIFO_STATUS_0_FULL_INIT_ENUM                 FALSE
#define AODMIC_APB_FIFO_STATUS_0_FULL_FALSE                     MK_ENUM_CONST(0)
#define AODMIC_APB_FIFO_STATUS_0_FULL_TRUE                      MK_ENUM_CONST(1)

#define AODMIC_APB_FIFO_STATUS_0_EMPTY_SHIFT                    MK_SHIFT_CONST(6)
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_FIELD                    MK_FIELD_CONST(0x1, AODMIC_APB_FIFO_STATUS_0_EMPTY_SHIFT)
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_RANGE                    6:6
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_MSB                      MK_SHIFT_CONST(6)
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_LSB                      MK_SHIFT_CONST(6)
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_WOFFSET                  0x0
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_DEFAULT                  MK_MASK_CONST(0x1)
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_INIT_ENUM                        TRUE
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_FALSE                    MK_ENUM_CONST(0)
#define AODMIC_APB_FIFO_STATUS_0_EMPTY_TRUE                     MK_ENUM_CONST(1)

#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_SHIFT                       MK_SHIFT_CONST(0)
#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_FIELD                       MK_FIELD_CONST(0x3f, AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_SHIFT)
#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_RANGE                       5:0
#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_MSB                 MK_SHIFT_CONST(5)
#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_LSB                 MK_SHIFT_CONST(0)
#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_WOFFSET                     0x0
#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register AODMIC_APB_RX_INT_STATUS_0
#define AODMIC_APB_RX_INT_STATUS_0                      MK_ADDR_CONST(0xc)
#define AODMIC_APB_RX_INT_STATUS_0_SECURE                       0x0
#define AODMIC_APB_RX_INT_STATUS_0_DUAL                         0x0
#define AODMIC_APB_RX_INT_STATUS_0_SCR                  0
#define AODMIC_APB_RX_INT_STATUS_0_SCRREG                       0
#define AODMIC_APB_RX_INT_STATUS_0_WORD_COUNT                   0x1
#define AODMIC_APB_RX_INT_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x101)
#define AODMIC_APB_RX_INT_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_STATUS_0_READ_MASK                    MK_MASK_CONST(0x101)
#define AODMIC_APB_RX_INT_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_SHIFT                     MK_SHIFT_CONST(8)
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_FIELD                     MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_SHIFT)
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_RANGE                     8:8
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_MSB                       MK_SHIFT_CONST(8)
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_LSB                       MK_SHIFT_CONST(8)
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_WOFFSET                   0x0
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_DEFAULT                   MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_INIT_ENUM                 CLEAR
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_CLEAR                     MK_ENUM_CONST(0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_SET                       MK_ENUM_CONST(1)

#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_SHIFT                        MK_SHIFT_CONST(0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_FIELD                        MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_STATUS_0_RX_DONE_SHIFT)
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_RANGE                        0:0
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_MSB                  MK_SHIFT_CONST(0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_LSB                  MK_SHIFT_CONST(0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_WOFFSET                      0x0
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_INIT_ENUM                    CLEAR
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_CLEAR                        MK_ENUM_CONST(0)
#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_SET                  MK_ENUM_CONST(1)


// Register AODMIC_APB_RX_INT_MASK_0
#define AODMIC_APB_RX_INT_MASK_0                        MK_ADDR_CONST(0x10)
#define AODMIC_APB_RX_INT_MASK_0_SECURE                         0x0
#define AODMIC_APB_RX_INT_MASK_0_DUAL                   0x0
#define AODMIC_APB_RX_INT_MASK_0_SCR                    0
#define AODMIC_APB_RX_INT_MASK_0_SCRREG                         0
#define AODMIC_APB_RX_INT_MASK_0_WORD_COUNT                     0x1
#define AODMIC_APB_RX_INT_MASK_0_RESET_VAL                      MK_MASK_CONST(0x101)
#define AODMIC_APB_RX_INT_MASK_0_RESET_MASK                     MK_MASK_CONST(0x101)
#define AODMIC_APB_RX_INT_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_MASK_0_READ_MASK                      MK_MASK_CONST(0x101)
#define AODMIC_APB_RX_INT_MASK_0_WRITE_MASK                     MK_MASK_CONST(0x101)
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_SHIFT                       MK_SHIFT_CONST(8)
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_FIELD                       MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_SHIFT)
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_RANGE                       8:8
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_MSB                 MK_SHIFT_CONST(8)
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_LSB                 MK_SHIFT_CONST(8)
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_WOFFSET                     0x0
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_DEFAULT                     MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_INIT_ENUM                   MASK
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_UNMASK                      MK_ENUM_CONST(0)
#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_MASK                        MK_ENUM_CONST(1)

#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_SHIFT                  MK_SHIFT_CONST(0)
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_FIELD                  MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_MASK_0_RX_DONE_SHIFT)
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_RANGE                  0:0
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_MSB                    MK_SHIFT_CONST(0)
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_LSB                    MK_SHIFT_CONST(0)
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_WOFFSET                        0x0
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_DEFAULT                        MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_INIT_ENUM                      MASK
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_UNMASK                 MK_ENUM_CONST(0)
#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_MASK                   MK_ENUM_CONST(1)


// Register AODMIC_APB_RX_INT_SET_0
#define AODMIC_APB_RX_INT_SET_0                 MK_ADDR_CONST(0x14)
#define AODMIC_APB_RX_INT_SET_0_SECURE                  0x0
#define AODMIC_APB_RX_INT_SET_0_DUAL                    0x0
#define AODMIC_APB_RX_INT_SET_0_SCR                     0
#define AODMIC_APB_RX_INT_SET_0_SCRREG                  0
#define AODMIC_APB_RX_INT_SET_0_WORD_COUNT                      0x1
#define AODMIC_APB_RX_INT_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_SET_0_RESET_MASK                      MK_MASK_CONST(0x101)
#define AODMIC_APB_RX_INT_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_SET_0_READ_MASK                       MK_MASK_CONST(0x101)
#define AODMIC_APB_RX_INT_SET_0_WRITE_MASK                      MK_MASK_CONST(0x101)
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_SHIFT                        MK_SHIFT_CONST(8)
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_FIELD                        MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_SHIFT)
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_RANGE                        8:8
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_MSB                  MK_SHIFT_CONST(8)
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_LSB                  MK_SHIFT_CONST(8)
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_WOFFSET                      0x0
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_DEFAULT                      MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_INIT_ENUM                    CLEAR
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_CLEAR                        MK_ENUM_CONST(0)
#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_SET                  MK_ENUM_CONST(1)

#define AODMIC_APB_RX_INT_SET_0_RX_DONE_SHIFT                   MK_SHIFT_CONST(0)
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_FIELD                   MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_SET_0_RX_DONE_SHIFT)
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_RANGE                   0:0
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_MSB                     MK_SHIFT_CONST(0)
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_LSB                     MK_SHIFT_CONST(0)
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_WOFFSET                 0x0
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_DEFAULT                 MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_INIT_ENUM                       CLEAR
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_CLEAR                   MK_ENUM_CONST(0)
#define AODMIC_APB_RX_INT_SET_0_RX_DONE_SET                     MK_ENUM_CONST(1)


// Register AODMIC_APB_RX_INT_CLEAR_0
#define AODMIC_APB_RX_INT_CLEAR_0                       MK_ADDR_CONST(0x18)
#define AODMIC_APB_RX_INT_CLEAR_0_SECURE                        0x0
#define AODMIC_APB_RX_INT_CLEAR_0_DUAL                  0x0
#define AODMIC_APB_RX_INT_CLEAR_0_SCR                   0
#define AODMIC_APB_RX_INT_CLEAR_0_SCRREG                        0
#define AODMIC_APB_RX_INT_CLEAR_0_WORD_COUNT                    0x1
#define AODMIC_APB_RX_INT_CLEAR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_CLEAR_0_RESET_MASK                    MK_MASK_CONST(0x101)
#define AODMIC_APB_RX_INT_CLEAR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_CLEAR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_CLEAR_0_READ_MASK                     MK_MASK_CONST(0x101)
#define AODMIC_APB_RX_INT_CLEAR_0_WRITE_MASK                    MK_MASK_CONST(0x101)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_SHIFT                      MK_SHIFT_CONST(8)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_FIELD                      MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_SHIFT)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_RANGE                      8:8
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_MSB                        MK_SHIFT_CONST(8)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_LSB                        MK_SHIFT_CONST(8)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_WOFFSET                    0x0
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_DEFAULT                    MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_INIT_ENUM                  CLEAR
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_CLEAR                      MK_ENUM_CONST(0)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_SET                        MK_ENUM_CONST(1)

#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_SHIFT                 MK_SHIFT_CONST(0)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_FIELD                 MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_SHIFT)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_RANGE                 0:0
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_MSB                   MK_SHIFT_CONST(0)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_LSB                   MK_SHIFT_CONST(0)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_WOFFSET                       0x0
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_DEFAULT                       MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_INIT_ENUM                     CLEAR
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_CLEAR                 MK_ENUM_CONST(0)
#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_SET                   MK_ENUM_CONST(1)


// Register AODMIC_ENABLE_0
#define AODMIC_ENABLE_0                 MK_ADDR_CONST(0x40)
#define AODMIC_ENABLE_0_SECURE                  0x0
#define AODMIC_ENABLE_0_DUAL                    0x0
#define AODMIC_ENABLE_0_SCR                     0
#define AODMIC_ENABLE_0_SCRREG                  0
#define AODMIC_ENABLE_0_WORD_COUNT                      0x1
#define AODMIC_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define AODMIC_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define AODMIC_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define AODMIC_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define AODMIC_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1)
#define AODMIC_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define AODMIC_ENABLE_0_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define AODMIC_ENABLE_0_ENABLE_FIELD                    MK_FIELD_CONST(0x1, AODMIC_ENABLE_0_ENABLE_SHIFT)
#define AODMIC_ENABLE_0_ENABLE_RANGE                    0:0
#define AODMIC_ENABLE_0_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define AODMIC_ENABLE_0_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define AODMIC_ENABLE_0_ENABLE_WOFFSET                  0x0
#define AODMIC_ENABLE_0_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define AODMIC_ENABLE_0_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define AODMIC_ENABLE_0_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define AODMIC_ENABLE_0_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define AODMIC_ENABLE_0_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define AODMIC_ENABLE_0_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define AODMIC_ENABLE_0_ENABLE_INIT_ENUM                        FALSE
#define AODMIC_ENABLE_0_ENABLE_FALSE                    MK_ENUM_CONST(0)
#define AODMIC_ENABLE_0_ENABLE_TRUE                     MK_ENUM_CONST(1)


// Register AODMIC_SOFT_RESET_0
#define AODMIC_SOFT_RESET_0                     MK_ADDR_CONST(0x44)
#define AODMIC_SOFT_RESET_0_SECURE                      0x0
#define AODMIC_SOFT_RESET_0_DUAL                        0x0
#define AODMIC_SOFT_RESET_0_SCR                         0
#define AODMIC_SOFT_RESET_0_SCRREG                      0
#define AODMIC_SOFT_RESET_0_WORD_COUNT                  0x1
#define AODMIC_SOFT_RESET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define AODMIC_SOFT_RESET_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define AODMIC_SOFT_RESET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define AODMIC_SOFT_RESET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define AODMIC_SOFT_RESET_0_READ_MASK                   MK_MASK_CONST(0x1)
#define AODMIC_SOFT_RESET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define AODMIC_SOFT_RESET_0_SOFT_RESET_SHIFT                    MK_SHIFT_CONST(0)
#define AODMIC_SOFT_RESET_0_SOFT_RESET_FIELD                    MK_FIELD_CONST(0x1, AODMIC_SOFT_RESET_0_SOFT_RESET_SHIFT)
#define AODMIC_SOFT_RESET_0_SOFT_RESET_RANGE                    0:0
#define AODMIC_SOFT_RESET_0_SOFT_RESET_MSB                      MK_SHIFT_CONST(0)
#define AODMIC_SOFT_RESET_0_SOFT_RESET_LSB                      MK_SHIFT_CONST(0)
#define AODMIC_SOFT_RESET_0_SOFT_RESET_WOFFSET                  0x0
#define AODMIC_SOFT_RESET_0_SOFT_RESET_DEFAULT                  MK_MASK_CONST(0x0)
#define AODMIC_SOFT_RESET_0_SOFT_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define AODMIC_SOFT_RESET_0_SOFT_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define AODMIC_SOFT_RESET_0_SOFT_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define AODMIC_SOFT_RESET_0_SOFT_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define AODMIC_SOFT_RESET_0_SOFT_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define AODMIC_SOFT_RESET_0_SOFT_RESET_INIT_ENUM                        FALSE
#define AODMIC_SOFT_RESET_0_SOFT_RESET_FALSE                    MK_ENUM_CONST(0)
#define AODMIC_SOFT_RESET_0_SOFT_RESET_TRUE                     MK_ENUM_CONST(1)


// Register AODMIC_CG_0
#define AODMIC_CG_0                     MK_ADDR_CONST(0x48)
#define AODMIC_CG_0_SECURE                      0x0
#define AODMIC_CG_0_DUAL                        0x0
#define AODMIC_CG_0_SCR                         0
#define AODMIC_CG_0_SCRREG                      0
#define AODMIC_CG_0_WORD_COUNT                  0x1
#define AODMIC_CG_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define AODMIC_CG_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define AODMIC_CG_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define AODMIC_CG_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define AODMIC_CG_0_READ_MASK                   MK_MASK_CONST(0x1)
#define AODMIC_CG_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define AODMIC_CG_0_SLCG_EN_SHIFT                       MK_SHIFT_CONST(0)
#define AODMIC_CG_0_SLCG_EN_FIELD                       MK_FIELD_CONST(0x1, AODMIC_CG_0_SLCG_EN_SHIFT)
#define AODMIC_CG_0_SLCG_EN_RANGE                       0:0
#define AODMIC_CG_0_SLCG_EN_MSB                 MK_SHIFT_CONST(0)
#define AODMIC_CG_0_SLCG_EN_LSB                 MK_SHIFT_CONST(0)
#define AODMIC_CG_0_SLCG_EN_WOFFSET                     0x0
#define AODMIC_CG_0_SLCG_EN_DEFAULT                     MK_MASK_CONST(0x1)
#define AODMIC_CG_0_SLCG_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define AODMIC_CG_0_SLCG_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define AODMIC_CG_0_SLCG_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define AODMIC_CG_0_SLCG_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define AODMIC_CG_0_SLCG_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define AODMIC_CG_0_SLCG_EN_INIT_ENUM                   TRUE
#define AODMIC_CG_0_SLCG_EN_FALSE                       MK_ENUM_CONST(0)
#define AODMIC_CG_0_SLCG_EN_TRUE                        MK_ENUM_CONST(1)


// Register AODMIC_STATUS_0
#define AODMIC_STATUS_0                 MK_ADDR_CONST(0x4c)
#define AODMIC_STATUS_0_SECURE                  0x0
#define AODMIC_STATUS_0_DUAL                    0x0
#define AODMIC_STATUS_0_SCR                     0
#define AODMIC_STATUS_0_SCRREG                  0
#define AODMIC_STATUS_0_WORD_COUNT                      0x1
#define AODMIC_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x10)
#define AODMIC_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x80000131)
#define AODMIC_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_READ_MASK                       MK_MASK_CONST(0x80000131)
#define AODMIC_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_CNFG_ERR_SHIFT                  MK_SHIFT_CONST(31)
#define AODMIC_STATUS_0_CNFG_ERR_FIELD                  MK_FIELD_CONST(0x1, AODMIC_STATUS_0_CNFG_ERR_SHIFT)
#define AODMIC_STATUS_0_CNFG_ERR_RANGE                  31:31
#define AODMIC_STATUS_0_CNFG_ERR_MSB                    MK_SHIFT_CONST(31)
#define AODMIC_STATUS_0_CNFG_ERR_LSB                    MK_SHIFT_CONST(31)
#define AODMIC_STATUS_0_CNFG_ERR_WOFFSET                        0x0
#define AODMIC_STATUS_0_CNFG_ERR_DEFAULT                        MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_CNFG_ERR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define AODMIC_STATUS_0_CNFG_ERR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_CNFG_ERR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_CNFG_ERR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_CNFG_ERR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define AODMIC_STATUS_0_CNFG_ERR_INIT_ENUM                      FALSE
#define AODMIC_STATUS_0_CNFG_ERR_FALSE                  MK_ENUM_CONST(0)
#define AODMIC_STATUS_0_CNFG_ERR_TRUE                   MK_ENUM_CONST(1)

#define AODMIC_STATUS_0_SLCG_CLKEN_SHIFT                        MK_SHIFT_CONST(8)
#define AODMIC_STATUS_0_SLCG_CLKEN_FIELD                        MK_FIELD_CONST(0x1, AODMIC_STATUS_0_SLCG_CLKEN_SHIFT)
#define AODMIC_STATUS_0_SLCG_CLKEN_RANGE                        8:8
#define AODMIC_STATUS_0_SLCG_CLKEN_MSB                  MK_SHIFT_CONST(8)
#define AODMIC_STATUS_0_SLCG_CLKEN_LSB                  MK_SHIFT_CONST(8)
#define AODMIC_STATUS_0_SLCG_CLKEN_WOFFSET                      0x0
#define AODMIC_STATUS_0_SLCG_CLKEN_DEFAULT                      MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_SLCG_CLKEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define AODMIC_STATUS_0_SLCG_CLKEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_SLCG_CLKEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_SLCG_CLKEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_SLCG_CLKEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define AODMIC_STATUS_0_SLCG_CLKEN_INIT_ENUM                    FALSE
#define AODMIC_STATUS_0_SLCG_CLKEN_FALSE                        MK_ENUM_CONST(0)
#define AODMIC_STATUS_0_SLCG_CLKEN_TRUE                 MK_ENUM_CONST(1)

#define AODMIC_STATUS_0_FIFO_FULL_SHIFT                 MK_SHIFT_CONST(5)
#define AODMIC_STATUS_0_FIFO_FULL_FIELD                 MK_FIELD_CONST(0x1, AODMIC_STATUS_0_FIFO_FULL_SHIFT)
#define AODMIC_STATUS_0_FIFO_FULL_RANGE                 5:5
#define AODMIC_STATUS_0_FIFO_FULL_MSB                   MK_SHIFT_CONST(5)
#define AODMIC_STATUS_0_FIFO_FULL_LSB                   MK_SHIFT_CONST(5)
#define AODMIC_STATUS_0_FIFO_FULL_WOFFSET                       0x0
#define AODMIC_STATUS_0_FIFO_FULL_DEFAULT                       MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_FIFO_FULL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define AODMIC_STATUS_0_FIFO_FULL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_FIFO_FULL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_FIFO_FULL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_FIFO_FULL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define AODMIC_STATUS_0_FIFO_FULL_INIT_ENUM                     FALSE
#define AODMIC_STATUS_0_FIFO_FULL_FALSE                 MK_ENUM_CONST(0)
#define AODMIC_STATUS_0_FIFO_FULL_TRUE                  MK_ENUM_CONST(1)

#define AODMIC_STATUS_0_FIFO_EMPTY_SHIFT                        MK_SHIFT_CONST(4)
#define AODMIC_STATUS_0_FIFO_EMPTY_FIELD                        MK_FIELD_CONST(0x1, AODMIC_STATUS_0_FIFO_EMPTY_SHIFT)
#define AODMIC_STATUS_0_FIFO_EMPTY_RANGE                        4:4
#define AODMIC_STATUS_0_FIFO_EMPTY_MSB                  MK_SHIFT_CONST(4)
#define AODMIC_STATUS_0_FIFO_EMPTY_LSB                  MK_SHIFT_CONST(4)
#define AODMIC_STATUS_0_FIFO_EMPTY_WOFFSET                      0x0
#define AODMIC_STATUS_0_FIFO_EMPTY_DEFAULT                      MK_MASK_CONST(0x1)
#define AODMIC_STATUS_0_FIFO_EMPTY_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define AODMIC_STATUS_0_FIFO_EMPTY_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_FIFO_EMPTY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_FIFO_EMPTY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_FIFO_EMPTY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define AODMIC_STATUS_0_FIFO_EMPTY_INIT_ENUM                    TRUE
#define AODMIC_STATUS_0_FIFO_EMPTY_FALSE                        MK_ENUM_CONST(0)
#define AODMIC_STATUS_0_FIFO_EMPTY_TRUE                 MK_ENUM_CONST(1)

#define AODMIC_STATUS_0_ENABLE_STATUS_SHIFT                     MK_SHIFT_CONST(0)
#define AODMIC_STATUS_0_ENABLE_STATUS_FIELD                     MK_FIELD_CONST(0x1, AODMIC_STATUS_0_ENABLE_STATUS_SHIFT)
#define AODMIC_STATUS_0_ENABLE_STATUS_RANGE                     0:0
#define AODMIC_STATUS_0_ENABLE_STATUS_MSB                       MK_SHIFT_CONST(0)
#define AODMIC_STATUS_0_ENABLE_STATUS_LSB                       MK_SHIFT_CONST(0)
#define AODMIC_STATUS_0_ENABLE_STATUS_WOFFSET                   0x0
#define AODMIC_STATUS_0_ENABLE_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_ENABLE_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define AODMIC_STATUS_0_ENABLE_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_ENABLE_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_ENABLE_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define AODMIC_STATUS_0_ENABLE_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define AODMIC_STATUS_0_ENABLE_STATUS_INIT_ENUM                 FALSE
#define AODMIC_STATUS_0_ENABLE_STATUS_FALSE                     MK_ENUM_CONST(0)
#define AODMIC_STATUS_0_ENABLE_STATUS_TRUE                      MK_ENUM_CONST(1)


// Register AODMIC_INT_STATUS_0
#define AODMIC_INT_STATUS_0                     MK_ADDR_CONST(0x50)
#define AODMIC_INT_STATUS_0_SECURE                      0x0
#define AODMIC_INT_STATUS_0_DUAL                        0x0
#define AODMIC_INT_STATUS_0_SCR                         0
#define AODMIC_INT_STATUS_0_SCRREG                      0
#define AODMIC_INT_STATUS_0_WORD_COUNT                  0x1
#define AODMIC_INT_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define AODMIC_INT_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x101)
#define AODMIC_INT_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define AODMIC_INT_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define AODMIC_INT_STATUS_0_READ_MASK                   MK_MASK_CONST(0x101)
#define AODMIC_INT_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define AODMIC_INT_STATUS_0_RX_OVERRUN_SHIFT                    MK_SHIFT_CONST(8)
#define AODMIC_INT_STATUS_0_RX_OVERRUN_FIELD                    MK_FIELD_CONST(0x1, AODMIC_INT_STATUS_0_RX_OVERRUN_SHIFT)
#define AODMIC_INT_STATUS_0_RX_OVERRUN_RANGE                    8:8
#define AODMIC_INT_STATUS_0_RX_OVERRUN_MSB                      MK_SHIFT_CONST(8)
#define AODMIC_INT_STATUS_0_RX_OVERRUN_LSB                      MK_SHIFT_CONST(8)
#define AODMIC_INT_STATUS_0_RX_OVERRUN_WOFFSET                  0x0
#define AODMIC_INT_STATUS_0_RX_OVERRUN_DEFAULT                  MK_MASK_CONST(0x0)
#define AODMIC_INT_STATUS_0_RX_OVERRUN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define AODMIC_INT_STATUS_0_RX_OVERRUN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define AODMIC_INT_STATUS_0_RX_OVERRUN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define AODMIC_INT_STATUS_0_RX_OVERRUN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define AODMIC_INT_STATUS_0_RX_OVERRUN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define AODMIC_INT_STATUS_0_RX_OVERRUN_INIT_ENUM                        CLEAR
#define AODMIC_INT_STATUS_0_RX_OVERRUN_CLEAR                    MK_ENUM_CONST(0)
#define AODMIC_INT_STATUS_0_RX_OVERRUN_SET                      MK_ENUM_CONST(1)

#define AODMIC_INT_STATUS_0_RX_DONE_SHIFT                       MK_SHIFT_CONST(0)
#define AODMIC_INT_STATUS_0_RX_DONE_FIELD                       MK_FIELD_CONST(0x1, AODMIC_INT_STATUS_0_RX_DONE_SHIFT)
#define AODMIC_INT_STATUS_0_RX_DONE_RANGE                       0:0
#define AODMIC_INT_STATUS_0_RX_DONE_MSB                 MK_SHIFT_CONST(0)
#define AODMIC_INT_STATUS_0_RX_DONE_LSB                 MK_SHIFT_CONST(0)
#define AODMIC_INT_STATUS_0_RX_DONE_WOFFSET                     0x0
#define AODMIC_INT_STATUS_0_RX_DONE_DEFAULT                     MK_MASK_CONST(0x0)
#define AODMIC_INT_STATUS_0_RX_DONE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define AODMIC_INT_STATUS_0_RX_DONE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define AODMIC_INT_STATUS_0_RX_DONE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define AODMIC_INT_STATUS_0_RX_DONE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define AODMIC_INT_STATUS_0_RX_DONE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define AODMIC_INT_STATUS_0_RX_DONE_INIT_ENUM                   CLEAR
#define AODMIC_INT_STATUS_0_RX_DONE_CLEAR                       MK_ENUM_CONST(0)
#define AODMIC_INT_STATUS_0_RX_DONE_SET                 MK_ENUM_CONST(1)


// Reserved address 0x54

// Reserved address 0x58

// Reserved address 0x5c

// Reserved address 0x60

// Register AODMIC_CTRL_0
#define AODMIC_CTRL_0                   MK_ADDR_CONST(0x64)
#define AODMIC_CTRL_0_SECURE                    0x0
#define AODMIC_CTRL_0_DUAL                      0x0
#define AODMIC_CTRL_0_SCR                       0
#define AODMIC_CTRL_0_SCRREG                    0
#define AODMIC_CTRL_0_WORD_COUNT                        0x1
#define AODMIC_CTRL_0_RESET_VAL                         MK_MASK_CONST(0x300)
#define AODMIC_CTRL_0_RESET_MASK                        MK_MASK_CONST(0x313)
#define AODMIC_CTRL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define AODMIC_CTRL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define AODMIC_CTRL_0_READ_MASK                         MK_MASK_CONST(0x313)
#define AODMIC_CTRL_0_WRITE_MASK                        MK_MASK_CONST(0x313)
#define AODMIC_CTRL_0_CHANNEL_SELECT_SHIFT                      MK_SHIFT_CONST(8)
#define AODMIC_CTRL_0_CHANNEL_SELECT_FIELD                      MK_FIELD_CONST(0x3, AODMIC_CTRL_0_CHANNEL_SELECT_SHIFT)
#define AODMIC_CTRL_0_CHANNEL_SELECT_RANGE                      9:8
#define AODMIC_CTRL_0_CHANNEL_SELECT_MSB                        MK_SHIFT_CONST(9)
#define AODMIC_CTRL_0_CHANNEL_SELECT_LSB                        MK_SHIFT_CONST(8)
#define AODMIC_CTRL_0_CHANNEL_SELECT_WOFFSET                    0x0
#define AODMIC_CTRL_0_CHANNEL_SELECT_DEFAULT                    MK_MASK_CONST(0x3)
#define AODMIC_CTRL_0_CHANNEL_SELECT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
#define AODMIC_CTRL_0_CHANNEL_SELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define AODMIC_CTRL_0_CHANNEL_SELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define AODMIC_CTRL_0_CHANNEL_SELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define AODMIC_CTRL_0_CHANNEL_SELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define AODMIC_CTRL_0_CHANNEL_SELECT_INIT_ENUM                  STEREO
#define AODMIC_CTRL_0_CHANNEL_SELECT_NONE                       MK_ENUM_CONST(0)
#define AODMIC_CTRL_0_CHANNEL_SELECT_LEFT                       MK_ENUM_CONST(1)
#define AODMIC_CTRL_0_CHANNEL_SELECT_RIGHT                      MK_ENUM_CONST(2)
#define AODMIC_CTRL_0_CHANNEL_SELECT_STEREO                     MK_ENUM_CONST(3)

#define AODMIC_CTRL_0_LRSEL_POLARITY_SHIFT                      MK_SHIFT_CONST(4)
#define AODMIC_CTRL_0_LRSEL_POLARITY_FIELD                      MK_FIELD_CONST(0x1, AODMIC_CTRL_0_LRSEL_POLARITY_SHIFT)
#define AODMIC_CTRL_0_LRSEL_POLARITY_RANGE                      4:4
#define AODMIC_CTRL_0_LRSEL_POLARITY_MSB                        MK_SHIFT_CONST(4)
#define AODMIC_CTRL_0_LRSEL_POLARITY_LSB                        MK_SHIFT_CONST(4)
#define AODMIC_CTRL_0_LRSEL_POLARITY_WOFFSET                    0x0
#define AODMIC_CTRL_0_LRSEL_POLARITY_DEFAULT                    MK_MASK_CONST(0x0)
#define AODMIC_CTRL_0_LRSEL_POLARITY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define AODMIC_CTRL_0_LRSEL_POLARITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define AODMIC_CTRL_0_LRSEL_POLARITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define AODMIC_CTRL_0_LRSEL_POLARITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define AODMIC_CTRL_0_LRSEL_POLARITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define AODMIC_CTRL_0_LRSEL_POLARITY_INIT_ENUM                  LEFT
#define AODMIC_CTRL_0_LRSEL_POLARITY_LEFT                       MK_ENUM_CONST(0)
#define AODMIC_CTRL_0_LRSEL_POLARITY_RIGHT                      MK_ENUM_CONST(1)

#define AODMIC_CTRL_0_OSR_SHIFT                 MK_SHIFT_CONST(0)
#define AODMIC_CTRL_0_OSR_FIELD                 MK_FIELD_CONST(0x3, AODMIC_CTRL_0_OSR_SHIFT)
#define AODMIC_CTRL_0_OSR_RANGE                 1:0
#define AODMIC_CTRL_0_OSR_MSB                   MK_SHIFT_CONST(1)
#define AODMIC_CTRL_0_OSR_LSB                   MK_SHIFT_CONST(0)
#define AODMIC_CTRL_0_OSR_WOFFSET                       0x0
#define AODMIC_CTRL_0_OSR_DEFAULT                       MK_MASK_CONST(0x0)
#define AODMIC_CTRL_0_OSR_DEFAULT_MASK                  MK_MASK_CONST(0x3)
#define AODMIC_CTRL_0_OSR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define AODMIC_CTRL_0_OSR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define AODMIC_CTRL_0_OSR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define AODMIC_CTRL_0_OSR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define AODMIC_CTRL_0_OSR_INIT_ENUM                     OSR64
#define AODMIC_CTRL_0_OSR_OSR64                 MK_ENUM_CONST(0)
#define AODMIC_CTRL_0_OSR_OSR128                        MK_ENUM_CONST(1)
#define AODMIC_CTRL_0_OSR_OSR256                        MK_ENUM_CONST(2)


// Register AODMIC_CYA_0
#define AODMIC_CYA_0                    MK_ADDR_CONST(0x68)
#define AODMIC_CYA_0_SECURE                     0x0
#define AODMIC_CYA_0_DUAL                       0x0
#define AODMIC_CYA_0_SCR                        0
#define AODMIC_CYA_0_SCRREG                     0
#define AODMIC_CYA_0_WORD_COUNT                         0x1
#define AODMIC_CYA_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define AODMIC_CYA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define AODMIC_CYA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define AODMIC_CYA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define AODMIC_CYA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define AODMIC_CYA_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define AODMIC_CYA_0_CYA_SHIFT                  MK_SHIFT_CONST(0)
#define AODMIC_CYA_0_CYA_FIELD                  MK_FIELD_CONST(0xffffffff, AODMIC_CYA_0_CYA_SHIFT)
#define AODMIC_CYA_0_CYA_RANGE                  31:0
#define AODMIC_CYA_0_CYA_MSB                    MK_SHIFT_CONST(31)
#define AODMIC_CYA_0_CYA_LSB                    MK_SHIFT_CONST(0)
#define AODMIC_CYA_0_CYA_WOFFSET                        0x0
#define AODMIC_CYA_0_CYA_DEFAULT                        MK_MASK_CONST(0x0)
#define AODMIC_CYA_0_CYA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define AODMIC_CYA_0_CYA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define AODMIC_CYA_0_CYA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AODMIC_CYA_0_CYA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define AODMIC_CYA_0_CYA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register AODMIC_CYA
#define AODMIC_CYA                      MK_ADDR_CONST(0x68)
#define AODMIC_CYA_SECURE                       0x0
#define AODMIC_CYA_DUAL                         0x0
#define AODMIC_CYA_SCR                  0
#define AODMIC_CYA_SCRREG                       0
#define AODMIC_CYA_WORD_COUNT                   0x1
#define AODMIC_CYA_RESET_VAL                    MK_MASK_CONST(0x0)
#define AODMIC_CYA_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define AODMIC_CYA_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define AODMIC_CYA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define AODMIC_CYA_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define AODMIC_CYA_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define AODMIC_CYA_CYA_SHIFT                    MK_SHIFT_CONST(0)
#define AODMIC_CYA_CYA_FIELD                    MK_FIELD_CONST(0xffffffff, AODMIC_CYA_CYA_SHIFT)
#define AODMIC_CYA_CYA_RANGE                    31:0
#define AODMIC_CYA_CYA_MSB                      MK_SHIFT_CONST(31)
#define AODMIC_CYA_CYA_LSB                      MK_SHIFT_CONST(0)
#define AODMIC_CYA_CYA_WOFFSET                  0x0
#define AODMIC_CYA_CYA_DEFAULT                  MK_MASK_CONST(0x0)
#define AODMIC_CYA_CYA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define AODMIC_CYA_CYA_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define AODMIC_CYA_CYA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define AODMIC_CYA_CYA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define AODMIC_CYA_CYA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register AODMIC_CYA_1
#define AODMIC_CYA_1                    MK_ADDR_CONST(0x6c)
#define AODMIC_CYA_1_SECURE                     0x0
#define AODMIC_CYA_1_DUAL                       0x0
#define AODMIC_CYA_1_SCR                        0
#define AODMIC_CYA_1_SCRREG                     0
#define AODMIC_CYA_1_WORD_COUNT                         0x1
#define AODMIC_CYA_1_RESET_VAL                  MK_MASK_CONST(0x0)
#define AODMIC_CYA_1_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define AODMIC_CYA_1_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define AODMIC_CYA_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define AODMIC_CYA_1_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define AODMIC_CYA_1_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define AODMIC_CYA_1_CYA_SHIFT                  MK_SHIFT_CONST(0)
#define AODMIC_CYA_1_CYA_FIELD                  MK_FIELD_CONST(0xffffffff, AODMIC_CYA_1_CYA_SHIFT)
#define AODMIC_CYA_1_CYA_RANGE                  31:0
#define AODMIC_CYA_1_CYA_MSB                    MK_SHIFT_CONST(31)
#define AODMIC_CYA_1_CYA_LSB                    MK_SHIFT_CONST(0)
#define AODMIC_CYA_1_CYA_WOFFSET                        0x0
#define AODMIC_CYA_1_CYA_DEFAULT                        MK_MASK_CONST(0x0)
#define AODMIC_CYA_1_CYA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define AODMIC_CYA_1_CYA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define AODMIC_CYA_1_CYA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AODMIC_CYA_1_CYA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define AODMIC_CYA_1_CYA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register AODMIC_DBG_CTRL_0
#define AODMIC_DBG_CTRL_0                       MK_ADDR_CONST(0x70)
#define AODMIC_DBG_CTRL_0_SECURE                        0x0
#define AODMIC_DBG_CTRL_0_DUAL                  0x0
#define AODMIC_DBG_CTRL_0_SCR                   0
#define AODMIC_DBG_CTRL_0_SCRREG                        0
#define AODMIC_DBG_CTRL_0_WORD_COUNT                    0x1
#define AODMIC_DBG_CTRL_0_RESET_VAL                     MK_MASK_CONST(0x2)
#define AODMIC_DBG_CTRL_0_RESET_MASK                    MK_MASK_CONST(0xf)
#define AODMIC_DBG_CTRL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_READ_MASK                     MK_MASK_CONST(0xf)
#define AODMIC_DBG_CTRL_0_WRITE_MASK                    MK_MASK_CONST(0xf)
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_SHIFT                      MK_SHIFT_CONST(3)
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, AODMIC_DBG_CTRL_0_DCR_ENABLE_SHIFT)
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_RANGE                      3:3
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_MSB                        MK_SHIFT_CONST(3)
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_LSB                        MK_SHIFT_CONST(3)
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_WOFFSET                    0x0
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_INIT_ENUM                  DISABLE
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_DISABLE                    MK_ENUM_CONST(0)
#define AODMIC_DBG_CTRL_0_DCR_ENABLE_ENABLE                     MK_ENUM_CONST(1)

#define AODMIC_DBG_CTRL_0_LP_ENABLE_SHIFT                       MK_SHIFT_CONST(2)
#define AODMIC_DBG_CTRL_0_LP_ENABLE_FIELD                       MK_FIELD_CONST(0x1, AODMIC_DBG_CTRL_0_LP_ENABLE_SHIFT)
#define AODMIC_DBG_CTRL_0_LP_ENABLE_RANGE                       2:2
#define AODMIC_DBG_CTRL_0_LP_ENABLE_MSB                 MK_SHIFT_CONST(2)
#define AODMIC_DBG_CTRL_0_LP_ENABLE_LSB                 MK_SHIFT_CONST(2)
#define AODMIC_DBG_CTRL_0_LP_ENABLE_WOFFSET                     0x0
#define AODMIC_DBG_CTRL_0_LP_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_LP_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define AODMIC_DBG_CTRL_0_LP_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_LP_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_LP_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_LP_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define AODMIC_DBG_CTRL_0_LP_ENABLE_INIT_ENUM                   DISABLE
#define AODMIC_DBG_CTRL_0_LP_ENABLE_DISABLE                     MK_ENUM_CONST(0)
#define AODMIC_DBG_CTRL_0_LP_ENABLE_ENABLE                      MK_ENUM_CONST(1)

#define AODMIC_DBG_CTRL_0_SC_ENABLE_SHIFT                       MK_SHIFT_CONST(1)
#define AODMIC_DBG_CTRL_0_SC_ENABLE_FIELD                       MK_FIELD_CONST(0x1, AODMIC_DBG_CTRL_0_SC_ENABLE_SHIFT)
#define AODMIC_DBG_CTRL_0_SC_ENABLE_RANGE                       1:1
#define AODMIC_DBG_CTRL_0_SC_ENABLE_MSB                 MK_SHIFT_CONST(1)
#define AODMIC_DBG_CTRL_0_SC_ENABLE_LSB                 MK_SHIFT_CONST(1)
#define AODMIC_DBG_CTRL_0_SC_ENABLE_WOFFSET                     0x0
#define AODMIC_DBG_CTRL_0_SC_ENABLE_DEFAULT                     MK_MASK_CONST(0x1)
#define AODMIC_DBG_CTRL_0_SC_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define AODMIC_DBG_CTRL_0_SC_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_SC_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_SC_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_SC_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define AODMIC_DBG_CTRL_0_SC_ENABLE_INIT_ENUM                   ENABLE
#define AODMIC_DBG_CTRL_0_SC_ENABLE_DISABLE                     MK_ENUM_CONST(0)
#define AODMIC_DBG_CTRL_0_SC_ENABLE_ENABLE                      MK_ENUM_CONST(1)

#define AODMIC_DBG_CTRL_0_BYPASS_SHIFT                  MK_SHIFT_CONST(0)
#define AODMIC_DBG_CTRL_0_BYPASS_FIELD                  MK_FIELD_CONST(0x1, AODMIC_DBG_CTRL_0_BYPASS_SHIFT)
#define AODMIC_DBG_CTRL_0_BYPASS_RANGE                  0:0
#define AODMIC_DBG_CTRL_0_BYPASS_MSB                    MK_SHIFT_CONST(0)
#define AODMIC_DBG_CTRL_0_BYPASS_LSB                    MK_SHIFT_CONST(0)
#define AODMIC_DBG_CTRL_0_BYPASS_WOFFSET                        0x0
#define AODMIC_DBG_CTRL_0_BYPASS_DEFAULT                        MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_BYPASS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define AODMIC_DBG_CTRL_0_BYPASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_BYPASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_BYPASS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define AODMIC_DBG_CTRL_0_BYPASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define AODMIC_DBG_CTRL_0_BYPASS_INIT_ENUM                      DISABLE
#define AODMIC_DBG_CTRL_0_BYPASS_DISABLE                        MK_ENUM_CONST(0)
#define AODMIC_DBG_CTRL_0_BYPASS_ENABLE                 MK_ENUM_CONST(1)


// Register AODMIC_DCR_FILTER_GAIN_0
#define AODMIC_DCR_FILTER_GAIN_0                        MK_ADDR_CONST(0x74)
#define AODMIC_DCR_FILTER_GAIN_0_SECURE                         0x0
#define AODMIC_DCR_FILTER_GAIN_0_DUAL                   0x0
#define AODMIC_DCR_FILTER_GAIN_0_SCR                    0
#define AODMIC_DCR_FILTER_GAIN_0_SCRREG                         0
#define AODMIC_DCR_FILTER_GAIN_0_WORD_COUNT                     0x1
#define AODMIC_DCR_FILTER_GAIN_0_RESET_VAL                      MK_MASK_CONST(0x800000)
#define AODMIC_DCR_FILTER_GAIN_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define AODMIC_DCR_FILTER_GAIN_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define AODMIC_DCR_FILTER_GAIN_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AODMIC_DCR_FILTER_GAIN_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define AODMIC_DCR_FILTER_GAIN_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_SHIFT                   MK_SHIFT_CONST(0)
#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_FIELD                   MK_FIELD_CONST(0xffffffff, AODMIC_DCR_FILTER_GAIN_0_GAIN_0_SHIFT)
#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_RANGE                   31:0
#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_MSB                     MK_SHIFT_CONST(31)
#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_LSB                     MK_SHIFT_CONST(0)
#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_WOFFSET                 0x0
#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_DEFAULT                 MK_MASK_CONST(0x800000)
#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register AODMIC_LP_FILTER_GAIN_0
#define AODMIC_LP_FILTER_GAIN_0                 MK_ADDR_CONST(0x8c)
#define AODMIC_LP_FILTER_GAIN_0_SECURE                  0x0
#define AODMIC_LP_FILTER_GAIN_0_DUAL                    0x0
#define AODMIC_LP_FILTER_GAIN_0_SCR                     0
#define AODMIC_LP_FILTER_GAIN_0_SCRREG                  0
#define AODMIC_LP_FILTER_GAIN_0_WORD_COUNT                      0x1
#define AODMIC_LP_FILTER_GAIN_0_RESET_VAL                       MK_MASK_CONST(0x4c255a)
#define AODMIC_LP_FILTER_GAIN_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define AODMIC_LP_FILTER_GAIN_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define AODMIC_LP_FILTER_GAIN_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define AODMIC_LP_FILTER_GAIN_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define AODMIC_LP_FILTER_GAIN_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_SHIFT                    MK_SHIFT_CONST(0)
#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_FIELD                    MK_FIELD_CONST(0xffffffff, AODMIC_LP_FILTER_GAIN_0_GAIN_0_SHIFT)
#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_RANGE                    31:0
#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_MSB                      MK_SHIFT_CONST(31)
#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_LSB                      MK_SHIFT_CONST(0)
#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_WOFFSET                  0x0
#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_DEFAULT                  MK_MASK_CONST(0x4c255a)
#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register AODMIC_CORRECTION_FILTER_GAIN_0
#define AODMIC_CORRECTION_FILTER_GAIN_0                 MK_ADDR_CONST(0xb8)
#define AODMIC_CORRECTION_FILTER_GAIN_0_SECURE                  0x0
#define AODMIC_CORRECTION_FILTER_GAIN_0_DUAL                    0x0
#define AODMIC_CORRECTION_FILTER_GAIN_0_SCR                     0
#define AODMIC_CORRECTION_FILTER_GAIN_0_SCRREG                  0
#define AODMIC_CORRECTION_FILTER_GAIN_0_WORD_COUNT                      0x1
#define AODMIC_CORRECTION_FILTER_GAIN_0_RESET_VAL                       MK_MASK_CONST(0x10628f6)
#define AODMIC_CORRECTION_FILTER_GAIN_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define AODMIC_CORRECTION_FILTER_GAIN_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define AODMIC_CORRECTION_FILTER_GAIN_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define AODMIC_CORRECTION_FILTER_GAIN_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define AODMIC_CORRECTION_FILTER_GAIN_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_SHIFT                    MK_SHIFT_CONST(0)
#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_FIELD                    MK_FIELD_CONST(0xffffffff, AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_SHIFT)
#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_RANGE                    31:0
#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_MSB                      MK_SHIFT_CONST(31)
#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_LSB                      MK_SHIFT_CONST(0)
#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_WOFFSET                  0x0
#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_DEFAULT                  MK_MASK_CONST(0x10628f6)
#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


#define NV_AODMIC_INT4  4
#define NV_AODMIC_INT6  6
#define NV_AODMIC_INT8  8
#define NV_AODMIC_INT16 16
#define NV_AODMIC_INT24 24
#define NV_AODMIC_INT32 32
#define NV_AODMIC_INT40 40
#define NV_AODMIC_INT43 43
#define NV_AODMIC_INT48 48
#define NV_AODMIC_INT64 64
#define NV_AODMIC_INT128        128
#define NV_AODMIC_INT256        256
#define NV_AODMIC_INT512        512
#define NV_AODMIC_INT1024       1024
#define NV_AODMIC_INT1280       1280
#define NV_AODMIC_MAX_OSR       64
#define NV_AODMIC_MAX_SYNCDECIMATION_ORDER      5
#define NV_AODMIC_MIN_OSR       64
#define NV_AODMIC_DIFF_OUTPUT_WIDTH     16

//
// REGISTER LIST
//
#define LIST_ARAODMIC_REGS(_op_) \
_op_(AODMIC_APB_FIFO_CTRL_0) \
_op_(AODMIC_APB_FIFO_CTRL_RD_DATA_0) \
_op_(AODMIC_APB_FIFO_STATUS_0) \
_op_(AODMIC_APB_RX_INT_STATUS_0) \
_op_(AODMIC_APB_RX_INT_MASK_0) \
_op_(AODMIC_APB_RX_INT_SET_0) \
_op_(AODMIC_APB_RX_INT_CLEAR_0) \
_op_(AODMIC_ENABLE_0) \
_op_(AODMIC_SOFT_RESET_0) \
_op_(AODMIC_CG_0) \
_op_(AODMIC_STATUS_0) \
_op_(AODMIC_INT_STATUS_0) \
_op_(AODMIC_CTRL_0) \
_op_(AODMIC_CYA_0) \
_op_(AODMIC_CYA) \
_op_(AODMIC_CYA_1) \
_op_(AODMIC_DBG_CTRL_0) \
_op_(AODMIC_DCR_FILTER_GAIN_0) \
_op_(AODMIC_LP_FILTER_GAIN_0) \
_op_(AODMIC_CORRECTION_FILTER_GAIN_0) \


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_AODMIC_APB 0x00000000
#define BASE_ADDRESS_AODMIC     0x00000040

//
// ARAODMIC REGISTER BANKS
//

#define AODMIC_APB0_FIRST_REG 0x0000 // AODMIC_APB_FIFO_CTRL_0
#define AODMIC_APB0_LAST_REG 0x0018 // AODMIC_APB_RX_INT_CLEAR_0
#define AODMIC0_FIRST_REG 0x0040 // AODMIC_ENABLE_0
#define AODMIC0_LAST_REG 0x0050 // AODMIC_INT_STATUS_0
#define AODMIC1_FIRST_REG 0x0064 // AODMIC_CTRL_0
#define AODMIC1_LAST_REG 0x00e0 // AODMIC_CORRECTION_BIQUAD_1_COEF_4_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARAODMIC_H_INC
