/**
 * @file fence.h
 *
 * @brief NVRISC-V fence wrappers
 *
 * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * * Redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer.
 * * Redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution.
 * * Neither the name of NVIDIA CORPORATION nor the names of its
 * contributors may be used to endorse or promote products derived
 * from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef CPU__FENCE_H
#define CPU__FENCE_H
#define FSP__CPU__FENCE_H                       1

/*
 * @file fence.h
 * Lightweight fence, may not be coherent with rest of the system
 */

/* Compiler headers */
#include <stdint.h>

/* Early FSP headers */
#include <misc/macros.h>                  // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
#include <misc/ct-assert.h>               // for CT_ASSERT

/* Hardware headers */

/* Late FSP headers */
#include <cpu/csr.h>

/*
 * Compile-time check for FSP header files
 *   Each FSP header file contains a signature unique to that file, and the
 *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
 *   check for this signature.  If it does not exist, then the build will
 *   abort.
 *
 *   This is a trap for projects which have their own include files of the
 *   same names, but different contents.  This trap ensures that only the
 *   files from the FSP project, are built into the FSP source code.
 */
START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
CT_ASSERT(FSP__CPU__CSR_H, "Header file missing or invalid.")
END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")

/**
 * @brief lightweight io fence wrapper
 */
static inline void riscv_lw_fence_io(void)
{
    __asm__ volatile ("csrrw zero, %0, zero" : : "i"(NV_RISCV_CSR_LWFENCEIO));
}

/**
 * @brief lightweight memory fence wrapper
 */
static inline void riscv_lw_fence_rw(void)
{
    __asm__ volatile ("csrrw zero, %0, zero" : : "i"(NV_RISCV_CSR_LWFENCEMEM));
}

/**
 * @brief lightweight fence wrapper for io and memory
 */
static inline void riscv_lw_fence_rwio(void)
{
    __asm__ volatile ("csrrw zero, %0, zero" : : "i"(NV_RISCV_CSR_LWFENCEALL));
}

/**
 * @brief heavy-weight io fence wrapper
 */
static inline void riscv_fence_io(void)
{
    __asm__ volatile ("fence io,io");
}

/**
 * @brief heavy-weight memory fence wrapper
 */
static inline void riscv_fence_rw(void)
{
    __asm__ volatile ("fence rw,rw");
}

/**
 * @brief heavy-weight fence wrapper for io and memory
 */
static inline void riscv_fence_rwio(void)
{
    __asm__ volatile ("fence iorw,iorw");
}

/**
 * @brief heavy-weight supervisor fence wrapper
 *
 * Synchronize updates to in-memory management data structures
 * with current execution.
 *
 * @param[in] asid      ASID value
 * @param[in] vaddr     virtual address value
 */
static inline void riscv_sfence_vma(uint8_t asid, uint8_t vaddr)
{
    __asm__ volatile ("sfence.vma %0, %1" :: "r" (asid), "r" (vaddr));
}

/**
 * @brief heavy-weight instruction fence
 */
static inline void riscv_fence_instr(void)
{
    __asm__ __volatile__("fence.i");
}

#endif /* FSP__CPU__FENCE_H */
