//
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//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARHSP_SHRD_SEM_H_INC
#define ARHSP_SHRD_SEM_H_INC
#define NV_MOBILE_ARHSP_SHRD_SEM_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARHSP_SHRD_SEM_H_SCRREG_NOMENCLATURE EXACT


// Register HSP_SHRD_SEM_0_SHRD_SMP_STA_0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SECURE                    0x0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_DUAL                      0x0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SCR                       SS_0_REG_0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_0_REG_0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_WORD_COUNT                        0x1
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_SHIFT)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_RANGE                 31:0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x4)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SECURE                        0x0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_DUAL                  0x0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SCR                   SS_0_REG_0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_0_REG_0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x8)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SECURE                        0x0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_DUAL                  0x0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SCR                   SS_0_REG_0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_0_REG_0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_1_SHRD_SMP_STA_0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x10000)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SECURE                    0x0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_DUAL                      0x0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SCR                       SS_1_REG_0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_1_REG_0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_WORD_COUNT                        0x1
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_SHIFT)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_RANGE                 31:0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x10004)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SECURE                        0x0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_DUAL                  0x0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SCR                   SS_1_REG_0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_1_REG_0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x10008)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SECURE                        0x0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_DUAL                  0x0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SCR                   SS_1_REG_0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_1_REG_0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_2_SHRD_SMP_STA_0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x20000)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SECURE                    0x0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_DUAL                      0x0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SCR                       SS_2_REG_0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_2_REG_0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_WORD_COUNT                        0x1
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_SHIFT)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_RANGE                 31:0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x20004)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SECURE                        0x0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_DUAL                  0x0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SCR                   SS_2_REG_0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_2_REG_0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x20008)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SECURE                        0x0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_DUAL                  0x0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SCR                   SS_2_REG_0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_2_REG_0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_3_SHRD_SMP_STA_0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x30000)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SECURE                    0x0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_DUAL                      0x0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SCR                       SS_3_REG_0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_3_REG_0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_WORD_COUNT                        0x1
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_SHIFT)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_RANGE                 31:0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x30004)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SECURE                        0x0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_DUAL                  0x0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SCR                   SS_3_REG_0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_3_REG_0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x30008)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SECURE                        0x0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_DUAL                  0x0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SCR                   SS_3_REG_0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_3_REG_0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_4_SHRD_SMP_STA_0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x40000)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SECURE                    0x0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_DUAL                      0x0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SCR                       SS_4_REG_0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_4_REG_0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_WORD_COUNT                        0x1
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_SHIFT)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_RANGE                 31:0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x40004)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SECURE                        0x0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_DUAL                  0x0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SCR                   SS_4_REG_0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_4_REG_0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x40008)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SECURE                        0x0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_DUAL                  0x0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SCR                   SS_4_REG_0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_4_REG_0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_5_SHRD_SMP_STA_0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x50000)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SECURE                    0x0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_DUAL                      0x0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SCR                       SS_5_REG_0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_5_REG_0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_WORD_COUNT                        0x1
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_SHIFT)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_RANGE                 31:0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x50004)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SECURE                        0x0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_DUAL                  0x0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SCR                   SS_5_REG_0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_5_REG_0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x50008)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SECURE                        0x0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_DUAL                  0x0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SCR                   SS_5_REG_0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_5_REG_0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_6_SHRD_SMP_STA_0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x60000)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SECURE                    0x0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_DUAL                      0x0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SCR                       SS_6_REG_0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_6_REG_0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_WORD_COUNT                        0x1
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_SHIFT)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_RANGE                 31:0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x60004)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SECURE                        0x0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_DUAL                  0x0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SCR                   SS_6_REG_0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_6_REG_0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x60008)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SECURE                        0x0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_DUAL                  0x0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SCR                   SS_6_REG_0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_6_REG_0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_7_SHRD_SMP_STA_0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x70000)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SECURE                    0x0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_DUAL                      0x0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SCR                       SS_7_REG_0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_7_REG_0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_WORD_COUNT                        0x1
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_SHIFT)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_RANGE                 31:0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x70004)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SECURE                        0x0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_DUAL                  0x0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SCR                   SS_7_REG_0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_7_REG_0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x70008)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SECURE                        0x0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_DUAL                  0x0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SCR                   SS_7_REG_0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_7_REG_0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARHSP_SHRD_SEM_REGS(_op_) \
_op_(HSP_SHRD_SEM_0_SHRD_SMP_STA_0) \
_op_(HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0) \
_op_(HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0) \
_op_(HSP_SHRD_SEM_1_SHRD_SMP_STA_0) \
_op_(HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0) \
_op_(HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0) \
_op_(HSP_SHRD_SEM_2_SHRD_SMP_STA_0) \
_op_(HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0) \
_op_(HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0) \
_op_(HSP_SHRD_SEM_3_SHRD_SMP_STA_0) \
_op_(HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0) \
_op_(HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0) \
_op_(HSP_SHRD_SEM_4_SHRD_SMP_STA_0) \
_op_(HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0) \
_op_(HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0) \
_op_(HSP_SHRD_SEM_5_SHRD_SMP_STA_0) \
_op_(HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0) \
_op_(HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0) \
_op_(HSP_SHRD_SEM_6_SHRD_SMP_STA_0) \
_op_(HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0) \
_op_(HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0) \
_op_(HSP_SHRD_SEM_7_SHRD_SMP_STA_0) \
_op_(HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0) \
_op_(HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_HSP_SHRD   0x00000000

//
// ARHSP_SHRD_SEM REGISTER BANKS
//

#define HSP_SHRD0_FIRST_REG 0x0000 // HSP_SHRD_SEM_0_SHRD_SMP_STA_0
#define HSP_SHRD0_LAST_REG 0x0008 // HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0
#define HSP_SHRD1_FIRST_REG 0x10000 // HSP_SHRD_SEM_1_SHRD_SMP_STA_0
#define HSP_SHRD1_LAST_REG 0x10008 // HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0
#define HSP_SHRD2_FIRST_REG 0x20000 // HSP_SHRD_SEM_2_SHRD_SMP_STA_0
#define HSP_SHRD2_LAST_REG 0x20008 // HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0
#define HSP_SHRD3_FIRST_REG 0x30000 // HSP_SHRD_SEM_3_SHRD_SMP_STA_0
#define HSP_SHRD3_LAST_REG 0x30008 // HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0
#define HSP_SHRD4_FIRST_REG 0x40000 // HSP_SHRD_SEM_4_SHRD_SMP_STA_0
#define HSP_SHRD4_LAST_REG 0x40008 // HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0
#define HSP_SHRD5_FIRST_REG 0x50000 // HSP_SHRD_SEM_5_SHRD_SMP_STA_0
#define HSP_SHRD5_LAST_REG 0x50008 // HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0
#define HSP_SHRD6_FIRST_REG 0x60000 // HSP_SHRD_SEM_6_SHRD_SMP_STA_0
#define HSP_SHRD6_LAST_REG 0x60008 // HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0
#define HSP_SHRD7_FIRST_REG 0x70000 // HSP_SHRD_SEM_7_SHRD_SMP_STA_0
#define HSP_SHRD7_LAST_REG 0x70008 // HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARHSP_SHRD_SEM_H_INC
