//
// Copyright (c) 2021 NVIDIA Corporation.
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are met:
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// this list of conditions and the following disclaimer.
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// this list of conditions and the following disclaimer in the documentation
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// may be used to endorse or promote products derived from this software
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//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARAONCLUSTER_EVP_H_INC
#define ARAONCLUSTER_EVP_H_INC
#define NV_MOBILE_ARAONCLUSTER_EVP_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARAONCLUSTER_EVP_H_SCRREG_NOMENCLATURE INFERRED


// Register AONCLUSTER_EVP_RESET_VEC_0
#define AONCLUSTER_EVP_RESET_VEC_0                      MK_ADDR_CONST(0x0)
#define AONCLUSTER_EVP_RESET_VEC_0_SECURE                       0x0
#define AONCLUSTER_EVP_RESET_VEC_0_DUAL                         0x0
#define AONCLUSTER_EVP_RESET_VEC_0_SCR                  0
#define AONCLUSTER_EVP_RESET_VEC_0_SCRREG                       0
#define AONCLUSTER_EVP_RESET_VEC_0_WORD_COUNT                   0x1
#define AONCLUSTER_EVP_RESET_VEC_0_RESET_VAL                    MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_RESET_VEC_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RESET_VEC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RESET_VEC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RESET_VEC_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RESET_VEC_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_SHIFT                 MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_FIELD                 MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_RESET_VEC_0_VECTOR_SHIFT)
#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_RANGE                 31:0
#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_MSB                   MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_LSB                   MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_WOFFSET                       0x0
#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_DEFAULT                       MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_UNDEF_VEC_0
#define AONCLUSTER_EVP_UNDEF_VEC_0                      MK_ADDR_CONST(0x4)
#define AONCLUSTER_EVP_UNDEF_VEC_0_SECURE                       0x0
#define AONCLUSTER_EVP_UNDEF_VEC_0_DUAL                         0x0
#define AONCLUSTER_EVP_UNDEF_VEC_0_SCR                  0
#define AONCLUSTER_EVP_UNDEF_VEC_0_SCRREG                       0
#define AONCLUSTER_EVP_UNDEF_VEC_0_WORD_COUNT                   0x1
#define AONCLUSTER_EVP_UNDEF_VEC_0_RESET_VAL                    MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_UNDEF_VEC_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_UNDEF_VEC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_UNDEF_VEC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_UNDEF_VEC_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_UNDEF_VEC_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_SHIFT                 MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_FIELD                 MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_SHIFT)
#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_RANGE                 31:0
#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_MSB                   MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_LSB                   MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_WOFFSET                       0x0
#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_DEFAULT                       MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_SWI_VEC_0
#define AONCLUSTER_EVP_SWI_VEC_0                        MK_ADDR_CONST(0x8)
#define AONCLUSTER_EVP_SWI_VEC_0_SECURE                         0x0
#define AONCLUSTER_EVP_SWI_VEC_0_DUAL                   0x0
#define AONCLUSTER_EVP_SWI_VEC_0_SCR                    0
#define AONCLUSTER_EVP_SWI_VEC_0_SCRREG                         0
#define AONCLUSTER_EVP_SWI_VEC_0_WORD_COUNT                     0x1
#define AONCLUSTER_EVP_SWI_VEC_0_RESET_VAL                      MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_SWI_VEC_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_SWI_VEC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_SWI_VEC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_SWI_VEC_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_SWI_VEC_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_SHIFT                   MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_FIELD                   MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_SWI_VEC_0_VECTOR_SHIFT)
#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_RANGE                   31:0
#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_MSB                     MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_LSB                     MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_WOFFSET                 0x0
#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_DEFAULT                 MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0                     MK_ADDR_CONST(0xc)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_SECURE                      0x0
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_DUAL                        0x0
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_SCR                         0
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_SCRREG                      0
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_WORD_COUNT                  0x1
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_RESET_VAL                   MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_SHIFT                        MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_FIELD                        MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_SHIFT)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_RANGE                        31:0
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_MSB                  MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_LSB                  MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_WOFFSET                      0x0
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_DEFAULT                      MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_DATA_ABORT_VEC_0
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0                 MK_ADDR_CONST(0x10)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_SECURE                  0x0
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_DUAL                    0x0
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_SCR                     0
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_SCRREG                  0
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_WORD_COUNT                      0x1
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_RESET_VAL                       MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_SHIFT                    MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_FIELD                    MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_SHIFT)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_RANGE                    31:0
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_MSB                      MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_LSB                      MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_WOFFSET                  0x0
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_DEFAULT                  MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_RSVD_VEC_0
#define AONCLUSTER_EVP_RSVD_VEC_0                       MK_ADDR_CONST(0x14)
#define AONCLUSTER_EVP_RSVD_VEC_0_SECURE                        0x0
#define AONCLUSTER_EVP_RSVD_VEC_0_DUAL                  0x0
#define AONCLUSTER_EVP_RSVD_VEC_0_SCR                   0
#define AONCLUSTER_EVP_RSVD_VEC_0_SCRREG                        0
#define AONCLUSTER_EVP_RSVD_VEC_0_WORD_COUNT                    0x1
#define AONCLUSTER_EVP_RSVD_VEC_0_RESET_VAL                     MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_RSVD_VEC_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RSVD_VEC_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RSVD_VEC_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RSVD_VEC_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RSVD_VEC_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_SHIFT                  MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_FIELD                  MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_SHIFT)
#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_RANGE                  31:0
#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_MSB                    MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_LSB                    MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_WOFFSET                        0x0
#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_DEFAULT                        MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_IRQ_VEC_0
#define AONCLUSTER_EVP_IRQ_VEC_0                        MK_ADDR_CONST(0x18)
#define AONCLUSTER_EVP_IRQ_VEC_0_SECURE                         0x0
#define AONCLUSTER_EVP_IRQ_VEC_0_DUAL                   0x0
#define AONCLUSTER_EVP_IRQ_VEC_0_SCR                    0
#define AONCLUSTER_EVP_IRQ_VEC_0_SCRREG                         0
#define AONCLUSTER_EVP_IRQ_VEC_0_WORD_COUNT                     0x1
#define AONCLUSTER_EVP_IRQ_VEC_0_RESET_VAL                      MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_IRQ_VEC_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_IRQ_VEC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_IRQ_VEC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_IRQ_VEC_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_IRQ_VEC_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_SHIFT                   MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_FIELD                   MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_SHIFT)
#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_RANGE                   31:0
#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_MSB                     MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_LSB                     MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_WOFFSET                 0x0
#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_DEFAULT                 MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_FIQ_VEC_0
#define AONCLUSTER_EVP_FIQ_VEC_0                        MK_ADDR_CONST(0x1c)
#define AONCLUSTER_EVP_FIQ_VEC_0_SECURE                         0x0
#define AONCLUSTER_EVP_FIQ_VEC_0_DUAL                   0x0
#define AONCLUSTER_EVP_FIQ_VEC_0_SCR                    0
#define AONCLUSTER_EVP_FIQ_VEC_0_SCRREG                         0
#define AONCLUSTER_EVP_FIQ_VEC_0_WORD_COUNT                     0x1
#define AONCLUSTER_EVP_FIQ_VEC_0_RESET_VAL                      MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_FIQ_VEC_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_FIQ_VEC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_FIQ_VEC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_FIQ_VEC_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_FIQ_VEC_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_SHIFT                   MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_FIELD                   MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_SHIFT)
#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_RANGE                   31:0
#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_MSB                     MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_LSB                     MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_WOFFSET                 0x0
#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_DEFAULT                 MK_MASK_CONST(0xe59ff018)
#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_RESET_ADDR_0
#define AONCLUSTER_EVP_RESET_ADDR_0                     MK_ADDR_CONST(0x20)
#define AONCLUSTER_EVP_RESET_ADDR_0_SECURE                      0x0
#define AONCLUSTER_EVP_RESET_ADDR_0_DUAL                        0x0
#define AONCLUSTER_EVP_RESET_ADDR_0_SCR                         0
#define AONCLUSTER_EVP_RESET_ADDR_0_SCRREG                      0
#define AONCLUSTER_EVP_RESET_ADDR_0_WORD_COUNT                  0x1
#define AONCLUSTER_EVP_RESET_ADDR_0_RESET_VAL                   MK_MASK_CONST(0xc480000)
#define AONCLUSTER_EVP_RESET_ADDR_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RESET_ADDR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RESET_ADDR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RESET_ADDR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RESET_ADDR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_SHIFT                  MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_FIELD                  MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_RESET_ADDR_0_ADDR_SHIFT)
#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_RANGE                  31:0
#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_MSB                    MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_LSB                    MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_WOFFSET                        0x0
#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_DEFAULT                        MK_MASK_CONST(0xc480000)
#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_UNDEF_ADDR_0
#define AONCLUSTER_EVP_UNDEF_ADDR_0                     MK_ADDR_CONST(0x24)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_SECURE                      0x0
#define AONCLUSTER_EVP_UNDEF_ADDR_0_DUAL                        0x0
#define AONCLUSTER_EVP_UNDEF_ADDR_0_SCR                         0
#define AONCLUSTER_EVP_UNDEF_ADDR_0_SCRREG                      0
#define AONCLUSTER_EVP_UNDEF_ADDR_0_WORD_COUNT                  0x1
#define AONCLUSTER_EVP_UNDEF_ADDR_0_RESET_VAL                   MK_MASK_CONST(0xc480004)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_SHIFT                  MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_FIELD                  MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_SHIFT)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_RANGE                  31:0
#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_MSB                    MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_LSB                    MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_WOFFSET                        0x0
#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_DEFAULT                        MK_MASK_CONST(0xc480004)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_SWI_ADDR_0
#define AONCLUSTER_EVP_SWI_ADDR_0                       MK_ADDR_CONST(0x28)
#define AONCLUSTER_EVP_SWI_ADDR_0_SECURE                        0x0
#define AONCLUSTER_EVP_SWI_ADDR_0_DUAL                  0x0
#define AONCLUSTER_EVP_SWI_ADDR_0_SCR                   0
#define AONCLUSTER_EVP_SWI_ADDR_0_SCRREG                        0
#define AONCLUSTER_EVP_SWI_ADDR_0_WORD_COUNT                    0x1
#define AONCLUSTER_EVP_SWI_ADDR_0_RESET_VAL                     MK_MASK_CONST(0xc480008)
#define AONCLUSTER_EVP_SWI_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_SWI_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_SWI_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_SWI_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_SWI_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_SHIFT                    MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_FIELD                    MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_SWI_ADDR_0_ADDR_SHIFT)
#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_RANGE                    31:0
#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_MSB                      MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_LSB                      MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_WOFFSET                  0x0
#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_DEFAULT                  MK_MASK_CONST(0xc480008)
#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0                    MK_ADDR_CONST(0x2c)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_SECURE                     0x0
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_DUAL                       0x0
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_SCR                        0
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_SCRREG                     0
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_WORD_COUNT                         0x1
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_RESET_VAL                  MK_MASK_CONST(0xc48000c)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_SHIFT                 MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_FIELD                 MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_SHIFT)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_RANGE                 31:0
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_MSB                   MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_LSB                   MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_WOFFSET                       0x0
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_DEFAULT                       MK_MASK_CONST(0xc48000c)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_DATA_ABORT_ADDR_0
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0                        MK_ADDR_CONST(0x30)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_SECURE                         0x0
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_DUAL                   0x0
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_SCR                    0
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_SCRREG                         0
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_WORD_COUNT                     0x1
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_RESET_VAL                      MK_MASK_CONST(0xc480010)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_SHIFT                     MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_FIELD                     MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_SHIFT)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_RANGE                     31:0
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_MSB                       MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_LSB                       MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_WOFFSET                   0x0
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_DEFAULT                   MK_MASK_CONST(0xc480010)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_RSVD_ADDR_0
#define AONCLUSTER_EVP_RSVD_ADDR_0                      MK_ADDR_CONST(0x34)
#define AONCLUSTER_EVP_RSVD_ADDR_0_SECURE                       0x0
#define AONCLUSTER_EVP_RSVD_ADDR_0_DUAL                         0x0
#define AONCLUSTER_EVP_RSVD_ADDR_0_SCR                  0
#define AONCLUSTER_EVP_RSVD_ADDR_0_SCRREG                       0
#define AONCLUSTER_EVP_RSVD_ADDR_0_WORD_COUNT                   0x1
#define AONCLUSTER_EVP_RSVD_ADDR_0_RESET_VAL                    MK_MASK_CONST(0xc480014)
#define AONCLUSTER_EVP_RSVD_ADDR_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RSVD_ADDR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RSVD_ADDR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RSVD_ADDR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RSVD_ADDR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_SHIFT                   MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_FIELD                   MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_SHIFT)
#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_RANGE                   31:0
#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_MSB                     MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_LSB                     MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_WOFFSET                 0x0
#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_DEFAULT                 MK_MASK_CONST(0xc480014)
#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_IRQ_ADDR_0
#define AONCLUSTER_EVP_IRQ_ADDR_0                       MK_ADDR_CONST(0x38)
#define AONCLUSTER_EVP_IRQ_ADDR_0_SECURE                        0x0
#define AONCLUSTER_EVP_IRQ_ADDR_0_DUAL                  0x0
#define AONCLUSTER_EVP_IRQ_ADDR_0_SCR                   0
#define AONCLUSTER_EVP_IRQ_ADDR_0_SCRREG                        0
#define AONCLUSTER_EVP_IRQ_ADDR_0_WORD_COUNT                    0x1
#define AONCLUSTER_EVP_IRQ_ADDR_0_RESET_VAL                     MK_MASK_CONST(0xc480018)
#define AONCLUSTER_EVP_IRQ_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_IRQ_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_IRQ_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_IRQ_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_IRQ_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_SHIFT                    MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_FIELD                    MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_SHIFT)
#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_RANGE                    31:0
#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_MSB                      MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_LSB                      MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_WOFFSET                  0x0
#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_DEFAULT                  MK_MASK_CONST(0xc480018)
#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register AONCLUSTER_EVP_FIQ_ADDR_0
#define AONCLUSTER_EVP_FIQ_ADDR_0                       MK_ADDR_CONST(0x3c)
#define AONCLUSTER_EVP_FIQ_ADDR_0_SECURE                        0x0
#define AONCLUSTER_EVP_FIQ_ADDR_0_DUAL                  0x0
#define AONCLUSTER_EVP_FIQ_ADDR_0_SCR                   0
#define AONCLUSTER_EVP_FIQ_ADDR_0_SCRREG                        0
#define AONCLUSTER_EVP_FIQ_ADDR_0_WORD_COUNT                    0x1
#define AONCLUSTER_EVP_FIQ_ADDR_0_RESET_VAL                     MK_MASK_CONST(0xc48001c)
#define AONCLUSTER_EVP_FIQ_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_FIQ_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_FIQ_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_FIQ_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_FIQ_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_SHIFT                    MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_FIELD                    MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_SHIFT)
#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_RANGE                    31:0
#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_MSB                      MK_SHIFT_CONST(31)
#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_LSB                      MK_SHIFT_CONST(0)
#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_WOFFSET                  0x0
#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_DEFAULT                  MK_MASK_CONST(0xc48001c)
#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARAONCLUSTER_EVP_REGS(_op_) \
_op_(AONCLUSTER_EVP_RESET_VEC_0) \
_op_(AONCLUSTER_EVP_UNDEF_VEC_0) \
_op_(AONCLUSTER_EVP_SWI_VEC_0) \
_op_(AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0) \
_op_(AONCLUSTER_EVP_DATA_ABORT_VEC_0) \
_op_(AONCLUSTER_EVP_RSVD_VEC_0) \
_op_(AONCLUSTER_EVP_IRQ_VEC_0) \
_op_(AONCLUSTER_EVP_FIQ_VEC_0) \
_op_(AONCLUSTER_EVP_RESET_ADDR_0) \
_op_(AONCLUSTER_EVP_UNDEF_ADDR_0) \
_op_(AONCLUSTER_EVP_SWI_ADDR_0) \
_op_(AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0) \
_op_(AONCLUSTER_EVP_DATA_ABORT_ADDR_0) \
_op_(AONCLUSTER_EVP_RSVD_ADDR_0) \
_op_(AONCLUSTER_EVP_IRQ_ADDR_0) \
_op_(AONCLUSTER_EVP_FIQ_ADDR_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_AONCLUSTER_EVP     0x00000000

//
// ARAONCLUSTER_EVP REGISTER BANKS
//

#define AONCLUSTER_EVP0_FIRST_REG 0x0000 // AONCLUSTER_EVP_RESET_VEC_0
#define AONCLUSTER_EVP0_LAST_REG 0x003c // AONCLUSTER_EVP_FIQ_ADDR_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARAONCLUSTER_EVP_H_INC
