//
// Copyright (c) 2021 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARINTR_CTLR_H_INC
#define ARINTR_CTLR_H_INC
#define NV_MOBILE_ARINTR_CTLR_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARINTR_CTLR_H_SCRREG_NOMENCLATURE INFERRED


// Register INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x4)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE0_IER_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0                 MK_ADDR_CONST(0x8)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0                     MK_ADDR_CONST(0xc)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x10)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x14)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0                 MK_ADDR_CONST(0x18)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0                 MK_ADDR_CONST(0x1c)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x20)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x24)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x40)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x44)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE1_IER_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0                 MK_ADDR_CONST(0x48)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x4c)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x50)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x54)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0                 MK_ADDR_CONST(0x58)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0                 MK_ADDR_CONST(0x5c)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x60)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x64)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x80)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x84)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE2_IER_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0                 MK_ADDR_CONST(0x88)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x8c)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x90)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x94)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0                 MK_ADDR_CONST(0x98)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0                 MK_ADDR_CONST(0x9c)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0xa0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0xa4)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0                        MK_ADDR_CONST(0xc0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0                        MK_ADDR_CONST(0xc4)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE3_IER_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0                 MK_ADDR_CONST(0xc8)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0                     MK_ADDR_CONST(0xcc)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0xd0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0xd4)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0                 MK_ADDR_CONST(0xd8)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0                 MK_ADDR_CONST(0xdc)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0xe0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0xe4)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x100)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x104)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE4_IER_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0                 MK_ADDR_CONST(0x108)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x10c)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x110)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x114)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0                 MK_ADDR_CONST(0x118)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0                 MK_ADDR_CONST(0x11c)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x120)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x124)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x140)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x144)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE5_IER_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0                 MK_ADDR_CONST(0x148)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x14c)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x150)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x154)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0                 MK_ADDR_CONST(0x158)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0                 MK_ADDR_CONST(0x15c)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x160)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x164)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x180)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x184)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE6_IER_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0                 MK_ADDR_CONST(0x188)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x18c)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x190)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x194)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0                 MK_ADDR_CONST(0x198)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0                 MK_ADDR_CONST(0x19c)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x1a0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x1a4)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x1c0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x1c4)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE7_IER_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0                 MK_ADDR_CONST(0x1c8)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x1cc)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x1d0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x1d4)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0                 MK_ADDR_CONST(0x1d8)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0                 MK_ADDR_CONST(0x1dc)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x1e0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x1e4)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x200)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x204)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE8_IER_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0                 MK_ADDR_CONST(0x208)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x20c)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x210)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x214)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0                 MK_ADDR_CONST(0x218)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0                 MK_ADDR_CONST(0x21c)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x220)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x224)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x240)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x244)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE9_IER_0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0                 MK_ADDR_CONST(0x248)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x24c)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x250)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x254)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE9_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0                 MK_ADDR_CONST(0x258)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_SCR                     CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE9_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0                 MK_ADDR_CONST(0x25c)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_SCR                     CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x260)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x264)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x280)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x284)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE10_IER_0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0                        MK_ADDR_CONST(0x288)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x28c)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x290)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x294)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE10_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0                        MK_ADDR_CONST(0x298)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE10_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0                        MK_ADDR_CONST(0x29c)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_SCR                    CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x2a0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x2a4)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x2c0)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x2c4)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE11_IER_0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0                        MK_ADDR_CONST(0x2c8)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x2cc)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x2d0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x2d4)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE11_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0                        MK_ADDR_CONST(0x2d8)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE11_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0                        MK_ADDR_CONST(0x2dc)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_SCR                    CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x2e0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x2e4)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x300)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x304)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE12_IER_0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0                        MK_ADDR_CONST(0x308)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x30c)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x310)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x314)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE12_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0                        MK_ADDR_CONST(0x318)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE12_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0                        MK_ADDR_CONST(0x31c)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_SCR                    CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x320)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x324)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x340)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x344)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE13_IER_0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0                        MK_ADDR_CONST(0x348)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x34c)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x350)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x354)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE13_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0                        MK_ADDR_CONST(0x358)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE13_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0                        MK_ADDR_CONST(0x35c)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_SCR                    CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x360)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x364)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x380)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x384)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE14_IER_0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0                        MK_ADDR_CONST(0x388)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x38c)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x390)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x394)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE14_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0                        MK_ADDR_CONST(0x398)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE14_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0                        MK_ADDR_CONST(0x39c)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_SCR                    CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x3a0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x3a4)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x3c0)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x3c4)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE15_IER_0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0                        MK_ADDR_CONST(0x3c8)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x3cc)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x3d0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x3d4)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE15_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0                        MK_ADDR_CONST(0x3d8)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE15_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0                        MK_ADDR_CONST(0x3dc)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_SCR                    CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x3e0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x3e4)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x400)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x404)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_SCR                   CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE16_IER_0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0                        MK_ADDR_CONST(0x408)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x40c)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x410)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x414)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE16_ISR_0
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0                        MK_ADDR_CONST(0x418)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_SCR                    CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE16_IDR_0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0                        MK_ADDR_CONST(0x41c)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_SCR                    CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x420)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x424)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0                  MK_ADDR_CONST(0x7c0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SCRREG                   0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0                  MK_ADDR_CONST(0x7c4)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SCRREG                   0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x800)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x804)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE0_IER_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0                 MK_ADDR_CONST(0x808)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x80c)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x810)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x814)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0                 MK_ADDR_CONST(0x818)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0                 MK_ADDR_CONST(0x81c)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x820)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x824)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x840)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x844)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE1_IER_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0                 MK_ADDR_CONST(0x848)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x84c)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x850)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x854)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0                 MK_ADDR_CONST(0x858)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0                 MK_ADDR_CONST(0x85c)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x860)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x864)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x880)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x884)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE2_IER_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0                 MK_ADDR_CONST(0x888)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x88c)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x890)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x894)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0                 MK_ADDR_CONST(0x898)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0                 MK_ADDR_CONST(0x89c)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x8a0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x8a4)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x8c0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x8c4)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE3_IER_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0                 MK_ADDR_CONST(0x8c8)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x8cc)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x8d0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x8d4)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0                 MK_ADDR_CONST(0x8d8)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0                 MK_ADDR_CONST(0x8dc)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x8e0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x8e4)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x900)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x904)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE4_IER_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0                 MK_ADDR_CONST(0x908)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x90c)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x910)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x914)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0                 MK_ADDR_CONST(0x918)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0                 MK_ADDR_CONST(0x91c)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x920)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x924)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x940)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x944)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE5_IER_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0                 MK_ADDR_CONST(0x948)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x94c)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x950)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x954)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0                 MK_ADDR_CONST(0x958)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0                 MK_ADDR_CONST(0x95c)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x960)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x964)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x980)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x984)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE6_IER_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0                 MK_ADDR_CONST(0x988)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x98c)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x990)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x994)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0                 MK_ADDR_CONST(0x998)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0                 MK_ADDR_CONST(0x99c)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x9a0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x9a4)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x9c0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x9c4)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE7_IER_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0                 MK_ADDR_CONST(0x9c8)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x9cc)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x9d0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x9d4)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0                 MK_ADDR_CONST(0x9d8)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0                 MK_ADDR_CONST(0x9dc)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x9e0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x9e4)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0                        MK_ADDR_CONST(0xa00)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0                        MK_ADDR_CONST(0xa04)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE8_IER_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0                 MK_ADDR_CONST(0xa08)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0                     MK_ADDR_CONST(0xa0c)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0xa10)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0xa14)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0                 MK_ADDR_CONST(0xa18)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0                 MK_ADDR_CONST(0xa1c)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0xa20)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0xa24)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0                        MK_ADDR_CONST(0xa40)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0                        MK_ADDR_CONST(0xa44)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE9_IER_0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0                 MK_ADDR_CONST(0xa48)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0                     MK_ADDR_CONST(0xa4c)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0xa50)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0xa54)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE9_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0                 MK_ADDR_CONST(0xa58)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_SCR                     CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE9_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0                 MK_ADDR_CONST(0xa5c)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_SCR                     CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0xa60)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0xa64)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0                       MK_ADDR_CONST(0xa80)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0                       MK_ADDR_CONST(0xa84)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE10_IER_0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0                        MK_ADDR_CONST(0xa88)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0                    MK_ADDR_CONST(0xa8c)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0xa90)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0xa94)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE10_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0                        MK_ADDR_CONST(0xa98)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE10_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0                        MK_ADDR_CONST(0xa9c)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_SCR                    CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0xaa0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0xaa4)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0                       MK_ADDR_CONST(0xac0)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0                       MK_ADDR_CONST(0xac4)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE11_IER_0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0                        MK_ADDR_CONST(0xac8)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0                    MK_ADDR_CONST(0xacc)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0xad0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0xad4)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE11_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0                        MK_ADDR_CONST(0xad8)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE11_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0                        MK_ADDR_CONST(0xadc)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_SCR                    CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0xae0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0xae4)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0                       MK_ADDR_CONST(0xb00)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0                       MK_ADDR_CONST(0xb04)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE12_IER_0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0                        MK_ADDR_CONST(0xb08)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0                    MK_ADDR_CONST(0xb0c)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0xb10)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0xb14)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE12_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0                        MK_ADDR_CONST(0xb18)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE12_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0                        MK_ADDR_CONST(0xb1c)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_SCR                    CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0xb20)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0xb24)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0                       MK_ADDR_CONST(0xb40)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0                       MK_ADDR_CONST(0xb44)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE13_IER_0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0                        MK_ADDR_CONST(0xb48)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0                    MK_ADDR_CONST(0xb4c)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0xb50)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0xb54)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE13_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0                        MK_ADDR_CONST(0xb58)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE13_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0                        MK_ADDR_CONST(0xb5c)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_SCR                    CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0xb60)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0xb64)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0                       MK_ADDR_CONST(0xb80)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0                       MK_ADDR_CONST(0xb84)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE14_IER_0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0                        MK_ADDR_CONST(0xb88)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0                    MK_ADDR_CONST(0xb8c)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0xb90)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0xb94)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE14_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0                        MK_ADDR_CONST(0xb98)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE14_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0                        MK_ADDR_CONST(0xb9c)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_SCR                    CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0xba0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0xba4)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0                       MK_ADDR_CONST(0xbc0)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0                       MK_ADDR_CONST(0xbc4)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE15_IER_0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0                        MK_ADDR_CONST(0xbc8)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0                    MK_ADDR_CONST(0xbcc)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0xbd0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0xbd4)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE15_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0                        MK_ADDR_CONST(0xbd8)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE15_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0                        MK_ADDR_CONST(0xbdc)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_SCR                    CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0xbe0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0xbe4)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0                       MK_ADDR_CONST(0xc00)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0                       MK_ADDR_CONST(0xc04)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_SCR                   CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE16_IER_0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0                        MK_ADDR_CONST(0xc08)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0                    MK_ADDR_CONST(0xc0c)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0xc10)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0xc14)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE16_ISR_0
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0                        MK_ADDR_CONST(0xc18)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_SCR                    CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE16_IDR_0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0                        MK_ADDR_CONST(0xc1c)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_SCR                    CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0xc20)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0xc24)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0                  MK_ADDR_CONST(0xfc0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SCRREG                   0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0                  MK_ADDR_CONST(0xfc4)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SCRREG                   0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x1000)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x1004)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE0_IER_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0                 MK_ADDR_CONST(0x1008)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x100c)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x1010)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x1014)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0                 MK_ADDR_CONST(0x1018)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0                 MK_ADDR_CONST(0x101c)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x1020)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x1024)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x1040)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x1044)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE1_IER_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0                 MK_ADDR_CONST(0x1048)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x104c)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x1050)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x1054)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0                 MK_ADDR_CONST(0x1058)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0                 MK_ADDR_CONST(0x105c)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x1060)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x1064)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x1080)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x1084)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE2_IER_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0                 MK_ADDR_CONST(0x1088)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x108c)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x1090)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x1094)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0                 MK_ADDR_CONST(0x1098)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0                 MK_ADDR_CONST(0x109c)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x10a0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x10a4)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x10c0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x10c4)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE3_IER_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0                 MK_ADDR_CONST(0x10c8)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x10cc)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x10d0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x10d4)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0                 MK_ADDR_CONST(0x10d8)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0                 MK_ADDR_CONST(0x10dc)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x10e0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x10e4)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x1100)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x1104)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE4_IER_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0                 MK_ADDR_CONST(0x1108)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x110c)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x1110)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x1114)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0                 MK_ADDR_CONST(0x1118)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0                 MK_ADDR_CONST(0x111c)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x1120)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x1124)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x1140)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x1144)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE5_IER_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0                 MK_ADDR_CONST(0x1148)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x114c)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x1150)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x1154)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0                 MK_ADDR_CONST(0x1158)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0                 MK_ADDR_CONST(0x115c)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x1160)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x1164)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x1180)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x1184)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE6_IER_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0                 MK_ADDR_CONST(0x1188)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x118c)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x1190)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x1194)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0                 MK_ADDR_CONST(0x1198)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0                 MK_ADDR_CONST(0x119c)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x11a0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x11a4)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x11c0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x11c4)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE7_IER_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0                 MK_ADDR_CONST(0x11c8)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x11cc)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x11d0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x11d4)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0                 MK_ADDR_CONST(0x11d8)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0                 MK_ADDR_CONST(0x11dc)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x11e0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x11e4)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x1200)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x1204)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE8_IER_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0                 MK_ADDR_CONST(0x1208)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x120c)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x1210)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x1214)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0                 MK_ADDR_CONST(0x1218)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0                 MK_ADDR_CONST(0x121c)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x1220)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x1224)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x1240)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x1244)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE9_IER_0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0                 MK_ADDR_CONST(0x1248)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x124c)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x1250)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x1254)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE9_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0                 MK_ADDR_CONST(0x1258)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_SCR                     CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE9_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0                 MK_ADDR_CONST(0x125c)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_SCR                     CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x1260)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x1264)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x1280)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x1284)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE10_IER_0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0                        MK_ADDR_CONST(0x1288)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x128c)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x1290)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x1294)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE10_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0                        MK_ADDR_CONST(0x1298)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE10_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0                        MK_ADDR_CONST(0x129c)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_SCR                    CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x12a0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x12a4)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x12c0)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x12c4)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE11_IER_0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0                        MK_ADDR_CONST(0x12c8)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x12cc)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x12d0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x12d4)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE11_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0                        MK_ADDR_CONST(0x12d8)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE11_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0                        MK_ADDR_CONST(0x12dc)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_SCR                    CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x12e0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x12e4)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x1300)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x1304)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE12_IER_0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0                        MK_ADDR_CONST(0x1308)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x130c)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x1310)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x1314)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE12_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0                        MK_ADDR_CONST(0x1318)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE12_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0                        MK_ADDR_CONST(0x131c)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_SCR                    CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x1320)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x1324)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x1340)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x1344)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE13_IER_0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0                        MK_ADDR_CONST(0x1348)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x134c)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x1350)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x1354)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE13_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0                        MK_ADDR_CONST(0x1358)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE13_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0                        MK_ADDR_CONST(0x135c)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_SCR                    CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x1360)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x1364)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x1380)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x1384)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE14_IER_0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0                        MK_ADDR_CONST(0x1388)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x138c)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x1390)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x1394)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE14_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0                        MK_ADDR_CONST(0x1398)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE14_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0                        MK_ADDR_CONST(0x139c)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_SCR                    CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x13a0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x13a4)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x13c0)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x13c4)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE15_IER_0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0                        MK_ADDR_CONST(0x13c8)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x13cc)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x13d0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x13d4)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE15_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0                        MK_ADDR_CONST(0x13d8)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE15_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0                        MK_ADDR_CONST(0x13dc)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_SCR                    CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x13e0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x13e4)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x1400)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x1404)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_SCR                   CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE16_IER_0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0                        MK_ADDR_CONST(0x1408)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x140c)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x1410)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x1414)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE16_ISR_0
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0                        MK_ADDR_CONST(0x1418)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_SCR                    CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE16_IDR_0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0                        MK_ADDR_CONST(0x141c)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_SCR                    CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x1420)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x1424)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0                  MK_ADDR_CONST(0x17c0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SCRREG                   0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0                  MK_ADDR_CONST(0x17c4)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SCRREG                   0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x1800)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x1804)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE0_IER_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0                 MK_ADDR_CONST(0x1808)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x180c)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x1810)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x1814)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0                 MK_ADDR_CONST(0x1818)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0                 MK_ADDR_CONST(0x181c)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x1820)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x1824)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x1840)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x1844)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE1_IER_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0                 MK_ADDR_CONST(0x1848)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x184c)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x1850)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x1854)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0                 MK_ADDR_CONST(0x1858)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0                 MK_ADDR_CONST(0x185c)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x1860)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x1864)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x1880)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x1884)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE2_IER_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0                 MK_ADDR_CONST(0x1888)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x188c)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x1890)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x1894)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0                 MK_ADDR_CONST(0x1898)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0                 MK_ADDR_CONST(0x189c)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x18a0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x18a4)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x18c0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x18c4)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE3_IER_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0                 MK_ADDR_CONST(0x18c8)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x18cc)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x18d0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x18d4)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0                 MK_ADDR_CONST(0x18d8)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0                 MK_ADDR_CONST(0x18dc)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x18e0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x18e4)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x1900)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x1904)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE4_IER_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0                 MK_ADDR_CONST(0x1908)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x190c)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x1910)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x1914)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0                 MK_ADDR_CONST(0x1918)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0                 MK_ADDR_CONST(0x191c)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x1920)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x1924)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x1940)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x1944)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE5_IER_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0                 MK_ADDR_CONST(0x1948)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x194c)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x1950)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x1954)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0                 MK_ADDR_CONST(0x1958)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0                 MK_ADDR_CONST(0x195c)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x1960)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x1964)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x1980)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x1984)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE6_IER_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0                 MK_ADDR_CONST(0x1988)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x198c)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x1990)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x1994)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0                 MK_ADDR_CONST(0x1998)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0                 MK_ADDR_CONST(0x199c)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x19a0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x19a4)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x19c0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x19c4)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE7_IER_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0                 MK_ADDR_CONST(0x19c8)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x19cc)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x19d0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x19d4)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0                 MK_ADDR_CONST(0x19d8)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0                 MK_ADDR_CONST(0x19dc)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x19e0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x19e4)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x1a00)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x1a04)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE8_IER_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0                 MK_ADDR_CONST(0x1a08)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x1a0c)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x1a10)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x1a14)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0                 MK_ADDR_CONST(0x1a18)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0                 MK_ADDR_CONST(0x1a1c)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x1a20)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x1a24)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x1a40)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x1a44)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE9_IER_0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0                 MK_ADDR_CONST(0x1a48)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x1a4c)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x1a50)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x1a54)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE9_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0                 MK_ADDR_CONST(0x1a58)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_SCR                     CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE9_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0                 MK_ADDR_CONST(0x1a5c)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_SCR                     CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x1a60)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x1a64)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x1a80)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x1a84)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE10_IER_0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0                        MK_ADDR_CONST(0x1a88)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x1a8c)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x1a90)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x1a94)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE10_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0                        MK_ADDR_CONST(0x1a98)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE10_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0                        MK_ADDR_CONST(0x1a9c)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_SCR                    CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x1aa0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x1aa4)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x1ac0)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x1ac4)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE11_IER_0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0                        MK_ADDR_CONST(0x1ac8)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x1acc)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x1ad0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x1ad4)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE11_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0                        MK_ADDR_CONST(0x1ad8)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE11_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0                        MK_ADDR_CONST(0x1adc)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_SCR                    CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x1ae0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x1ae4)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x1b00)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x1b04)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE12_IER_0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0                        MK_ADDR_CONST(0x1b08)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x1b0c)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x1b10)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x1b14)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE12_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0                        MK_ADDR_CONST(0x1b18)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE12_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0                        MK_ADDR_CONST(0x1b1c)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_SCR                    CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x1b20)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x1b24)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x1b40)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x1b44)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE13_IER_0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0                        MK_ADDR_CONST(0x1b48)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x1b4c)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x1b50)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x1b54)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE13_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0                        MK_ADDR_CONST(0x1b58)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE13_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0                        MK_ADDR_CONST(0x1b5c)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_SCR                    CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x1b60)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x1b64)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x1b80)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x1b84)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE14_IER_0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0                        MK_ADDR_CONST(0x1b88)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x1b8c)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x1b90)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x1b94)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE14_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0                        MK_ADDR_CONST(0x1b98)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE14_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0                        MK_ADDR_CONST(0x1b9c)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_SCR                    CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x1ba0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x1ba4)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x1bc0)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x1bc4)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE15_IER_0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0                        MK_ADDR_CONST(0x1bc8)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x1bcc)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x1bd0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x1bd4)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE15_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0                        MK_ADDR_CONST(0x1bd8)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE15_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0                        MK_ADDR_CONST(0x1bdc)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_SCR                    CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x1be0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x1be4)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x1c00)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x1c04)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_SCR                   CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE16_IER_0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0                        MK_ADDR_CONST(0x1c08)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x1c0c)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x1c10)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x1c14)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE16_ISR_0
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0                        MK_ADDR_CONST(0x1c18)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_SCR                    CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE16_IDR_0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0                        MK_ADDR_CONST(0x1c1c)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_SCR                    CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x1c20)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x1c24)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0                  MK_ADDR_CONST(0x1fc0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SCRREG                   0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0                  MK_ADDR_CONST(0x1fc4)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SCRREG                   0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x2000)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x2004)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE0_IER_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0                 MK_ADDR_CONST(0x2008)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x200c)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x2010)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x2014)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0                 MK_ADDR_CONST(0x2018)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0                 MK_ADDR_CONST(0x201c)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x2020)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x2024)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x2040)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x2044)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE1_IER_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0                 MK_ADDR_CONST(0x2048)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x204c)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x2050)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x2054)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0                 MK_ADDR_CONST(0x2058)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0                 MK_ADDR_CONST(0x205c)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x2060)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x2064)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x2080)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x2084)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE2_IER_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0                 MK_ADDR_CONST(0x2088)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x208c)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x2090)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x2094)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0                 MK_ADDR_CONST(0x2098)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0                 MK_ADDR_CONST(0x209c)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x20a0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x20a4)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x20c0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x20c4)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE3_IER_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0                 MK_ADDR_CONST(0x20c8)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x20cc)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x20d0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x20d4)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0                 MK_ADDR_CONST(0x20d8)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0                 MK_ADDR_CONST(0x20dc)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x20e0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x20e4)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x2100)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x2104)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE4_IER_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0                 MK_ADDR_CONST(0x2108)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x210c)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x2110)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x2114)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0                 MK_ADDR_CONST(0x2118)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0                 MK_ADDR_CONST(0x211c)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x2120)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x2124)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x2140)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x2144)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE5_IER_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0                 MK_ADDR_CONST(0x2148)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x214c)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x2150)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x2154)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0                 MK_ADDR_CONST(0x2158)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0                 MK_ADDR_CONST(0x215c)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x2160)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x2164)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x2180)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x2184)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE6_IER_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0                 MK_ADDR_CONST(0x2188)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x218c)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x2190)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x2194)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0                 MK_ADDR_CONST(0x2198)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0                 MK_ADDR_CONST(0x219c)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x21a0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x21a4)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x21c0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x21c4)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE7_IER_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0                 MK_ADDR_CONST(0x21c8)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x21cc)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x21d0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x21d4)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0                 MK_ADDR_CONST(0x21d8)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0                 MK_ADDR_CONST(0x21dc)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x21e0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x21e4)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x2200)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x2204)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE8_IER_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0                 MK_ADDR_CONST(0x2208)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x220c)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x2210)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x2214)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0                 MK_ADDR_CONST(0x2218)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0                 MK_ADDR_CONST(0x221c)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x2220)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x2224)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x2240)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x2244)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE9_IER_0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0                 MK_ADDR_CONST(0x2248)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x224c)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x2250)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x2254)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE9_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0                 MK_ADDR_CONST(0x2258)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_SCR                     CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE9_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0                 MK_ADDR_CONST(0x225c)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_SCR                     CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x2260)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x2264)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x2280)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x2284)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE10_IER_0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0                        MK_ADDR_CONST(0x2288)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x228c)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x2290)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x2294)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE10_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0                        MK_ADDR_CONST(0x2298)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE10_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0                        MK_ADDR_CONST(0x229c)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_SCR                    CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x22a0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x22a4)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x22c0)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x22c4)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE11_IER_0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0                        MK_ADDR_CONST(0x22c8)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x22cc)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x22d0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x22d4)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE11_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0                        MK_ADDR_CONST(0x22d8)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE11_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0                        MK_ADDR_CONST(0x22dc)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_SCR                    CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x22e0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x22e4)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x2300)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x2304)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE12_IER_0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0                        MK_ADDR_CONST(0x2308)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x230c)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x2310)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x2314)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE12_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0                        MK_ADDR_CONST(0x2318)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE12_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0                        MK_ADDR_CONST(0x231c)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_SCR                    CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x2320)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x2324)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x2340)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x2344)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE13_IER_0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0                        MK_ADDR_CONST(0x2348)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x234c)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x2350)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x2354)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE13_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0                        MK_ADDR_CONST(0x2358)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE13_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0                        MK_ADDR_CONST(0x235c)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_SCR                    CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x2360)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x2364)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x2380)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x2384)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE14_IER_0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0                        MK_ADDR_CONST(0x2388)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x238c)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x2390)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x2394)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE14_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0                        MK_ADDR_CONST(0x2398)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE14_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0                        MK_ADDR_CONST(0x239c)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_SCR                    CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x23a0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x23a4)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x23c0)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x23c4)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE15_IER_0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0                        MK_ADDR_CONST(0x23c8)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x23cc)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x23d0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x23d4)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE15_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0                        MK_ADDR_CONST(0x23d8)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE15_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0                        MK_ADDR_CONST(0x23dc)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_SCR                    CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x23e0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x23e4)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x2400)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x2404)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_SCR                   CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE16_IER_0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0                        MK_ADDR_CONST(0x2408)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x240c)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x2410)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x2414)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE16_ISR_0
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0                        MK_ADDR_CONST(0x2418)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_SCR                    CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE16_IDR_0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0                        MK_ADDR_CONST(0x241c)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_SCR                    CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x2420)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x2424)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0                  MK_ADDR_CONST(0x27c0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SCRREG                   0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0                  MK_ADDR_CONST(0x27c4)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SCRREG                   0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x2800)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x2804)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE0_IER_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0                 MK_ADDR_CONST(0x2808)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x280c)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x2810)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x2814)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0                 MK_ADDR_CONST(0x2818)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0                 MK_ADDR_CONST(0x281c)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x2820)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x2824)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x2840)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x2844)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE1_IER_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0                 MK_ADDR_CONST(0x2848)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x284c)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x2850)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x2854)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0                 MK_ADDR_CONST(0x2858)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0                 MK_ADDR_CONST(0x285c)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x2860)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x2864)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x2880)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x2884)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE2_IER_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0                 MK_ADDR_CONST(0x2888)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x288c)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x2890)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x2894)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0                 MK_ADDR_CONST(0x2898)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0                 MK_ADDR_CONST(0x289c)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x28a0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x28a4)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x28c0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x28c4)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE3_IER_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0                 MK_ADDR_CONST(0x28c8)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x28cc)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x28d0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x28d4)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0                 MK_ADDR_CONST(0x28d8)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0                 MK_ADDR_CONST(0x28dc)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x28e0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x28e4)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x2900)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x2904)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE4_IER_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0                 MK_ADDR_CONST(0x2908)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x290c)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x2910)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x2914)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0                 MK_ADDR_CONST(0x2918)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0                 MK_ADDR_CONST(0x291c)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x2920)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x2924)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x2940)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x2944)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE5_IER_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0                 MK_ADDR_CONST(0x2948)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x294c)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x2950)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x2954)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0                 MK_ADDR_CONST(0x2958)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0                 MK_ADDR_CONST(0x295c)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x2960)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x2964)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x2980)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x2984)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE6_IER_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0                 MK_ADDR_CONST(0x2988)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x298c)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x2990)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x2994)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0                 MK_ADDR_CONST(0x2998)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0                 MK_ADDR_CONST(0x299c)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x29a0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x29a4)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x29c0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x29c4)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE7_IER_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0                 MK_ADDR_CONST(0x29c8)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x29cc)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x29d0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x29d4)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0                 MK_ADDR_CONST(0x29d8)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0                 MK_ADDR_CONST(0x29dc)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x29e0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x29e4)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x2a00)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x2a04)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE8_IER_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0                 MK_ADDR_CONST(0x2a08)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x2a0c)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x2a10)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x2a14)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0                 MK_ADDR_CONST(0x2a18)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0                 MK_ADDR_CONST(0x2a1c)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x2a20)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x2a24)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x2a40)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x2a44)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE9_IER_0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0                 MK_ADDR_CONST(0x2a48)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x2a4c)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x2a50)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x2a54)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE9_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0                 MK_ADDR_CONST(0x2a58)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_SCR                     CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE9_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0                 MK_ADDR_CONST(0x2a5c)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_SCR                     CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x2a60)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x2a64)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x2a80)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x2a84)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE10_IER_0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0                        MK_ADDR_CONST(0x2a88)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x2a8c)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x2a90)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x2a94)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE10_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0                        MK_ADDR_CONST(0x2a98)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE10_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0                        MK_ADDR_CONST(0x2a9c)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_SCR                    CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x2aa0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x2aa4)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x2ac0)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x2ac4)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE11_IER_0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0                        MK_ADDR_CONST(0x2ac8)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x2acc)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x2ad0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x2ad4)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE11_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0                        MK_ADDR_CONST(0x2ad8)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE11_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0                        MK_ADDR_CONST(0x2adc)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_SCR                    CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x2ae0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x2ae4)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x2b00)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x2b04)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE12_IER_0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0                        MK_ADDR_CONST(0x2b08)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x2b0c)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x2b10)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x2b14)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE12_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0                        MK_ADDR_CONST(0x2b18)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE12_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0                        MK_ADDR_CONST(0x2b1c)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_SCR                    CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x2b20)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x2b24)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x2b40)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x2b44)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE13_IER_0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0                        MK_ADDR_CONST(0x2b48)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x2b4c)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x2b50)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x2b54)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE13_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0                        MK_ADDR_CONST(0x2b58)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE13_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0                        MK_ADDR_CONST(0x2b5c)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_SCR                    CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x2b60)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x2b64)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x2b80)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x2b84)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE14_IER_0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0                        MK_ADDR_CONST(0x2b88)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x2b8c)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x2b90)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x2b94)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE14_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0                        MK_ADDR_CONST(0x2b98)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE14_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0                        MK_ADDR_CONST(0x2b9c)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_SCR                    CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x2ba0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x2ba4)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x2bc0)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x2bc4)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE15_IER_0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0                        MK_ADDR_CONST(0x2bc8)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x2bcc)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x2bd0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x2bd4)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE15_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0                        MK_ADDR_CONST(0x2bd8)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE15_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0                        MK_ADDR_CONST(0x2bdc)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_SCR                    CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x2be0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x2be4)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x2c00)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x2c04)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_SCR                   CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE16_IER_0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0                        MK_ADDR_CONST(0x2c08)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x2c0c)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x2c10)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x2c14)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE16_ISR_0
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0                        MK_ADDR_CONST(0x2c18)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_SCR                    CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE16_IDR_0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0                        MK_ADDR_CONST(0x2c1c)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_SCR                    CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x2c20)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x2c24)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0                  MK_ADDR_CONST(0x2fc0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SCRREG                   0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0                  MK_ADDR_CONST(0x2fc4)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SCRREG                   0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x3000)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x3004)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE0_IER_0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0                 MK_ADDR_CONST(0x3008)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x300c)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x3010)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x3014)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0                 MK_ADDR_CONST(0x3018)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0                 MK_ADDR_CONST(0x301c)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_SCR                     CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x3020)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x3024)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x3040)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x3044)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE1_IER_0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0                 MK_ADDR_CONST(0x3048)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x304c)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x3050)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x3054)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0                 MK_ADDR_CONST(0x3058)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0                 MK_ADDR_CONST(0x305c)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_SCR                     CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x3060)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x3064)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x3080)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x3084)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE2_IER_0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0                 MK_ADDR_CONST(0x3088)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x308c)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x3090)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x3094)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0                 MK_ADDR_CONST(0x3098)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0                 MK_ADDR_CONST(0x309c)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_SCR                     CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x30a0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x30a4)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x30c0)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x30c4)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE3_IER_0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0                 MK_ADDR_CONST(0x30c8)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x30cc)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x30d0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x30d4)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0                 MK_ADDR_CONST(0x30d8)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0                 MK_ADDR_CONST(0x30dc)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_SCR                     CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x30e0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x30e4)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x3100)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x3104)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE4_IER_0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0                 MK_ADDR_CONST(0x3108)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x310c)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x3110)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x3114)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0                 MK_ADDR_CONST(0x3118)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0                 MK_ADDR_CONST(0x311c)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_SCR                     CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x3120)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x3124)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x3140)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x3144)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE5_IER_0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0                 MK_ADDR_CONST(0x3148)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x314c)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x3150)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x3154)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0                 MK_ADDR_CONST(0x3158)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0                 MK_ADDR_CONST(0x315c)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_SCR                     CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x3160)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x3164)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x3180)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x3184)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE6_IER_0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0                 MK_ADDR_CONST(0x3188)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x318c)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x3190)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x3194)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0                 MK_ADDR_CONST(0x3198)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0                 MK_ADDR_CONST(0x319c)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_SCR                     CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x31a0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x31a4)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x31c0)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x31c4)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE7_IER_0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0                 MK_ADDR_CONST(0x31c8)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x31cc)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x31d0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x31d4)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0                 MK_ADDR_CONST(0x31d8)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0                 MK_ADDR_CONST(0x31dc)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_SCR                     CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x31e0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x31e4)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x3200)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x3204)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE8_IER_0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0                 MK_ADDR_CONST(0x3208)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x320c)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x3210)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x3214)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0                 MK_ADDR_CONST(0x3218)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0                 MK_ADDR_CONST(0x321c)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_SCR                     CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x3220)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x3224)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x3240)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x3244)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE9_IER_0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0                 MK_ADDR_CONST(0x3248)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x324c)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x3250)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x3254)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE9_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0                 MK_ADDR_CONST(0x3258)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_SCR                     CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE9_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0                 MK_ADDR_CONST(0x325c)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_SCR                     CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x3260)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x3264)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x3280)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x3284)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE10_IER_0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0                        MK_ADDR_CONST(0x3288)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x328c)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x3290)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x3294)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE10_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0                        MK_ADDR_CONST(0x3298)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE10_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0                        MK_ADDR_CONST(0x329c)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_SCR                    CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x32a0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x32a4)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x32c0)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x32c4)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE11_IER_0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0                        MK_ADDR_CONST(0x32c8)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x32cc)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x32d0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x32d4)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE11_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0                        MK_ADDR_CONST(0x32d8)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE11_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0                        MK_ADDR_CONST(0x32dc)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_SCR                    CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x32e0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x32e4)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x3300)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x3304)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE12_IER_0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0                        MK_ADDR_CONST(0x3308)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x330c)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x3310)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x3314)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE12_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0                        MK_ADDR_CONST(0x3318)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE12_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0                        MK_ADDR_CONST(0x331c)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_SCR                    CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x3320)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x3324)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x3340)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x3344)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE13_IER_0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0                        MK_ADDR_CONST(0x3348)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x334c)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x3350)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x3354)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE13_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0                        MK_ADDR_CONST(0x3358)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE13_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0                        MK_ADDR_CONST(0x335c)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_SCR                    CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x3360)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x3364)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x3380)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x3384)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE14_IER_0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0                        MK_ADDR_CONST(0x3388)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x338c)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x3390)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x3394)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE14_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0                        MK_ADDR_CONST(0x3398)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE14_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0                        MK_ADDR_CONST(0x339c)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_SCR                    CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x33a0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x33a4)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x33c0)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x33c4)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE15_IER_0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0                        MK_ADDR_CONST(0x33c8)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x33cc)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x33d0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x33d4)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE15_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0                        MK_ADDR_CONST(0x33d8)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE15_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0                        MK_ADDR_CONST(0x33dc)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_SCR                    CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x33e0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x33e4)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x3400)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x3404)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_SCR                   CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE16_IER_0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0                        MK_ADDR_CONST(0x3408)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x340c)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x3410)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x3414)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE16_ISR_0
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0                        MK_ADDR_CONST(0x3418)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_SCR                    CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE16_IDR_0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0                        MK_ADDR_CONST(0x341c)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_SCR                    CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x3420)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x3424)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0                  MK_ADDR_CONST(0x37c0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SCRREG                   0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0                  MK_ADDR_CONST(0x37c4)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SCRREG                   0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x3800)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x3804)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE0_IER_0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0                 MK_ADDR_CONST(0x3808)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x380c)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x3810)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x3814)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0                 MK_ADDR_CONST(0x3818)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0                 MK_ADDR_CONST(0x381c)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_SCR                     CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x3820)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x3824)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x3840)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x3844)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE1_IER_0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0                 MK_ADDR_CONST(0x3848)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x384c)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x3850)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x3854)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0                 MK_ADDR_CONST(0x3858)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0                 MK_ADDR_CONST(0x385c)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_SCR                     CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x3860)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x3864)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x3880)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x3884)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE2_IER_0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0                 MK_ADDR_CONST(0x3888)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x388c)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x3890)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x3894)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0                 MK_ADDR_CONST(0x3898)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0                 MK_ADDR_CONST(0x389c)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_SCR                     CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x38a0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x38a4)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x38c0)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x38c4)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE3_IER_0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0                 MK_ADDR_CONST(0x38c8)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x38cc)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x38d0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x38d4)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0                 MK_ADDR_CONST(0x38d8)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0                 MK_ADDR_CONST(0x38dc)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_SCR                     CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x38e0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x38e4)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x3900)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x3904)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE4_IER_0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0                 MK_ADDR_CONST(0x3908)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x390c)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x3910)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x3914)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0                 MK_ADDR_CONST(0x3918)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0                 MK_ADDR_CONST(0x391c)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_SCR                     CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x3920)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x3924)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x3940)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x3944)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE5_IER_0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0                 MK_ADDR_CONST(0x3948)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x394c)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x3950)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x3954)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0                 MK_ADDR_CONST(0x3958)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0                 MK_ADDR_CONST(0x395c)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_SCR                     CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x3960)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x3964)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x3980)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x3984)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE6_IER_0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0                 MK_ADDR_CONST(0x3988)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x398c)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x3990)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x3994)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0                 MK_ADDR_CONST(0x3998)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0                 MK_ADDR_CONST(0x399c)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_SCR                     CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x39a0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x39a4)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x39c0)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x39c4)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE7_IER_0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0                 MK_ADDR_CONST(0x39c8)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x39cc)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x39d0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x39d4)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0                 MK_ADDR_CONST(0x39d8)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0                 MK_ADDR_CONST(0x39dc)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_SCR                     CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x39e0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x39e4)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x3a00)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x3a04)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE8_IER_0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0                 MK_ADDR_CONST(0x3a08)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x3a0c)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x3a10)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x3a14)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0                 MK_ADDR_CONST(0x3a18)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0                 MK_ADDR_CONST(0x3a1c)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_SCR                     CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x3a20)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x3a24)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x3a40)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x3a44)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE9_IER_0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0                 MK_ADDR_CONST(0x3a48)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x3a4c)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x3a50)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x3a54)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE9_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0                 MK_ADDR_CONST(0x3a58)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_SCR                     CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE9_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0                 MK_ADDR_CONST(0x3a5c)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_SCR                     CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x3a60)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x3a64)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x3a80)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x3a84)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE10_IER_0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0                        MK_ADDR_CONST(0x3a88)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x3a8c)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x3a90)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x3a94)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE10_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0                        MK_ADDR_CONST(0x3a98)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE10_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0                        MK_ADDR_CONST(0x3a9c)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_SCR                    CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x3aa0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x3aa4)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x3ac0)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x3ac4)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE11_IER_0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0                        MK_ADDR_CONST(0x3ac8)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x3acc)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x3ad0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x3ad4)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE11_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0                        MK_ADDR_CONST(0x3ad8)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE11_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0                        MK_ADDR_CONST(0x3adc)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_SCR                    CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x3ae0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x3ae4)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x3b00)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x3b04)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE12_IER_0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0                        MK_ADDR_CONST(0x3b08)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x3b0c)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x3b10)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x3b14)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE12_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0                        MK_ADDR_CONST(0x3b18)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE12_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0                        MK_ADDR_CONST(0x3b1c)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_SCR                    CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x3b20)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x3b24)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x3b40)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x3b44)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE13_IER_0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0                        MK_ADDR_CONST(0x3b48)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x3b4c)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x3b50)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x3b54)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE13_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0                        MK_ADDR_CONST(0x3b58)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE13_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0                        MK_ADDR_CONST(0x3b5c)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_SCR                    CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x3b60)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x3b64)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x3b80)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x3b84)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE14_IER_0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0                        MK_ADDR_CONST(0x3b88)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x3b8c)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x3b90)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x3b94)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE14_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0                        MK_ADDR_CONST(0x3b98)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE14_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0                        MK_ADDR_CONST(0x3b9c)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_SCR                    CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x3ba0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x3ba4)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x3bc0)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x3bc4)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE15_IER_0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0                        MK_ADDR_CONST(0x3bc8)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x3bcc)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x3bd0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x3bd4)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE15_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0                        MK_ADDR_CONST(0x3bd8)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE15_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0                        MK_ADDR_CONST(0x3bdc)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_SCR                    CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x3be0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x3be4)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x3c00)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x3c04)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_SCR                   CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE16_IER_0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0                        MK_ADDR_CONST(0x3c08)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x3c0c)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x3c10)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x3c14)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE16_ISR_0
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0                        MK_ADDR_CONST(0x3c18)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_SCR                    CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE16_IDR_0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0                        MK_ADDR_CONST(0x3c1c)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_SCR                    CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x3c20)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x3c24)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0                  MK_ADDR_CONST(0x3fc0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SCRREG                   0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0                  MK_ADDR_CONST(0x3fc4)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SCRREG                   0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x4000)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x4004)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE0_IER_0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0                 MK_ADDR_CONST(0x4008)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x400c)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x4010)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x4014)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0                 MK_ADDR_CONST(0x4018)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0                 MK_ADDR_CONST(0x401c)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_SCR                     CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x4020)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x4024)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x4040)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x4044)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE1_IER_0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0                 MK_ADDR_CONST(0x4048)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x404c)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x4050)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x4054)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0                 MK_ADDR_CONST(0x4058)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0                 MK_ADDR_CONST(0x405c)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_SCR                     CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x4060)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x4064)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x4080)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x4084)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE2_IER_0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0                 MK_ADDR_CONST(0x4088)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x408c)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x4090)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x4094)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0                 MK_ADDR_CONST(0x4098)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0                 MK_ADDR_CONST(0x409c)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_SCR                     CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x40a0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x40a4)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x40c0)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x40c4)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE3_IER_0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0                 MK_ADDR_CONST(0x40c8)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x40cc)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x40d0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x40d4)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0                 MK_ADDR_CONST(0x40d8)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0                 MK_ADDR_CONST(0x40dc)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_SCR                     CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x40e0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x40e4)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x4100)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x4104)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE4_IER_0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0                 MK_ADDR_CONST(0x4108)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x410c)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x4110)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x4114)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0                 MK_ADDR_CONST(0x4118)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0                 MK_ADDR_CONST(0x411c)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_SCR                     CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x4120)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x4124)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x4140)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x4144)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE5_IER_0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0                 MK_ADDR_CONST(0x4148)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x414c)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x4150)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x4154)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0                 MK_ADDR_CONST(0x4158)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0                 MK_ADDR_CONST(0x415c)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_SCR                     CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x4160)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x4164)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x4180)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x4184)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE6_IER_0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0                 MK_ADDR_CONST(0x4188)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x418c)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x4190)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x4194)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0                 MK_ADDR_CONST(0x4198)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0                 MK_ADDR_CONST(0x419c)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_SCR                     CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x41a0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x41a4)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x41c0)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x41c4)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE7_IER_0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0                 MK_ADDR_CONST(0x41c8)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x41cc)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x41d0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x41d4)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0                 MK_ADDR_CONST(0x41d8)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0                 MK_ADDR_CONST(0x41dc)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_SCR                     CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x41e0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x41e4)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x4200)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x4204)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE8_IER_0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0                 MK_ADDR_CONST(0x4208)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x420c)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x4210)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x4214)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0                 MK_ADDR_CONST(0x4218)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0                 MK_ADDR_CONST(0x421c)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_SCR                     CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x4220)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x4224)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x4240)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x4244)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE9_IER_0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0                 MK_ADDR_CONST(0x4248)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x424c)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x4250)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x4254)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE9_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0                 MK_ADDR_CONST(0x4258)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_SCR                     CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE9_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0                 MK_ADDR_CONST(0x425c)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_SCR                     CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x4260)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x4264)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x4280)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x4284)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE10_IER_0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0                        MK_ADDR_CONST(0x4288)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x428c)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x4290)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x4294)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE10_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0                        MK_ADDR_CONST(0x4298)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE10_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0                        MK_ADDR_CONST(0x429c)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_SCR                    CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x42a0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x42a4)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x42c0)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x42c4)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE11_IER_0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0                        MK_ADDR_CONST(0x42c8)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x42cc)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x42d0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x42d4)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE11_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0                        MK_ADDR_CONST(0x42d8)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE11_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0                        MK_ADDR_CONST(0x42dc)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_SCR                    CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x42e0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x42e4)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x4300)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x4304)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE12_IER_0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0                        MK_ADDR_CONST(0x4308)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x430c)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x4310)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x4314)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE12_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0                        MK_ADDR_CONST(0x4318)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE12_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0                        MK_ADDR_CONST(0x431c)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_SCR                    CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x4320)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x4324)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x4340)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x4344)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE13_IER_0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0                        MK_ADDR_CONST(0x4348)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x434c)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x4350)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x4354)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE13_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0                        MK_ADDR_CONST(0x4358)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE13_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0                        MK_ADDR_CONST(0x435c)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_SCR                    CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x4360)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x4364)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x4380)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x4384)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE14_IER_0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0                        MK_ADDR_CONST(0x4388)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x438c)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x4390)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x4394)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE14_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0                        MK_ADDR_CONST(0x4398)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE14_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0                        MK_ADDR_CONST(0x439c)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_SCR                    CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x43a0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x43a4)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x43c0)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x43c4)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE15_IER_0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0                        MK_ADDR_CONST(0x43c8)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x43cc)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x43d0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x43d4)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE15_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0                        MK_ADDR_CONST(0x43d8)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE15_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0                        MK_ADDR_CONST(0x43dc)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_SCR                    CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x43e0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x43e4)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x4400)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x4404)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_SCR                   CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE16_IER_0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0                        MK_ADDR_CONST(0x4408)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x440c)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x4410)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x4414)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE16_ISR_0
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0                        MK_ADDR_CONST(0x4418)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_SCR                    CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE16_IDR_0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0                        MK_ADDR_CONST(0x441c)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_SCR                    CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x4420)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x4424)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0                  MK_ADDR_CONST(0x47c0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SCRREG                   0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0                  MK_ADDR_CONST(0x47c4)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SCRREG                   0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x4800)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x4804)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE0_IER_0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0                 MK_ADDR_CONST(0x4808)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x480c)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x4810)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x4814)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0                 MK_ADDR_CONST(0x4818)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0                 MK_ADDR_CONST(0x481c)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_SCR                     CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x4820)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x4824)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x4840)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x4844)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE1_IER_0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0                 MK_ADDR_CONST(0x4848)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x484c)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x4850)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x4854)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0                 MK_ADDR_CONST(0x4858)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0                 MK_ADDR_CONST(0x485c)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_SCR                     CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x4860)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x4864)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x4880)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x4884)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE2_IER_0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0                 MK_ADDR_CONST(0x4888)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x488c)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x4890)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x4894)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0                 MK_ADDR_CONST(0x4898)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0                 MK_ADDR_CONST(0x489c)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_SCR                     CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x48a0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x48a4)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x48c0)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x48c4)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE3_IER_0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0                 MK_ADDR_CONST(0x48c8)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x48cc)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x48d0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x48d4)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0                 MK_ADDR_CONST(0x48d8)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0                 MK_ADDR_CONST(0x48dc)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_SCR                     CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x48e0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x48e4)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x4900)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x4904)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE4_IER_0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0                 MK_ADDR_CONST(0x4908)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x490c)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x4910)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x4914)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0                 MK_ADDR_CONST(0x4918)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0                 MK_ADDR_CONST(0x491c)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_SCR                     CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x4920)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x4924)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x4940)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x4944)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE5_IER_0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0                 MK_ADDR_CONST(0x4948)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x494c)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x4950)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x4954)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0                 MK_ADDR_CONST(0x4958)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0                 MK_ADDR_CONST(0x495c)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_SCR                     CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x4960)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x4964)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x4980)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x4984)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE6_IER_0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0                 MK_ADDR_CONST(0x4988)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x498c)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x4990)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x4994)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0                 MK_ADDR_CONST(0x4998)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0                 MK_ADDR_CONST(0x499c)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_SCR                     CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x49a0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x49a4)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x49c0)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x49c4)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE7_IER_0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0                 MK_ADDR_CONST(0x49c8)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x49cc)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x49d0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x49d4)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0                 MK_ADDR_CONST(0x49d8)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0                 MK_ADDR_CONST(0x49dc)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_SCR                     CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x49e0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x49e4)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x4a00)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x4a04)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE8_IER_0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0                 MK_ADDR_CONST(0x4a08)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x4a0c)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x4a10)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x4a14)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0                 MK_ADDR_CONST(0x4a18)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0                 MK_ADDR_CONST(0x4a1c)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_SCR                     CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x4a20)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x4a24)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x4a40)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x4a44)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE9_IER_0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0                 MK_ADDR_CONST(0x4a48)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x4a4c)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x4a50)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x4a54)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE9_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0                 MK_ADDR_CONST(0x4a58)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_SCR                     CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE9_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0                 MK_ADDR_CONST(0x4a5c)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_SCR                     CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x4a60)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x4a64)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x4a80)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x4a84)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE10_IER_0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0                        MK_ADDR_CONST(0x4a88)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x4a8c)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x4a90)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x4a94)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE10_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0                        MK_ADDR_CONST(0x4a98)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE10_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0                        MK_ADDR_CONST(0x4a9c)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_SCR                    CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x4aa0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x4aa4)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x4ac0)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x4ac4)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE11_IER_0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0                        MK_ADDR_CONST(0x4ac8)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x4acc)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x4ad0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x4ad4)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE11_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0                        MK_ADDR_CONST(0x4ad8)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE11_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0                        MK_ADDR_CONST(0x4adc)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_SCR                    CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x4ae0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x4ae4)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x4b00)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x4b04)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE12_IER_0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0                        MK_ADDR_CONST(0x4b08)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x4b0c)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x4b10)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x4b14)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE12_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0                        MK_ADDR_CONST(0x4b18)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE12_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0                        MK_ADDR_CONST(0x4b1c)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_SCR                    CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x4b20)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x4b24)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x4b40)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x4b44)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE13_IER_0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0                        MK_ADDR_CONST(0x4b48)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x4b4c)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x4b50)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x4b54)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE13_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0                        MK_ADDR_CONST(0x4b58)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE13_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0                        MK_ADDR_CONST(0x4b5c)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_SCR                    CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x4b60)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x4b64)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x4b80)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x4b84)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE14_IER_0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0                        MK_ADDR_CONST(0x4b88)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x4b8c)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x4b90)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x4b94)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE14_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0                        MK_ADDR_CONST(0x4b98)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE14_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0                        MK_ADDR_CONST(0x4b9c)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_SCR                    CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x4ba0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x4ba4)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x4bc0)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x4bc4)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE15_IER_0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0                        MK_ADDR_CONST(0x4bc8)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x4bcc)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x4bd0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x4bd4)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE15_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0                        MK_ADDR_CONST(0x4bd8)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE15_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0                        MK_ADDR_CONST(0x4bdc)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_SCR                    CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x4be0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x4be4)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x4c00)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x4c04)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_SCR                   CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE16_IER_0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0                        MK_ADDR_CONST(0x4c08)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x4c0c)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x4c10)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x4c14)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE16_ISR_0
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0                        MK_ADDR_CONST(0x4c18)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_SCR                    CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE16_IDR_0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0                        MK_ADDR_CONST(0x4c1c)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_SCR                    CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x4c20)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x4c24)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0                  MK_ADDR_CONST(0x4fc0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SCR                      0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SCRREG                   0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0                  MK_ADDR_CONST(0x4fc4)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SCR                      0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SCRREG                   0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_RANGE                    29:29
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_RANGE                    28:28
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_RANGE                    27:27
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_RANGE                  26:24
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_RANGE                        23:23
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_RANGE                        22:22
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_RANGE                        21:21
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_RANGE                        20:20
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_RANGE                        19:19
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_RANGE                        18:18
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_RANGE                        17:17
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_RANGE                        16:16
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_RANGE                        15:15
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_RANGE                        14:14
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_RANGE                        13:13
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_RANGE                        12:12
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_RANGE                        11:11
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_RANGE                        10:10
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_RANGE                        9:9
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_RANGE                        8:8
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_RANGE                        7:7
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_RANGE                        6:6
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_RANGE                        5:5
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_RANGE                        4:4
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_RANGE                        3:3
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_RANGE                        2:2
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_RANGE                        1:1
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_RANGE                        0:0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0                       MK_ADDR_CONST(0x5000)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0                       MK_ADDR_CONST(0x5004)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE0_IER_0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0                        MK_ADDR_CONST(0x5008)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0                    MK_ADDR_CONST(0x500c)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0                    MK_ADDR_CONST(0x5010)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0                  MK_ADDR_CONST(0x5014)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0                        MK_ADDR_CONST(0x5018)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0                        MK_ADDR_CONST(0x501c)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_SCR                    CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0                    MK_ADDR_CONST(0x5020)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0                    MK_ADDR_CONST(0x5024)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0                       MK_ADDR_CONST(0x5040)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0                       MK_ADDR_CONST(0x5044)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE1_IER_0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0                        MK_ADDR_CONST(0x5048)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0                    MK_ADDR_CONST(0x504c)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0                    MK_ADDR_CONST(0x5050)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0                  MK_ADDR_CONST(0x5054)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0                        MK_ADDR_CONST(0x5058)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0                        MK_ADDR_CONST(0x505c)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_SCR                    CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0                    MK_ADDR_CONST(0x5060)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0                    MK_ADDR_CONST(0x5064)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0                       MK_ADDR_CONST(0x5080)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0                       MK_ADDR_CONST(0x5084)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE2_IER_0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0                        MK_ADDR_CONST(0x5088)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0                    MK_ADDR_CONST(0x508c)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0                    MK_ADDR_CONST(0x5090)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0                  MK_ADDR_CONST(0x5094)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0                        MK_ADDR_CONST(0x5098)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0                        MK_ADDR_CONST(0x509c)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_SCR                    CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0                    MK_ADDR_CONST(0x50a0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0                    MK_ADDR_CONST(0x50a4)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0                       MK_ADDR_CONST(0x50c0)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0                       MK_ADDR_CONST(0x50c4)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE3_IER_0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0                        MK_ADDR_CONST(0x50c8)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0                    MK_ADDR_CONST(0x50cc)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0                    MK_ADDR_CONST(0x50d0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0                  MK_ADDR_CONST(0x50d4)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0                        MK_ADDR_CONST(0x50d8)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0                        MK_ADDR_CONST(0x50dc)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_SCR                    CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0                    MK_ADDR_CONST(0x50e0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0                    MK_ADDR_CONST(0x50e4)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0                       MK_ADDR_CONST(0x5100)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0                       MK_ADDR_CONST(0x5104)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE4_IER_0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0                        MK_ADDR_CONST(0x5108)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0                    MK_ADDR_CONST(0x510c)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0                    MK_ADDR_CONST(0x5110)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0                  MK_ADDR_CONST(0x5114)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0                        MK_ADDR_CONST(0x5118)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0                        MK_ADDR_CONST(0x511c)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_SCR                    CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0                    MK_ADDR_CONST(0x5120)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0                    MK_ADDR_CONST(0x5124)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0                       MK_ADDR_CONST(0x5140)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0                       MK_ADDR_CONST(0x5144)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE5_IER_0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0                        MK_ADDR_CONST(0x5148)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0                    MK_ADDR_CONST(0x514c)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0                    MK_ADDR_CONST(0x5150)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0                  MK_ADDR_CONST(0x5154)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0                        MK_ADDR_CONST(0x5158)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0                        MK_ADDR_CONST(0x515c)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_SCR                    CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0                    MK_ADDR_CONST(0x5160)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0                    MK_ADDR_CONST(0x5164)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0                       MK_ADDR_CONST(0x5180)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0                       MK_ADDR_CONST(0x5184)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE6_IER_0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0                        MK_ADDR_CONST(0x5188)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0                    MK_ADDR_CONST(0x518c)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0                    MK_ADDR_CONST(0x5190)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0                  MK_ADDR_CONST(0x5194)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0                        MK_ADDR_CONST(0x5198)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0                        MK_ADDR_CONST(0x519c)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_SCR                    CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0                    MK_ADDR_CONST(0x51a0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0                    MK_ADDR_CONST(0x51a4)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0                       MK_ADDR_CONST(0x51c0)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0                       MK_ADDR_CONST(0x51c4)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE7_IER_0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0                        MK_ADDR_CONST(0x51c8)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0                    MK_ADDR_CONST(0x51cc)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0                    MK_ADDR_CONST(0x51d0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0                  MK_ADDR_CONST(0x51d4)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0                        MK_ADDR_CONST(0x51d8)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0                        MK_ADDR_CONST(0x51dc)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_SCR                    CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0                    MK_ADDR_CONST(0x51e0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0                    MK_ADDR_CONST(0x51e4)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0                       MK_ADDR_CONST(0x5200)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0                       MK_ADDR_CONST(0x5204)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE8_IER_0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0                        MK_ADDR_CONST(0x5208)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0                    MK_ADDR_CONST(0x520c)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0                    MK_ADDR_CONST(0x5210)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0                  MK_ADDR_CONST(0x5214)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0                        MK_ADDR_CONST(0x5218)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0                        MK_ADDR_CONST(0x521c)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_SCR                    CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0                    MK_ADDR_CONST(0x5220)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0                    MK_ADDR_CONST(0x5224)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0                       MK_ADDR_CONST(0x5240)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0                       MK_ADDR_CONST(0x5244)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE9_IER_0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0                        MK_ADDR_CONST(0x5248)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0                    MK_ADDR_CONST(0x524c)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0                    MK_ADDR_CONST(0x5250)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0                  MK_ADDR_CONST(0x5254)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE9_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0                        MK_ADDR_CONST(0x5258)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_SCR                    CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE9_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0                        MK_ADDR_CONST(0x525c)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_SCR                    CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0                    MK_ADDR_CONST(0x5260)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0                    MK_ADDR_CONST(0x5264)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0                      MK_ADDR_CONST(0x5280)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0                      MK_ADDR_CONST(0x5284)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE10_IER_0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0                       MK_ADDR_CONST(0x5288)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0                   MK_ADDR_CONST(0x528c)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0                   MK_ADDR_CONST(0x5290)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0                 MK_ADDR_CONST(0x5294)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE10_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0                       MK_ADDR_CONST(0x5298)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE10_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0                       MK_ADDR_CONST(0x529c)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_SCR                   CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0                   MK_ADDR_CONST(0x52a0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0                   MK_ADDR_CONST(0x52a4)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0                      MK_ADDR_CONST(0x52c0)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0                      MK_ADDR_CONST(0x52c4)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE11_IER_0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0                       MK_ADDR_CONST(0x52c8)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0                   MK_ADDR_CONST(0x52cc)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0                   MK_ADDR_CONST(0x52d0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0                 MK_ADDR_CONST(0x52d4)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE11_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0                       MK_ADDR_CONST(0x52d8)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE11_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0                       MK_ADDR_CONST(0x52dc)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_SCR                   CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0                   MK_ADDR_CONST(0x52e0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0                   MK_ADDR_CONST(0x52e4)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0                      MK_ADDR_CONST(0x5300)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0                      MK_ADDR_CONST(0x5304)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE12_IER_0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0                       MK_ADDR_CONST(0x5308)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0                   MK_ADDR_CONST(0x530c)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0                   MK_ADDR_CONST(0x5310)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0                 MK_ADDR_CONST(0x5314)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE12_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0                       MK_ADDR_CONST(0x5318)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE12_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0                       MK_ADDR_CONST(0x531c)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_SCR                   CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0                   MK_ADDR_CONST(0x5320)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0                   MK_ADDR_CONST(0x5324)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0                      MK_ADDR_CONST(0x5340)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0                      MK_ADDR_CONST(0x5344)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE13_IER_0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0                       MK_ADDR_CONST(0x5348)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0                   MK_ADDR_CONST(0x534c)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0                   MK_ADDR_CONST(0x5350)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0                 MK_ADDR_CONST(0x5354)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE13_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0                       MK_ADDR_CONST(0x5358)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE13_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0                       MK_ADDR_CONST(0x535c)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_SCR                   CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0                   MK_ADDR_CONST(0x5360)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0                   MK_ADDR_CONST(0x5364)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0                      MK_ADDR_CONST(0x5380)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0                      MK_ADDR_CONST(0x5384)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE14_IER_0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0                       MK_ADDR_CONST(0x5388)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0                   MK_ADDR_CONST(0x538c)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0                   MK_ADDR_CONST(0x5390)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0                 MK_ADDR_CONST(0x5394)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE14_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0                       MK_ADDR_CONST(0x5398)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE14_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0                       MK_ADDR_CONST(0x539c)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_SCR                   CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0                   MK_ADDR_CONST(0x53a0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0                   MK_ADDR_CONST(0x53a4)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0                      MK_ADDR_CONST(0x53c0)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0                      MK_ADDR_CONST(0x53c4)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE15_IER_0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0                       MK_ADDR_CONST(0x53c8)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0                   MK_ADDR_CONST(0x53cc)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0                   MK_ADDR_CONST(0x53d0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0                 MK_ADDR_CONST(0x53d4)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE15_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0                       MK_ADDR_CONST(0x53d8)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE15_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0                       MK_ADDR_CONST(0x53dc)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_SCR                   CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0                   MK_ADDR_CONST(0x53e0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0                   MK_ADDR_CONST(0x53e4)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0                      MK_ADDR_CONST(0x5400)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0                      MK_ADDR_CONST(0x5404)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_SCR                  CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE16_IER_0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0                       MK_ADDR_CONST(0x5408)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0                   MK_ADDR_CONST(0x540c)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0                   MK_ADDR_CONST(0x5410)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0                 MK_ADDR_CONST(0x5414)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE16_ISR_0
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0                       MK_ADDR_CONST(0x5418)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_SCR                   CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE16_IDR_0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0                       MK_ADDR_CONST(0x541c)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_SCR                   CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0                   MK_ADDR_CONST(0x5420)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0                   MK_ADDR_CONST(0x5424)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0                        MK_ADDR_CONST(0x57c0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SCR                    0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SCRREG                         0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_RANGE                  29:29
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_RANGE                  28:28
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_RANGE                  27:27
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_RANGE                        26:24
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_RANGE                      23:23
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_RANGE                      22:22
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_RANGE                      21:21
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_RANGE                      20:20
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_RANGE                      19:19
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_RANGE                      18:18
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_RANGE                      17:17
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_RANGE                      16:16
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_RANGE                      15:15
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_RANGE                      14:14
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_RANGE                      13:13
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_RANGE                      12:12
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_RANGE                      11:11
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_RANGE                      10:10
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_RANGE                      9:9
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_RANGE                      8:8
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_RANGE                      7:7
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_RANGE                      6:6
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_RANGE                      5:5
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_RANGE                      4:4
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_RANGE                      3:3
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_RANGE                      2:2
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_RANGE                      1:1
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_RANGE                      0:0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0                        MK_ADDR_CONST(0x57c4)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SCR                    0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SCRREG                         0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_RANGE                  29:29
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_RANGE                  28:28
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_RANGE                  27:27
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_RANGE                        26:24
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_RANGE                      23:23
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_RANGE                      22:22
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_RANGE                      21:21
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_RANGE                      20:20
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_RANGE                      19:19
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_RANGE                      18:18
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_RANGE                      17:17
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_RANGE                      16:16
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_RANGE                      15:15
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_RANGE                      14:14
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_RANGE                      13:13
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_RANGE                      12:12
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_RANGE                      11:11
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_RANGE                      10:10
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_RANGE                      9:9
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_RANGE                      8:8
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_RANGE                      7:7
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_RANGE                      6:6
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_RANGE                      5:5
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_RANGE                      4:4
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_RANGE                      3:3
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_RANGE                      2:2
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_RANGE                      1:1
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_RANGE                      0:0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0                       MK_ADDR_CONST(0x5800)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0                       MK_ADDR_CONST(0x5804)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE0_IER_0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0                        MK_ADDR_CONST(0x5808)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0                    MK_ADDR_CONST(0x580c)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0                    MK_ADDR_CONST(0x5810)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0                  MK_ADDR_CONST(0x5814)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE0_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0                        MK_ADDR_CONST(0x5818)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE0_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0                        MK_ADDR_CONST(0x581c)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_SCR                    CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0                    MK_ADDR_CONST(0x5820)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0                    MK_ADDR_CONST(0x5824)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0                       MK_ADDR_CONST(0x5840)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0                       MK_ADDR_CONST(0x5844)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE1_IER_0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0                        MK_ADDR_CONST(0x5848)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0                    MK_ADDR_CONST(0x584c)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0                    MK_ADDR_CONST(0x5850)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0                  MK_ADDR_CONST(0x5854)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE1_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0                        MK_ADDR_CONST(0x5858)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE1_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0                        MK_ADDR_CONST(0x585c)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_SCR                    CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0                    MK_ADDR_CONST(0x5860)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0                    MK_ADDR_CONST(0x5864)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0                       MK_ADDR_CONST(0x5880)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0                       MK_ADDR_CONST(0x5884)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE2_IER_0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0                        MK_ADDR_CONST(0x5888)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0                    MK_ADDR_CONST(0x588c)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0                    MK_ADDR_CONST(0x5890)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0                  MK_ADDR_CONST(0x5894)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE2_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0                        MK_ADDR_CONST(0x5898)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE2_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0                        MK_ADDR_CONST(0x589c)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_SCR                    CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0                    MK_ADDR_CONST(0x58a0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0                    MK_ADDR_CONST(0x58a4)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0                       MK_ADDR_CONST(0x58c0)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0                       MK_ADDR_CONST(0x58c4)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE3_IER_0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0                        MK_ADDR_CONST(0x58c8)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0                    MK_ADDR_CONST(0x58cc)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0                    MK_ADDR_CONST(0x58d0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0                  MK_ADDR_CONST(0x58d4)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE3_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0                        MK_ADDR_CONST(0x58d8)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE3_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0                        MK_ADDR_CONST(0x58dc)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_SCR                    CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0                    MK_ADDR_CONST(0x58e0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0                    MK_ADDR_CONST(0x58e4)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0                       MK_ADDR_CONST(0x5900)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0                       MK_ADDR_CONST(0x5904)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE4_IER_0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0                        MK_ADDR_CONST(0x5908)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0                    MK_ADDR_CONST(0x590c)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0                    MK_ADDR_CONST(0x5910)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0                  MK_ADDR_CONST(0x5914)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE4_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0                        MK_ADDR_CONST(0x5918)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE4_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0                        MK_ADDR_CONST(0x591c)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_SCR                    CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0                    MK_ADDR_CONST(0x5920)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0                    MK_ADDR_CONST(0x5924)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0                       MK_ADDR_CONST(0x5940)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0                       MK_ADDR_CONST(0x5944)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE5_IER_0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0                        MK_ADDR_CONST(0x5948)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0                    MK_ADDR_CONST(0x594c)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0                    MK_ADDR_CONST(0x5950)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0                  MK_ADDR_CONST(0x5954)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE5_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0                        MK_ADDR_CONST(0x5958)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE5_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0                        MK_ADDR_CONST(0x595c)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_SCR                    CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0                    MK_ADDR_CONST(0x5960)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0                    MK_ADDR_CONST(0x5964)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0                       MK_ADDR_CONST(0x5980)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0                       MK_ADDR_CONST(0x5984)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE6_IER_0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0                        MK_ADDR_CONST(0x5988)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0                    MK_ADDR_CONST(0x598c)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0                    MK_ADDR_CONST(0x5990)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0                  MK_ADDR_CONST(0x5994)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE6_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0                        MK_ADDR_CONST(0x5998)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE6_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0                        MK_ADDR_CONST(0x599c)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_SCR                    CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0                    MK_ADDR_CONST(0x59a0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0                    MK_ADDR_CONST(0x59a4)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0                       MK_ADDR_CONST(0x59c0)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0                       MK_ADDR_CONST(0x59c4)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE7_IER_0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0                        MK_ADDR_CONST(0x59c8)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0                    MK_ADDR_CONST(0x59cc)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0                    MK_ADDR_CONST(0x59d0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0                  MK_ADDR_CONST(0x59d4)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE7_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0                        MK_ADDR_CONST(0x59d8)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE7_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0                        MK_ADDR_CONST(0x59dc)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_SCR                    CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0                    MK_ADDR_CONST(0x59e0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0                    MK_ADDR_CONST(0x59e4)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0                       MK_ADDR_CONST(0x5a00)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0                       MK_ADDR_CONST(0x5a04)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE8_IER_0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0                        MK_ADDR_CONST(0x5a08)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0                    MK_ADDR_CONST(0x5a0c)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0                    MK_ADDR_CONST(0x5a10)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0                  MK_ADDR_CONST(0x5a14)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE8_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0                        MK_ADDR_CONST(0x5a18)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE8_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0                        MK_ADDR_CONST(0x5a1c)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_SCR                    CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0                    MK_ADDR_CONST(0x5a20)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0                    MK_ADDR_CONST(0x5a24)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0                       MK_ADDR_CONST(0x5a40)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0                       MK_ADDR_CONST(0x5a44)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_RANGE                    31:0
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_WOFFSET                  0x0
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE9_IER_0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0                        MK_ADDR_CONST(0x5a48)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0                    MK_ADDR_CONST(0x5a4c)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0                    MK_ADDR_CONST(0x5a50)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0                  MK_ADDR_CONST(0x5a54)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_SECURE                   0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_DUAL                     0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_WORD_COUNT                       0x1
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE9_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0                        MK_ADDR_CONST(0x5a58)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_SCR                    CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE9_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0                        MK_ADDR_CONST(0x5a5c)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_SCR                    CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0                    MK_ADDR_CONST(0x5a60)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0                    MK_ADDR_CONST(0x5a64)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_SECURE                     0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_DUAL                       0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_WORD_COUNT                         0x1
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                      31:0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0                      MK_ADDR_CONST(0x5a80)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0                      MK_ADDR_CONST(0x5a84)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE10_IER_0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0                       MK_ADDR_CONST(0x5a88)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0                   MK_ADDR_CONST(0x5a8c)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0                   MK_ADDR_CONST(0x5a90)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0                 MK_ADDR_CONST(0x5a94)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE10_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0                       MK_ADDR_CONST(0x5a98)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE10_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0                       MK_ADDR_CONST(0x5a9c)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_SCR                   CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0                   MK_ADDR_CONST(0x5aa0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0                   MK_ADDR_CONST(0x5aa4)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0                      MK_ADDR_CONST(0x5ac0)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0                      MK_ADDR_CONST(0x5ac4)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE11_IER_0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0                       MK_ADDR_CONST(0x5ac8)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0                   MK_ADDR_CONST(0x5acc)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0                   MK_ADDR_CONST(0x5ad0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0                 MK_ADDR_CONST(0x5ad4)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE11_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0                       MK_ADDR_CONST(0x5ad8)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE11_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0                       MK_ADDR_CONST(0x5adc)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_SCR                   CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0                   MK_ADDR_CONST(0x5ae0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0                   MK_ADDR_CONST(0x5ae4)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0                      MK_ADDR_CONST(0x5b00)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0                      MK_ADDR_CONST(0x5b04)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE12_IER_0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0                       MK_ADDR_CONST(0x5b08)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0                   MK_ADDR_CONST(0x5b0c)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0                   MK_ADDR_CONST(0x5b10)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0                 MK_ADDR_CONST(0x5b14)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE12_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0                       MK_ADDR_CONST(0x5b18)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE12_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0                       MK_ADDR_CONST(0x5b1c)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_SCR                   CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0                   MK_ADDR_CONST(0x5b20)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0                   MK_ADDR_CONST(0x5b24)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0                      MK_ADDR_CONST(0x5b40)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0                      MK_ADDR_CONST(0x5b44)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE13_IER_0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0                       MK_ADDR_CONST(0x5b48)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0                   MK_ADDR_CONST(0x5b4c)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0                   MK_ADDR_CONST(0x5b50)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0                 MK_ADDR_CONST(0x5b54)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE13_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0                       MK_ADDR_CONST(0x5b58)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE13_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0                       MK_ADDR_CONST(0x5b5c)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_SCR                   CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0                   MK_ADDR_CONST(0x5b60)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0                   MK_ADDR_CONST(0x5b64)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0                      MK_ADDR_CONST(0x5b80)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0                      MK_ADDR_CONST(0x5b84)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE14_IER_0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0                       MK_ADDR_CONST(0x5b88)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0                   MK_ADDR_CONST(0x5b8c)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0                   MK_ADDR_CONST(0x5b90)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0                 MK_ADDR_CONST(0x5b94)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE14_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0                       MK_ADDR_CONST(0x5b98)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE14_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0                       MK_ADDR_CONST(0x5b9c)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_SCR                   CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0                   MK_ADDR_CONST(0x5ba0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0                   MK_ADDR_CONST(0x5ba4)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0                      MK_ADDR_CONST(0x5bc0)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0                      MK_ADDR_CONST(0x5bc4)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE15_IER_0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0                       MK_ADDR_CONST(0x5bc8)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0                   MK_ADDR_CONST(0x5bcc)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0                   MK_ADDR_CONST(0x5bd0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0                 MK_ADDR_CONST(0x5bd4)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE15_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0                       MK_ADDR_CONST(0x5bd8)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE15_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0                       MK_ADDR_CONST(0x5bdc)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_SCR                   CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0                   MK_ADDR_CONST(0x5be0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0                   MK_ADDR_CONST(0x5be4)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0                      MK_ADDR_CONST(0x5c00)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0                      MK_ADDR_CONST(0x5c04)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_SECURE                       0x0
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_DUAL                         0x0
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_SCR                  CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_WORD_COUNT                   0x1
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_RANGE                   31:0
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_WOFFSET                 0x0
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE16_IER_0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0                       MK_ADDR_CONST(0x5c08)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0                   MK_ADDR_CONST(0x5c0c)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0                   MK_ADDR_CONST(0x5c10)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0                 MK_ADDR_CONST(0x5c14)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_SECURE                  0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_DUAL                    0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_WORD_COUNT                      0x1
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE16_ISR_0
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0                       MK_ADDR_CONST(0x5c18)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_SCR                   CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE16_IDR_0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0                       MK_ADDR_CONST(0x5c1c)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_SECURE                        0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_DUAL                  0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_SCR                   CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_WORD_COUNT                    0x1
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0                   MK_ADDR_CONST(0x5c20)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0                   MK_ADDR_CONST(0x5c24)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_SECURE                    0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_DUAL                      0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_WORD_COUNT                        0x1
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                     31:0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0                        MK_ADDR_CONST(0x5fc0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SCR                    0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SCRREG                         0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_RANGE                  29:29
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_RANGE                  28:28
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_RANGE                  27:27
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_RANGE                        26:24
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_RANGE                      23:23
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_RANGE                      22:22
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_RANGE                      21:21
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_RANGE                      20:20
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_RANGE                      19:19
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_RANGE                      18:18
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_RANGE                      17:17
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_RANGE                      16:16
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_RANGE                      15:15
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_RANGE                      14:14
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_RANGE                      13:13
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_RANGE                      12:12
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_RANGE                      11:11
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_RANGE                      10:10
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_RANGE                      9:9
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_RANGE                      8:8
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_RANGE                      7:7
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_RANGE                      6:6
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_RANGE                      5:5
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_RANGE                      4:4
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_RANGE                      3:3
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_RANGE                      2:2
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_RANGE                      1:1
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_RANGE                      0:0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0                        MK_ADDR_CONST(0x5fc4)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SECURE                         0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_DUAL                   0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SCR                    0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SCRREG                         0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_WORD_COUNT                     0x1
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_RANGE                  29:29
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_RANGE                  28:28
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_RANGE                  27:27
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_WOFFSET                        0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_RANGE                        26:24
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_WOFFSET                      0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_RANGE                      23:23
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_RANGE                      22:22
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_RANGE                      21:21
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_RANGE                      20:20
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_RANGE                      19:19
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_RANGE                      18:18
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_RANGE                      17:17
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_RANGE                      16:16
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_RANGE                      15:15
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_RANGE                      14:14
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_RANGE                      13:13
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_RANGE                      12:12
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_RANGE                      11:11
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_RANGE                      10:10
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_RANGE                      9:9
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_RANGE                      8:8
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_RANGE                      7:7
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_RANGE                      6:6
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_RANGE                      5:5
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_RANGE                      4:4
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_RANGE                      3:3
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_RANGE                      2:2
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_RANGE                      1:1
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_SHIFT)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_RANGE                      0:0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_WOFFSET                    0x0
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE0_GISR_0
#define INTR_CTLR_COMMON_SLICE0_GISR_0                  MK_ADDR_CONST(0xf800)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE0_GISR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE0_GISR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE0_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE0_FIR_0
#define INTR_CTLR_COMMON_SLICE0_FIR_0                   MK_ADDR_CONST(0xf804)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_0_DUAL                      0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_0_SCR                       SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE0_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE0_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0                       MK_ADDR_CONST(0xf808)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE0_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0                       MK_ADDR_CONST(0xf80c)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE0_CIDR_0
#define INTR_CTLR_COMMON_SLICE0_CIDR_0                  MK_ADDR_CONST(0xf810)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE0_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0                      MK_ADDR_CONST(0xf814)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0                      MK_ADDR_CONST(0xf818)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE1_GISR_0
#define INTR_CTLR_COMMON_SLICE1_GISR_0                  MK_ADDR_CONST(0xf840)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE1_GISR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE1_GISR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE1_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE1_FIR_0
#define INTR_CTLR_COMMON_SLICE1_FIR_0                   MK_ADDR_CONST(0xf844)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_0_DUAL                      0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_0_SCR                       SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE1_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE1_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0                       MK_ADDR_CONST(0xf848)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE1_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0                       MK_ADDR_CONST(0xf84c)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE1_CIDR_0
#define INTR_CTLR_COMMON_SLICE1_CIDR_0                  MK_ADDR_CONST(0xf850)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE1_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0                      MK_ADDR_CONST(0xf854)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0                      MK_ADDR_CONST(0xf858)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE2_GISR_0
#define INTR_CTLR_COMMON_SLICE2_GISR_0                  MK_ADDR_CONST(0xf880)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE2_GISR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE2_GISR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE2_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE2_FIR_0
#define INTR_CTLR_COMMON_SLICE2_FIR_0                   MK_ADDR_CONST(0xf884)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_0_DUAL                      0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_0_SCR                       SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE2_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE2_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0                       MK_ADDR_CONST(0xf888)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE2_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0                       MK_ADDR_CONST(0xf88c)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE2_CIDR_0
#define INTR_CTLR_COMMON_SLICE2_CIDR_0                  MK_ADDR_CONST(0xf890)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE2_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0                      MK_ADDR_CONST(0xf894)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0                      MK_ADDR_CONST(0xf898)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE3_GISR_0
#define INTR_CTLR_COMMON_SLICE3_GISR_0                  MK_ADDR_CONST(0xf8c0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE3_GISR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE3_GISR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE3_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE3_FIR_0
#define INTR_CTLR_COMMON_SLICE3_FIR_0                   MK_ADDR_CONST(0xf8c4)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_0_DUAL                      0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_0_SCR                       SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE3_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE3_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0                       MK_ADDR_CONST(0xf8c8)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE3_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0                       MK_ADDR_CONST(0xf8cc)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE3_CIDR_0
#define INTR_CTLR_COMMON_SLICE3_CIDR_0                  MK_ADDR_CONST(0xf8d0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE3_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0                      MK_ADDR_CONST(0xf8d4)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0                      MK_ADDR_CONST(0xf8d8)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE4_GISR_0
#define INTR_CTLR_COMMON_SLICE4_GISR_0                  MK_ADDR_CONST(0xf900)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE4_GISR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE4_GISR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE4_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE4_FIR_0
#define INTR_CTLR_COMMON_SLICE4_FIR_0                   MK_ADDR_CONST(0xf904)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_0_DUAL                      0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_0_SCR                       SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE4_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE4_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0                       MK_ADDR_CONST(0xf908)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE4_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0                       MK_ADDR_CONST(0xf90c)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE4_CIDR_0
#define INTR_CTLR_COMMON_SLICE4_CIDR_0                  MK_ADDR_CONST(0xf910)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE4_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0                      MK_ADDR_CONST(0xf914)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0                      MK_ADDR_CONST(0xf918)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE5_GISR_0
#define INTR_CTLR_COMMON_SLICE5_GISR_0                  MK_ADDR_CONST(0xf940)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE5_GISR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE5_GISR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE5_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE5_FIR_0
#define INTR_CTLR_COMMON_SLICE5_FIR_0                   MK_ADDR_CONST(0xf944)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_0_DUAL                      0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_0_SCR                       SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE5_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE5_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0                       MK_ADDR_CONST(0xf948)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE5_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0                       MK_ADDR_CONST(0xf94c)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE5_CIDR_0
#define INTR_CTLR_COMMON_SLICE5_CIDR_0                  MK_ADDR_CONST(0xf950)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE5_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0                      MK_ADDR_CONST(0xf954)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0                      MK_ADDR_CONST(0xf958)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE6_GISR_0
#define INTR_CTLR_COMMON_SLICE6_GISR_0                  MK_ADDR_CONST(0xf980)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE6_GISR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE6_GISR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE6_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE6_FIR_0
#define INTR_CTLR_COMMON_SLICE6_FIR_0                   MK_ADDR_CONST(0xf984)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_0_DUAL                      0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_0_SCR                       SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE6_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE6_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0                       MK_ADDR_CONST(0xf988)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE6_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0                       MK_ADDR_CONST(0xf98c)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE6_CIDR_0
#define INTR_CTLR_COMMON_SLICE6_CIDR_0                  MK_ADDR_CONST(0xf990)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE6_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0                      MK_ADDR_CONST(0xf994)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0                      MK_ADDR_CONST(0xf998)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE7_GISR_0
#define INTR_CTLR_COMMON_SLICE7_GISR_0                  MK_ADDR_CONST(0xf9c0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE7_GISR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE7_GISR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE7_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE7_FIR_0
#define INTR_CTLR_COMMON_SLICE7_FIR_0                   MK_ADDR_CONST(0xf9c4)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_0_DUAL                      0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_0_SCR                       SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE7_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE7_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0                       MK_ADDR_CONST(0xf9c8)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE7_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0                       MK_ADDR_CONST(0xf9cc)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE7_CIDR_0
#define INTR_CTLR_COMMON_SLICE7_CIDR_0                  MK_ADDR_CONST(0xf9d0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE7_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0                      MK_ADDR_CONST(0xf9d4)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0                      MK_ADDR_CONST(0xf9d8)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE8_GISR_0
#define INTR_CTLR_COMMON_SLICE8_GISR_0                  MK_ADDR_CONST(0xfa00)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE8_GISR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE8_GISR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE8_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE8_FIR_0
#define INTR_CTLR_COMMON_SLICE8_FIR_0                   MK_ADDR_CONST(0xfa04)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_0_DUAL                      0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_0_SCR                       SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE8_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE8_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0                       MK_ADDR_CONST(0xfa08)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE8_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0                       MK_ADDR_CONST(0xfa0c)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE8_CIDR_0
#define INTR_CTLR_COMMON_SLICE8_CIDR_0                  MK_ADDR_CONST(0xfa10)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE8_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0                      MK_ADDR_CONST(0xfa14)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0                      MK_ADDR_CONST(0xfa18)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE9_GISR_0
#define INTR_CTLR_COMMON_SLICE9_GISR_0                  MK_ADDR_CONST(0xfa40)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE9_GISR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE9_GISR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_GISR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE9_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE9_FIR_0
#define INTR_CTLR_COMMON_SLICE9_FIR_0                   MK_ADDR_CONST(0xfa44)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_SECURE                    0x0
#define INTR_CTLR_COMMON_SLICE9_FIR_0_DUAL                      0x0
#define INTR_CTLR_COMMON_SLICE9_FIR_0_SCR                       SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_FIR_0_WORD_COUNT                        0x1
#define INTR_CTLR_COMMON_SLICE9_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE9_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0                       MK_ADDR_CONST(0xfa48)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE9_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0                       MK_ADDR_CONST(0xfa4c)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_SCR                   SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_RANGE                 31:0
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE9_CIDR_0
#define INTR_CTLR_COMMON_SLICE9_CIDR_0                  MK_ADDR_CONST(0xfa50)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE9_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0                      MK_ADDR_CONST(0xfa54)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0                      MK_ADDR_CONST(0xfa58)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE10_GISR_0
#define INTR_CTLR_COMMON_SLICE10_GISR_0                 MK_ADDR_CONST(0xfa80)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE10_GISR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE10_GISR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_GISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE10_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE10_FIR_0
#define INTR_CTLR_COMMON_SLICE10_FIR_0                  MK_ADDR_CONST(0xfa84)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE10_FIR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE10_FIR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_FIR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE10_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE10_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0                      MK_ADDR_CONST(0xfa88)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE10_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0                      MK_ADDR_CONST(0xfa8c)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE10_CIDR_0
#define INTR_CTLR_COMMON_SLICE10_CIDR_0                 MK_ADDR_CONST(0xfa90)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE10_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0                     MK_ADDR_CONST(0xfa94)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0                     MK_ADDR_CONST(0xfa98)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE11_GISR_0
#define INTR_CTLR_COMMON_SLICE11_GISR_0                 MK_ADDR_CONST(0xfac0)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE11_GISR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE11_GISR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_GISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE11_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE11_FIR_0
#define INTR_CTLR_COMMON_SLICE11_FIR_0                  MK_ADDR_CONST(0xfac4)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE11_FIR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE11_FIR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_FIR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE11_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE11_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0                      MK_ADDR_CONST(0xfac8)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE11_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0                      MK_ADDR_CONST(0xfacc)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE11_CIDR_0
#define INTR_CTLR_COMMON_SLICE11_CIDR_0                 MK_ADDR_CONST(0xfad0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE11_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0                     MK_ADDR_CONST(0xfad4)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0                     MK_ADDR_CONST(0xfad8)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE12_GISR_0
#define INTR_CTLR_COMMON_SLICE12_GISR_0                 MK_ADDR_CONST(0xfb00)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE12_GISR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE12_GISR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_GISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE12_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE12_FIR_0
#define INTR_CTLR_COMMON_SLICE12_FIR_0                  MK_ADDR_CONST(0xfb04)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE12_FIR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE12_FIR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_FIR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE12_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE12_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0                      MK_ADDR_CONST(0xfb08)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE12_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0                      MK_ADDR_CONST(0xfb0c)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE12_CIDR_0
#define INTR_CTLR_COMMON_SLICE12_CIDR_0                 MK_ADDR_CONST(0xfb10)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE12_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0                     MK_ADDR_CONST(0xfb14)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0                     MK_ADDR_CONST(0xfb18)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE13_GISR_0
#define INTR_CTLR_COMMON_SLICE13_GISR_0                 MK_ADDR_CONST(0xfb40)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE13_GISR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE13_GISR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_GISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE13_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE13_FIR_0
#define INTR_CTLR_COMMON_SLICE13_FIR_0                  MK_ADDR_CONST(0xfb44)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE13_FIR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE13_FIR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_FIR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE13_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE13_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0                      MK_ADDR_CONST(0xfb48)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE13_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0                      MK_ADDR_CONST(0xfb4c)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE13_CIDR_0
#define INTR_CTLR_COMMON_SLICE13_CIDR_0                 MK_ADDR_CONST(0xfb50)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE13_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0                     MK_ADDR_CONST(0xfb54)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0                     MK_ADDR_CONST(0xfb58)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE14_GISR_0
#define INTR_CTLR_COMMON_SLICE14_GISR_0                 MK_ADDR_CONST(0xfb80)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE14_GISR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE14_GISR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_GISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE14_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE14_FIR_0
#define INTR_CTLR_COMMON_SLICE14_FIR_0                  MK_ADDR_CONST(0xfb84)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE14_FIR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE14_FIR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_FIR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE14_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE14_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0                      MK_ADDR_CONST(0xfb88)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE14_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0                      MK_ADDR_CONST(0xfb8c)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE14_CIDR_0
#define INTR_CTLR_COMMON_SLICE14_CIDR_0                 MK_ADDR_CONST(0xfb90)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE14_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0                     MK_ADDR_CONST(0xfb94)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0                     MK_ADDR_CONST(0xfb98)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE15_GISR_0
#define INTR_CTLR_COMMON_SLICE15_GISR_0                 MK_ADDR_CONST(0xfbc0)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE15_GISR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE15_GISR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_GISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE15_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE15_FIR_0
#define INTR_CTLR_COMMON_SLICE15_FIR_0                  MK_ADDR_CONST(0xfbc4)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE15_FIR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE15_FIR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_FIR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE15_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE15_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0                      MK_ADDR_CONST(0xfbc8)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE15_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0                      MK_ADDR_CONST(0xfbcc)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE15_CIDR_0
#define INTR_CTLR_COMMON_SLICE15_CIDR_0                 MK_ADDR_CONST(0xfbd0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE15_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0                     MK_ADDR_CONST(0xfbd4)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0                     MK_ADDR_CONST(0xfbd8)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE16_GISR_0
#define INTR_CTLR_COMMON_SLICE16_GISR_0                 MK_ADDR_CONST(0xfc00)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE16_GISR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE16_GISR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_GISR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE16_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_SHIFT)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE16_FIR_0
#define INTR_CTLR_COMMON_SLICE16_FIR_0                  MK_ADDR_CONST(0xfc04)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_SECURE                   0x0
#define INTR_CTLR_COMMON_SLICE16_FIR_0_DUAL                     0x0
#define INTR_CTLR_COMMON_SLICE16_FIR_0_SCR                      SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_FIR_0_WORD_COUNT                       0x1
#define INTR_CTLR_COMMON_SLICE16_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_SHIFT)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE16_FIR_SET_0
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0                      MK_ADDR_CONST(0xfc08)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE16_FIR_CLR_0
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0                      MK_ADDR_CONST(0xfc0c)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_SECURE                       0x0
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_DUAL                         0x0
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_SCR                  SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_WORD_COUNT                   0x1
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_RANGE                        31:0
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE16_CIDR_0
#define INTR_CTLR_COMMON_SLICE16_CIDR_0                 MK_ADDR_CONST(0xfc10)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_SECURE                  0x0
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_DUAL                    0x0
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_SCR                     SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_WORD_COUNT                      0x1
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_SHIFT)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE16_CIDR_SET_0
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0                     MK_ADDR_CONST(0xfc14)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_SHIFT)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0                     MK_ADDR_CONST(0xfc18)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_SECURE                      0x0
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_DUAL                        0x0
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_SCR                         SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_WORD_COUNT                  0x1
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_SHIFT)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xfc40

// Reserved address 0xfc44

// Reserved address 0xfc48

// Reserved address 0xfc4c

// Reserved address 0xfc50

// Reserved address 0xfc54

// Reserved address 0xfc58

// Reserved address 0xfc5c

// Reserved address 0xfc60

// Reserved address 0xfc64

// Reserved address 0xfc68

// Reserved address 0xfc6c

// Reserved address 0xfc70

// Reserved address 0xfc74

// Reserved address 0xfc78

// Reserved address 0xfc7c

// Reserved address 0xfc80

// Reserved address 0xfc84

// Reserved address 0xfc88

// Reserved address 0xfc8c

// Reserved address 0xfc90

// Reserved address 0xfc94

// Reserved address 0xfc98

// Reserved address 0xfc9c

// Reserved address 0xfca0

// Reserved address 0xfca4

// Reserved address 0xfca8

// Reserved address 0xfcac

// Reserved address 0xfcb0

// Reserved address 0xfcb4

// Reserved address 0xfcb8

// Reserved address 0xfcbc

// Reserved address 0xfcc0

// Reserved address 0xfcc4

// Reserved address 0xfcc8

// Reserved address 0xfccc

// Reserved address 0xfcd0

// Reserved address 0xfcd4

// Reserved address 0xfcd8

// Reserved address 0xfcdc

// Reserved address 0xfce0

// Reserved address 0xfce4

// Reserved address 0xfce8

// Reserved address 0xfcec

// Reserved address 0xfcf0

// Reserved address 0xfcf4

// Reserved address 0xfcf8

// Reserved address 0xfcfc

// Reserved address 0xfd00

// Reserved address 0xfd04

// Reserved address 0xfd08

// Reserved address 0xfd0c

// Reserved address 0xfd10

// Reserved address 0xfd14

// Reserved address 0xfd18

// Reserved address 0xfd1c

// Reserved address 0xfd20

// Reserved address 0xfd24

// Reserved address 0xfd28

// Reserved address 0xfd2c

// Reserved address 0xfd30

// Reserved address 0xfd34

// Reserved address 0xfd38

// Reserved address 0xfd3c

// Reserved address 0xfd40

// Reserved address 0xfd44

// Reserved address 0xfd48

// Reserved address 0xfd4c

// Reserved address 0xfd50

// Reserved address 0xfd54

// Reserved address 0xfd58

// Reserved address 0xfd5c

// Reserved address 0xfd60

// Reserved address 0xfd64

// Reserved address 0xfd68

// Reserved address 0xfd6c

// Reserved address 0xfd70

// Reserved address 0xfd74

// Reserved address 0xfd78

// Reserved address 0xfd7c

// Reserved address 0xfd80

// Reserved address 0xfd84

// Reserved address 0xfd88

// Reserved address 0xfd8c

// Reserved address 0xfd90

// Reserved address 0xfd94

// Reserved address 0xfd98

// Reserved address 0xfd9c

// Reserved address 0xfda0

// Reserved address 0xfda4

// Reserved address 0xfda8

// Reserved address 0xfdac

// Reserved address 0xfdb0

// Reserved address 0xfdb4

// Reserved address 0xfdb8

// Reserved address 0xfdbc

// Reserved address 0xfdc0

// Reserved address 0xfdc4

// Reserved address 0xfdc8

// Reserved address 0xfdcc

// Reserved address 0xfdd0

// Reserved address 0xfdd4

// Reserved address 0xfdd8

// Reserved address 0xfddc

// Reserved address 0xfde0

// Reserved address 0xfde4

// Reserved address 0xfde8

// Reserved address 0xfdec

// Reserved address 0xfdf0

// Reserved address 0xfdf4

// Reserved address 0xfdf8

// Reserved address 0xfdfc

// Reserved address 0xfe00

// Reserved address 0xfe04

// Reserved address 0xfe08

// Reserved address 0xfe0c

// Reserved address 0xfe10

// Reserved address 0xfe14

// Reserved address 0xfe18

// Reserved address 0xfe1c

// Reserved address 0xfe20

// Reserved address 0xfe24

// Reserved address 0xfe28

// Reserved address 0xfe2c

// Reserved address 0xfe30

// Reserved address 0xfe34

// Reserved address 0xfe38

// Reserved address 0xfe3c

// Reserved address 0xfe40

// Reserved address 0xfe44

// Reserved address 0xfe48

// Reserved address 0xfe4c

// Reserved address 0xfe50

// Reserved address 0xfe54

// Reserved address 0xfe58

// Reserved address 0xfe5c

// Reserved address 0xfe60

// Reserved address 0xfe64

// Reserved address 0xfe68

// Reserved address 0xfe6c

// Reserved address 0xfe70

// Reserved address 0xfe74

// Reserved address 0xfe78

// Reserved address 0xfe7c

// Reserved address 0xfe80

// Reserved address 0xfe84

// Reserved address 0xfe88

// Reserved address 0xfe8c

// Reserved address 0xfe90

// Reserved address 0xfe94

// Reserved address 0xfe98

// Reserved address 0xfe9c

// Reserved address 0xfea0

// Reserved address 0xfea4

// Reserved address 0xfea8

// Reserved address 0xfeac

// Reserved address 0xfeb0

// Reserved address 0xfeb4

// Reserved address 0xfeb8

// Reserved address 0xfebc

// Reserved address 0xfec0

// Reserved address 0xfec4

// Reserved address 0xfec8

// Reserved address 0xfecc

// Reserved address 0xfed0

// Reserved address 0xfed4

// Reserved address 0xfed8

// Reserved address 0xfedc

// Reserved address 0xfee0

// Reserved address 0xfee4

// Reserved address 0xfee8

// Reserved address 0xfeec

// Reserved address 0xfef0

// Reserved address 0xfef4

// Reserved address 0xfef8

// Reserved address 0xfefc

// Reserved address 0xff00

// Reserved address 0xff04

// Reserved address 0xff08

// Reserved address 0xff0c

// Reserved address 0xff10

// Reserved address 0xff14

// Reserved address 0xff18

// Reserved address 0xff1c

// Reserved address 0xff20

// Reserved address 0xff24

// Reserved address 0xff28

// Reserved address 0xff2c

// Reserved address 0xff30

// Reserved address 0xff34

// Reserved address 0xff38

// Reserved address 0xff3c

// Reserved address 0xff40

// Reserved address 0xff44

// Reserved address 0xff48

// Reserved address 0xff4c

// Reserved address 0xff50

// Reserved address 0xff54

// Reserved address 0xff58

// Reserved address 0xff5c

// Reserved address 0xff60

// Reserved address 0xff64

// Reserved address 0xff68

// Reserved address 0xff6c

// Reserved address 0xff70

// Reserved address 0xff74

// Reserved address 0xff78

// Reserved address 0xff7c

// Reserved address 0xff80

// Reserved address 0xff84

// Reserved address 0xff88

// Reserved address 0xff8c

// Reserved address 0xff90

// Reserved address 0xff94

// Reserved address 0xff98

// Reserved address 0xff9c

// Reserved address 0xffa0

// Reserved address 0xffa4

// Reserved address 0xffa8

// Reserved address 0xffac

// Reserved address 0xffb0

// Reserved address 0xffb4

// Reserved address 0xffb8

// Reserved address 0xffbc

// Reserved address 0xffc0

// Register INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0                       MK_ADDR_CONST(0xffc4)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SECURE                        0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_DUAL                  0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SCR                   0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SCRREG                        0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_WORD_COUNT                    0x1
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_RANGE                 29:29
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_RANGE                 28:28
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_RANGE                 27:27
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_WOFFSET                       0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_RANGE                       26:24
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_WOFFSET                     0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_RANGE                     23:23
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_MSB                       MK_SHIFT_CONST(23)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_LSB                       MK_SHIFT_CONST(23)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_RANGE                     22:22
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_MSB                       MK_SHIFT_CONST(22)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_LSB                       MK_SHIFT_CONST(22)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_RANGE                     21:21
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_MSB                       MK_SHIFT_CONST(21)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_LSB                       MK_SHIFT_CONST(21)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_RANGE                     20:20
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_MSB                       MK_SHIFT_CONST(20)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_LSB                       MK_SHIFT_CONST(20)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_RANGE                     19:19
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_MSB                       MK_SHIFT_CONST(19)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_LSB                       MK_SHIFT_CONST(19)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_RANGE                     18:18
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_MSB                       MK_SHIFT_CONST(18)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_LSB                       MK_SHIFT_CONST(18)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_RANGE                     17:17
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_MSB                       MK_SHIFT_CONST(17)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_LSB                       MK_SHIFT_CONST(17)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_RANGE                     16:16
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_MSB                       MK_SHIFT_CONST(16)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_LSB                       MK_SHIFT_CONST(16)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_RANGE                     15:15
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_MSB                       MK_SHIFT_CONST(15)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_LSB                       MK_SHIFT_CONST(15)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_RANGE                     14:14
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_MSB                       MK_SHIFT_CONST(14)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_LSB                       MK_SHIFT_CONST(14)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_RANGE                     13:13
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_MSB                       MK_SHIFT_CONST(13)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_LSB                       MK_SHIFT_CONST(13)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_RANGE                     12:12
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_MSB                       MK_SHIFT_CONST(12)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_LSB                       MK_SHIFT_CONST(12)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_RANGE                     11:11
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_MSB                       MK_SHIFT_CONST(11)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_LSB                       MK_SHIFT_CONST(11)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_RANGE                     10:10
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_MSB                       MK_SHIFT_CONST(10)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_LSB                       MK_SHIFT_CONST(10)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_RANGE                     9:9
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_MSB                       MK_SHIFT_CONST(9)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_LSB                       MK_SHIFT_CONST(9)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_RANGE                     8:8
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_MSB                       MK_SHIFT_CONST(8)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_LSB                       MK_SHIFT_CONST(8)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_RANGE                     7:7
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_MSB                       MK_SHIFT_CONST(7)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_LSB                       MK_SHIFT_CONST(7)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_RANGE                     6:6
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_MSB                       MK_SHIFT_CONST(6)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_LSB                       MK_SHIFT_CONST(6)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_RANGE                     5:5
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_MSB                       MK_SHIFT_CONST(5)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_LSB                       MK_SHIFT_CONST(5)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_RANGE                     4:4
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_MSB                       MK_SHIFT_CONST(4)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_LSB                       MK_SHIFT_CONST(4)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_RANGE                     3:3
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_MSB                       MK_SHIFT_CONST(3)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_LSB                       MK_SHIFT_CONST(3)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_RANGE                     2:2
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_MSB                       MK_SHIFT_CONST(2)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_LSB                       MK_SHIFT_CONST(2)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_RANGE                     1:1
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_MSB                       MK_SHIFT_CONST(1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_LSB                       MK_SHIFT_CONST(1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_SHIFT)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_RANGE                     0:0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_MSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_LSB                       MK_SHIFT_CONST(0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_WOFFSET                   0x0
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Packet SLICE0_ICTLR_FIELDS_0
#define SLICE0_ICTLR_FIELDS_0_SIZE 32

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_SHIFT                    MK_SHIFT_CONST(0)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_RANGE                    MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_SHIFT                    MK_SHIFT_CONST(1)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_RANGE                    MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_SHIFT                    MK_SHIFT_CONST(2)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_RANGE                    MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_SHIFT                    MK_SHIFT_CONST(3)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_RANGE                    MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_SHIFT                    MK_SHIFT_CONST(4)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_RANGE                    MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_SHIFT                    MK_SHIFT_CONST(5)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_RANGE                    MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_SHIFT                    MK_SHIFT_CONST(6)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_RANGE                    MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_SHIFT                    MK_SHIFT_CONST(7)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_RANGE                    MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_SHIFT                    MK_SHIFT_CONST(8)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_RANGE                    MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_SHIFT                    MK_SHIFT_CONST(9)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_RANGE                    MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_ROW                      0

#define SLICE0_ICTLR_FIELDS_0_RTC_SHIFT                 MK_SHIFT_CONST(10)
#define SLICE0_ICTLR_FIELDS_0_RTC_FIELD                 MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_RTC_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_RTC_RANGE                 MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE0_ICTLR_FIELDS_0_RTC_ROW                   0

#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_SHIFT                   MK_SHIFT_CONST(11)
#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_FIELD                   MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_RANGE                   MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_ROW                     0

#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_SHIFT                   MK_SHIFT_CONST(12)
#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_FIELD                   MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_RANGE                   MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_ROW                     0

#define SLICE0_ICTLR_FIELDS_0_AON_GTE_SHIFT                     MK_SHIFT_CONST(13)
#define SLICE0_ICTLR_FIELDS_0_AON_GTE_FIELD                     MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_AON_GTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_AON_GTE_RANGE                     MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE0_ICTLR_FIELDS_0_AON_GTE_ROW                       0

#define SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_SHIFT                     MK_SHIFT_CONST(14)
#define SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_FIELD                     MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_RANGE                     MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_ROW                       0

#define SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_SHIFT                      MK_SHIFT_CONST(15)
#define SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_FIELD                      MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_RANGE                      MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_ROW                        0

#define SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_SHIFT                      MK_SHIFT_CONST(16)
#define SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_FIELD                      MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_RANGE                      MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_ROW                        0

#define SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_SHIFT                      MK_SHIFT_CONST(17)
#define SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_FIELD                      MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_RANGE                      MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_ROW                        0

#define SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_SHIFT                        MK_SHIFT_CONST(18)
#define SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_RANGE                        MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_RCE_WDT_REMOTE_SHIFT                      MK_SHIFT_CONST(19)
#define SLICE0_ICTLR_FIELDS_0_RCE_WDT_REMOTE_FIELD                      MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_RCE_WDT_REMOTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_RCE_WDT_REMOTE_RANGE                      MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE0_ICTLR_FIELDS_0_RCE_WDT_REMOTE_ROW                        0

#define SLICE0_ICTLR_FIELDS_0_APE_WDT_REMOTE_SHIFT                      MK_SHIFT_CONST(20)
#define SLICE0_ICTLR_FIELDS_0_APE_WDT_REMOTE_FIELD                      MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_APE_WDT_REMOTE_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_APE_WDT_REMOTE_RANGE                      MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE0_ICTLR_FIELDS_0_APE_WDT_REMOTE_ROW                        0

#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF0_SHIFT                       MK_SHIFT_CONST(21)
#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF0_FIELD                       MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF0_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF0_RANGE                       MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF0_ROW                 0

#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF1_SHIFT                       MK_SHIFT_CONST(22)
#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF1_FIELD                       MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF1_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF1_RANGE                       MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF1_ROW                 0

#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF2_SHIFT                       MK_SHIFT_CONST(23)
#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF2_FIELD                       MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF2_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF2_RANGE                       MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF2_ROW                 0

#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF3_SHIFT                       MK_SHIFT_CONST(24)
#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF3_FIELD                       MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF3_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF3_RANGE                       MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF3_ROW                 0

#define SLICE0_ICTLR_FIELDS_0_I2C_SHIFT                 MK_SHIFT_CONST(25)
#define SLICE0_ICTLR_FIELDS_0_I2C_FIELD                 MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C_RANGE                 MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE0_ICTLR_FIELDS_0_I2C_ROW                   0

#define SLICE0_ICTLR_FIELDS_0_I2C2_SHIFT                        MK_SHIFT_CONST(26)
#define SLICE0_ICTLR_FIELDS_0_I2C2_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C2_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C2_RANGE                        MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE0_ICTLR_FIELDS_0_I2C2_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_I2C3_SHIFT                        MK_SHIFT_CONST(27)
#define SLICE0_ICTLR_FIELDS_0_I2C3_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C3_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C3_RANGE                        MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE0_ICTLR_FIELDS_0_I2C3_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_I2C4_SHIFT                        MK_SHIFT_CONST(28)
#define SLICE0_ICTLR_FIELDS_0_I2C4_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C4_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C4_RANGE                        MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE0_ICTLR_FIELDS_0_I2C4_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_I2C5_SHIFT                        MK_SHIFT_CONST(29)
#define SLICE0_ICTLR_FIELDS_0_I2C5_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C5_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C5_RANGE                        MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE0_ICTLR_FIELDS_0_I2C5_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_I2C6_SHIFT                        MK_SHIFT_CONST(30)
#define SLICE0_ICTLR_FIELDS_0_I2C6_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C6_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C6_RANGE                        MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE0_ICTLR_FIELDS_0_I2C6_ROW                  0

#define SLICE0_ICTLR_FIELDS_0_I2C7_SHIFT                        MK_SHIFT_CONST(31)
#define SLICE0_ICTLR_FIELDS_0_I2C7_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C7_SHIFT)
#define SLICE0_ICTLR_FIELDS_0_I2C7_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE0_ICTLR_FIELDS_0_I2C7_ROW                  0


// Packet SLICE1_ICTLR_FIELDS_0
#define SLICE1_ICTLR_FIELDS_0_SIZE 32

#define SLICE1_ICTLR_FIELDS_0_I2C8_SHIFT                        MK_SHIFT_CONST(0)
#define SLICE1_ICTLR_FIELDS_0_I2C8_FIELD                        MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_I2C8_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_I2C8_RANGE                        MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE1_ICTLR_FIELDS_0_I2C8_ROW                  0

#define SLICE1_ICTLR_FIELDS_0_I2C9_SHIFT                        MK_SHIFT_CONST(1)
#define SLICE1_ICTLR_FIELDS_0_I2C9_FIELD                        MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_I2C9_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_I2C9_RANGE                        MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE1_ICTLR_FIELDS_0_I2C9_ROW                  0

#define SLICE1_ICTLR_FIELDS_0_RESERVED_34_SHIFT                 MK_SHIFT_CONST(2)
#define SLICE1_ICTLR_FIELDS_0_RESERVED_34_FIELD                 MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_RESERVED_34_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_RESERVED_34_RANGE                 MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE1_ICTLR_FIELDS_0_RESERVED_34_ROW                   0

#define SLICE1_ICTLR_FIELDS_0_QSPI0_SHIFT                       MK_SHIFT_CONST(3)
#define SLICE1_ICTLR_FIELDS_0_QSPI0_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_QSPI0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_QSPI0_RANGE                       MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE1_ICTLR_FIELDS_0_QSPI0_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_SPI1_SHIFT                        MK_SHIFT_CONST(4)
#define SLICE1_ICTLR_FIELDS_0_SPI1_FIELD                        MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SPI1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_SPI1_RANGE                        MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE1_ICTLR_FIELDS_0_SPI1_ROW                  0

#define SLICE1_ICTLR_FIELDS_0_SPI2_SHIFT                        MK_SHIFT_CONST(5)
#define SLICE1_ICTLR_FIELDS_0_SPI2_FIELD                        MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SPI2_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_SPI2_RANGE                        MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE1_ICTLR_FIELDS_0_SPI2_ROW                  0

#define SLICE1_ICTLR_FIELDS_0_SPI3_SHIFT                        MK_SHIFT_CONST(6)
#define SLICE1_ICTLR_FIELDS_0_SPI3_FIELD                        MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SPI3_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_SPI3_RANGE                        MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE1_ICTLR_FIELDS_0_SPI3_ROW                  0

#define SLICE1_ICTLR_FIELDS_0_QSPI1_SHIFT                       MK_SHIFT_CONST(7)
#define SLICE1_ICTLR_FIELDS_0_QSPI1_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_QSPI1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_QSPI1_RANGE                       MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE1_ICTLR_FIELDS_0_QSPI1_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_CAN1_0_SHIFT                      MK_SHIFT_CONST(8)
#define SLICE1_ICTLR_FIELDS_0_CAN1_0_FIELD                      MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_CAN1_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_CAN1_0_RANGE                      MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE1_ICTLR_FIELDS_0_CAN1_0_ROW                        0

#define SLICE1_ICTLR_FIELDS_0_CAN1_1_SHIFT                      MK_SHIFT_CONST(9)
#define SLICE1_ICTLR_FIELDS_0_CAN1_1_FIELD                      MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_CAN1_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_CAN1_1_RANGE                      MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE1_ICTLR_FIELDS_0_CAN1_1_ROW                        0

#define SLICE1_ICTLR_FIELDS_0_CAN2_0_SHIFT                      MK_SHIFT_CONST(10)
#define SLICE1_ICTLR_FIELDS_0_CAN2_0_FIELD                      MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_CAN2_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_CAN2_0_RANGE                      MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE1_ICTLR_FIELDS_0_CAN2_0_ROW                        0

#define SLICE1_ICTLR_FIELDS_0_CAN2_1_SHIFT                      MK_SHIFT_CONST(11)
#define SLICE1_ICTLR_FIELDS_0_CAN2_1_FIELD                      MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_CAN2_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_CAN2_1_RANGE                      MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE1_ICTLR_FIELDS_0_CAN2_1_ROW                        0

#define SLICE1_ICTLR_FIELDS_0_UFSHC_C0_SHIFT                    MK_SHIFT_CONST(12)
#define SLICE1_ICTLR_FIELDS_0_UFSHC_C0_FIELD                    MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_UFSHC_C0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_UFSHC_C0_RANGE                    MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE1_ICTLR_FIELDS_0_UFSHC_C0_ROW                      0

#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_0_SHIFT                       MK_SHIFT_CONST(13)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_0_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_0_RANGE                       MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_0_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_1_SHIFT                       MK_SHIFT_CONST(14)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_1_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_1_RANGE                       MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_1_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_0_SHIFT                       MK_SHIFT_CONST(15)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_0_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_0_RANGE                       MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_0_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_1_SHIFT                       MK_SHIFT_CONST(16)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_1_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_1_RANGE                       MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_1_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_0_SHIFT                       MK_SHIFT_CONST(17)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_0_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_0_RANGE                       MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_0_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_1_SHIFT                       MK_SHIFT_CONST(18)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_1_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_1_RANGE                       MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_1_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_0_SHIFT                       MK_SHIFT_CONST(19)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_0_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_0_RANGE                       MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_0_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_1_SHIFT                       MK_SHIFT_CONST(20)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_1_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_1_RANGE                       MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_1_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_0_SHIFT                       MK_SHIFT_CONST(21)
#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_0_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_0_RANGE                       MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_0_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_1_SHIFT                       MK_SHIFT_CONST(22)
#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_1_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_1_RANGE                       MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_1_ROW                 0

#define SLICE1_ICTLR_FIELDS_0_RESERVED_55_SHIFT                 MK_SHIFT_CONST(23)
#define SLICE1_ICTLR_FIELDS_0_RESERVED_55_FIELD                 MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_RESERVED_55_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_RESERVED_55_RANGE                 MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE1_ICTLR_FIELDS_0_RESERVED_55_ROW                   0

#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_SHIFT                  MK_SHIFT_CONST(24)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_FIELD                  MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_RANGE                  MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_ROW                    0

#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_SHIFT                  MK_SHIFT_CONST(25)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_FIELD                  MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_RANGE                  MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_ROW                    0

#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_2_SHIFT                  MK_SHIFT_CONST(26)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_2_FIELD                  MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_AON_GPIO_2_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_2_RANGE                  MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_2_ROW                    0

#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_3_SHIFT                  MK_SHIFT_CONST(27)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_3_FIELD                  MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_AON_GPIO_3_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_3_RANGE                  MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_3_ROW                    0

#define SLICE1_ICTLR_FIELDS_0_AZA_SHIFT                 MK_SHIFT_CONST(28)
#define SLICE1_ICTLR_FIELDS_0_AZA_FIELD                 MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_AZA_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_AZA_RANGE                 MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE1_ICTLR_FIELDS_0_AZA_ROW                   0

#define SLICE1_ICTLR_FIELDS_0_HDACODEC_SHIFT                    MK_SHIFT_CONST(29)
#define SLICE1_ICTLR_FIELDS_0_HDACODEC_FIELD                    MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_HDACODEC_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_HDACODEC_RANGE                    MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE1_ICTLR_FIELDS_0_HDACODEC_ROW                      0

#define SLICE1_ICTLR_FIELDS_0_SDMMC1_SHIFT                      MK_SHIFT_CONST(30)
#define SLICE1_ICTLR_FIELDS_0_SDMMC1_FIELD                      MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SDMMC1_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_SDMMC1_RANGE                      MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE1_ICTLR_FIELDS_0_SDMMC1_ROW                        0

#define SLICE1_ICTLR_FIELDS_0_SPI4_SHIFT                        MK_SHIFT_CONST(31)
#define SLICE1_ICTLR_FIELDS_0_SPI4_FIELD                        MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SPI4_SHIFT)
#define SLICE1_ICTLR_FIELDS_0_SPI4_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE1_ICTLR_FIELDS_0_SPI4_ROW                  0


// Packet SLICE2_ICTLR_FIELDS_0
#define SLICE2_ICTLR_FIELDS_0_SIZE 32

#define SLICE2_ICTLR_FIELDS_0_SPI5_SHIFT                        MK_SHIFT_CONST(0)
#define SLICE2_ICTLR_FIELDS_0_SPI5_FIELD                        MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SPI5_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_SPI5_RANGE                        MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE2_ICTLR_FIELDS_0_SPI5_ROW                  0

#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SHIFT                      MK_SHIFT_CONST(1)
#define SLICE2_ICTLR_FIELDS_0_SDMMC4_FIELD                      MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SDMMC4_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_SDMMC4_RANGE                      MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE2_ICTLR_FIELDS_0_SDMMC4_ROW                        0

#define SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_SHIFT                  MK_SHIFT_CONST(2)
#define SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_FIELD                  MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_RANGE                  MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_ROW                    0

#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_0_SHIFT                      MK_SHIFT_CONST(3)
#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_0_FIELD                      MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_0_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_0_RANGE                      MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_0_ROW                        0

#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_1_SHIFT                      MK_SHIFT_CONST(4)
#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_1_FIELD                      MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_1_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_1_RANGE                      MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_1_ROW                        0

#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_SHIFT                  MK_SHIFT_CONST(5)
#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_FIELD                  MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_RANGE                  MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_ROW                    0

#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_2_SHIFT                      MK_SHIFT_CONST(6)
#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_2_FIELD                      MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_2_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_2_RANGE                      MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_2_ROW                        0

#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_3_SHIFT                      MK_SHIFT_CONST(7)
#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_3_FIELD                      MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_3_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_3_RANGE                      MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_3_ROW                        0

#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_0_SHIFT                       MK_SHIFT_CONST(8)
#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_0_FIELD                       MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_0_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_0_RANGE                       MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_0_ROW                 0

#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_1_SHIFT                       MK_SHIFT_CONST(9)
#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_1_FIELD                       MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_1_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_1_RANGE                       MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_1_ROW                 0

#define SLICE2_ICTLR_FIELDS_0_TSC_IRQ_SHIFT                     MK_SHIFT_CONST(10)
#define SLICE2_ICTLR_FIELDS_0_TSC_IRQ_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_TSC_IRQ_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_TSC_IRQ_RANGE                     MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE2_ICTLR_FIELDS_0_TSC_IRQ_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_SHIFT                     MK_SHIFT_CONST(11)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_RANGE                     MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_SHIFT                     MK_SHIFT_CONST(12)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_RANGE                     MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_SHIFT                     MK_SHIFT_CONST(13)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_RANGE                     MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_SHIFT                     MK_SHIFT_CONST(14)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_RANGE                     MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_SHIFT                     MK_SHIFT_CONST(15)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_RANGE                     MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_SHIFT                     MK_SHIFT_CONST(16)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_RANGE                     MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_SHIFT                     MK_SHIFT_CONST(17)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_RANGE                     MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_SHIFT                     MK_SHIFT_CONST(18)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_RANGE                     MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_SHIFT                     MK_SHIFT_CONST(19)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_RANGE                     MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_SHIFT                     MK_SHIFT_CONST(20)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_RANGE                     MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_ROW                       0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_SHIFT                    MK_SHIFT_CONST(21)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_RANGE                    MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_SHIFT                    MK_SHIFT_CONST(22)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_RANGE                    MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_SHIFT                    MK_SHIFT_CONST(23)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_RANGE                    MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_SHIFT                    MK_SHIFT_CONST(24)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_RANGE                    MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_SHIFT                    MK_SHIFT_CONST(25)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_RANGE                    MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_SHIFT                    MK_SHIFT_CONST(26)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_RANGE                    MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_SHIFT                    MK_SHIFT_CONST(27)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_RANGE                    MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_SHIFT                    MK_SHIFT_CONST(28)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_RANGE                    MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_SHIFT                    MK_SHIFT_CONST(29)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_RANGE                    MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_SHIFT                    MK_SHIFT_CONST(30)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_RANGE                    MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_ROW                      0

#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_SHIFT                    MK_SHIFT_CONST(31)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_SHIFT)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_RANGE                    MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_ROW                      0


// Packet SLICE3_ICTLR_FIELDS_0
#define SLICE3_ICTLR_FIELDS_0_SIZE 32

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_SHIFT                    MK_SHIFT_CONST(0)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_RANGE                    MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_SHIFT                    MK_SHIFT_CONST(1)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_RANGE                    MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_SHIFT                    MK_SHIFT_CONST(2)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_RANGE                    MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_SHIFT                    MK_SHIFT_CONST(3)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_RANGE                    MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_SHIFT                    MK_SHIFT_CONST(4)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_RANGE                    MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_SHIFT                    MK_SHIFT_CONST(5)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_RANGE                    MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_SHIFT                    MK_SHIFT_CONST(6)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_RANGE                    MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_SHIFT                    MK_SHIFT_CONST(7)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_RANGE                    MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_SHIFT                    MK_SHIFT_CONST(8)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_RANGE                    MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_SHIFT                    MK_SHIFT_CONST(9)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_RANGE                    MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_SHIFT                    MK_SHIFT_CONST(10)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_RANGE                    MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_ROW                      0

#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_SHIFT                  MK_SHIFT_CONST(11)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_FIELD                  MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_RANGE                  MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_ROW                    0

#define SLICE3_ICTLR_FIELDS_0_PEX2_L4_P2U_SW_SHIFT                      MK_SHIFT_CONST(12)
#define SLICE3_ICTLR_FIELDS_0_PEX2_L4_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_PEX2_L4_P2U_SW_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_PEX2_L4_P2U_SW_RANGE                      MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE3_ICTLR_FIELDS_0_PEX2_L4_P2U_SW_ROW                        0

#define SLICE3_ICTLR_FIELDS_0_PEX2_L5_P2U_SW_SHIFT                      MK_SHIFT_CONST(13)
#define SLICE3_ICTLR_FIELDS_0_PEX2_L5_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_PEX2_L5_P2U_SW_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_PEX2_L5_P2U_SW_RANGE                      MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE3_ICTLR_FIELDS_0_PEX2_L5_P2U_SW_ROW                        0

#define SLICE3_ICTLR_FIELDS_0_PEX2_L6_P2U_SW_SHIFT                      MK_SHIFT_CONST(14)
#define SLICE3_ICTLR_FIELDS_0_PEX2_L6_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_PEX2_L6_P2U_SW_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_PEX2_L6_P2U_SW_RANGE                      MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE3_ICTLR_FIELDS_0_PEX2_L6_P2U_SW_ROW                        0

#define SLICE3_ICTLR_FIELDS_0_PEX2_L7_P2U_SW_SHIFT                      MK_SHIFT_CONST(15)
#define SLICE3_ICTLR_FIELDS_0_PEX2_L7_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_PEX2_L7_P2U_SW_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_PEX2_L7_P2U_SW_RANGE                      MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE3_ICTLR_FIELDS_0_PEX2_L7_P2U_SW_ROW                        0

#define SLICE3_ICTLR_FIELDS_0_UARTA_SHIFT                       MK_SHIFT_CONST(16)
#define SLICE3_ICTLR_FIELDS_0_UARTA_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTA_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_UARTA_RANGE                       MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE3_ICTLR_FIELDS_0_UARTA_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_UARTB_SHIFT                       MK_SHIFT_CONST(17)
#define SLICE3_ICTLR_FIELDS_0_UARTB_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTB_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_UARTB_RANGE                       MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE3_ICTLR_FIELDS_0_UARTB_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_UARTC_SHIFT                       MK_SHIFT_CONST(18)
#define SLICE3_ICTLR_FIELDS_0_UARTC_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTC_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_UARTC_RANGE                       MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE3_ICTLR_FIELDS_0_UARTC_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_UARTD_SHIFT                       MK_SHIFT_CONST(19)
#define SLICE3_ICTLR_FIELDS_0_UARTD_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTD_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_UARTD_RANGE                       MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE3_ICTLR_FIELDS_0_UARTD_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_UARTE_SHIFT                       MK_SHIFT_CONST(20)
#define SLICE3_ICTLR_FIELDS_0_UARTE_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTE_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_UARTE_RANGE                       MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE3_ICTLR_FIELDS_0_UARTE_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_UARTF_SHIFT                       MK_SHIFT_CONST(21)
#define SLICE3_ICTLR_FIELDS_0_UARTF_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTF_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_UARTF_RANGE                       MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE3_ICTLR_FIELDS_0_UARTF_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_RESERVED_118_SHIFT                        MK_SHIFT_CONST(22)
#define SLICE3_ICTLR_FIELDS_0_RESERVED_118_FIELD                        MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_RESERVED_118_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_RESERVED_118_RANGE                        MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE3_ICTLR_FIELDS_0_RESERVED_118_ROW                  0

#define SLICE3_ICTLR_FIELDS_0_NVCSI_SHIFT                       MK_SHIFT_CONST(23)
#define SLICE3_ICTLR_FIELDS_0_NVCSI_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_NVCSI_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_NVCSI_RANGE                       MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE3_ICTLR_FIELDS_0_NVCSI_ROW                 0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_SHIFT                   MK_SHIFT_CONST(24)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_RANGE                   MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_SHIFT                   MK_SHIFT_CONST(25)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_RANGE                   MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_SHIFT                   MK_SHIFT_CONST(26)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_RANGE                   MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_SHIFT                   MK_SHIFT_CONST(27)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_RANGE                   MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_SHIFT                   MK_SHIFT_CONST(28)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_RANGE                   MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_SHIFT                   MK_SHIFT_CONST(29)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_RANGE                   MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_SHIFT                   MK_SHIFT_CONST(30)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_RANGE                   MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_ROW                     0

#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_SHIFT                   MK_SHIFT_CONST(31)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_SHIFT)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_RANGE                   MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_ROW                     0


// Packet SLICE4_ICTLR_FIELDS_0
#define SLICE4_ICTLR_FIELDS_0_SIZE 32

#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_SHIFT                   MK_SHIFT_CONST(0)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_RANGE                   MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_SHIFT                   MK_SHIFT_CONST(1)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_RANGE                   MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_SHIFT                   MK_SHIFT_CONST(2)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_RANGE                   MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_SHIFT                   MK_SHIFT_CONST(3)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_RANGE                   MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_SHIFT                   MK_SHIFT_CONST(4)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_RANGE                   MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_SHIFT                      MK_SHIFT_CONST(5)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_RANGE                      MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_SHIFT                      MK_SHIFT_CONST(6)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_RANGE                      MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_SHIFT                      MK_SHIFT_CONST(7)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_RANGE                      MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_SHIFT                      MK_SHIFT_CONST(8)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_RANGE                      MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_SHIFT                   MK_SHIFT_CONST(9)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_RANGE                   MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_SHIFT                   MK_SHIFT_CONST(10)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_RANGE                   MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_SHIFT                   MK_SHIFT_CONST(11)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_RANGE                   MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_SHIFT                   MK_SHIFT_CONST(12)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_RANGE                   MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_ROW                     0

#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_SHIFT                      MK_SHIFT_CONST(13)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_RANGE                      MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_SHIFT                      MK_SHIFT_CONST(14)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_RANGE                      MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_SHIFT                      MK_SHIFT_CONST(15)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_RANGE                      MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_SHIFT                      MK_SHIFT_CONST(16)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_RANGE                      MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_ROW                        0

#define SLICE4_ICTLR_FIELDS_0_APE_IRQ0_SHIFT                    MK_SHIFT_CONST(17)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ0_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_IRQ0_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ0_RANGE                    MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ0_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_IRQ1_SHIFT                    MK_SHIFT_CONST(18)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ1_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_IRQ1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ1_RANGE                    MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ1_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_IRQ2_SHIFT                    MK_SHIFT_CONST(19)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ2_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_IRQ2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ2_RANGE                    MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ2_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_IRQ3_SHIFT                    MK_SHIFT_CONST(20)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ3_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_IRQ3_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ3_RANGE                    MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE4_ICTLR_FIELDS_0_APE_IRQ3_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_FIQ0_SHIFT                    MK_SHIFT_CONST(21)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ0_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_FIQ0_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ0_RANGE                    MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ0_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_FIQ1_SHIFT                    MK_SHIFT_CONST(22)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ1_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_FIQ1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ1_RANGE                    MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ1_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_FIQ2_SHIFT                    MK_SHIFT_CONST(23)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ2_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_FIQ2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ2_RANGE                    MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ2_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_APE_FIQ3_SHIFT                    MK_SHIFT_CONST(24)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ3_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_FIQ3_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ3_RANGE                    MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE4_ICTLR_FIELDS_0_APE_FIQ3_ROW                      0

#define SLICE4_ICTLR_FIELDS_0_VI2_THI_SHIFT                     MK_SHIFT_CONST(25)
#define SLICE4_ICTLR_FIELDS_0_VI2_THI_FIELD                     MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_THI_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_VI2_THI_RANGE                     MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE4_ICTLR_FIELDS_0_VI2_THI_ROW                       0

#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_0_SHIFT                  MK_SHIFT_CONST(26)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_0_FIELD                  MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_VMID_0_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_0_RANGE                  MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_0_ROW                    0

#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_1_SHIFT                  MK_SHIFT_CONST(27)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_1_FIELD                  MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_VMID_1_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_1_RANGE                  MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_1_ROW                    0

#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_2_SHIFT                  MK_SHIFT_CONST(28)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_2_FIELD                  MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_VMID_2_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_2_RANGE                  MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_2_ROW                    0

#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_3_SHIFT                  MK_SHIFT_CONST(29)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_3_FIELD                  MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_VMID_3_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_3_RANGE                  MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_3_ROW                    0

#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_4_SHIFT                  MK_SHIFT_CONST(30)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_4_FIELD                  MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_VMID_4_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_4_RANGE                  MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_4_ROW                    0

#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_5_SHIFT                  MK_SHIFT_CONST(31)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_5_FIELD                  MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_VMID_5_SHIFT)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_5_RANGE                  MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_5_ROW                    0


// Packet SLICE5_ICTLR_FIELDS_0
#define SLICE5_ICTLR_FIELDS_0_SIZE 32

#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_6_SHIFT                  MK_SHIFT_CONST(0)
#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_6_FIELD                  MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_VI2_VMID_6_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_6_RANGE                  MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_6_ROW                    0

#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_7_SHIFT                  MK_SHIFT_CONST(1)
#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_7_FIELD                  MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_VI2_VMID_7_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_7_RANGE                  MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_7_ROW                    0

#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_8_SHIFT                  MK_SHIFT_CONST(2)
#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_8_FIELD                  MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_VI2_VMID_8_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_8_RANGE                  MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_8_ROW                    0

#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_SHIFT                       MK_SHIFT_CONST(3)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_FIELD                       MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_RANGE                       MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_ROW                 0

#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_SHIFT                       MK_SHIFT_CONST(4)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_FIELD                       MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_RANGE                       MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_ROW                 0

#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_SHIFT                       MK_SHIFT_CONST(5)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_FIELD                       MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_RANGE                       MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_ROW                 0

#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_SHIFT                        MK_SHIFT_CONST(6)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_RANGE                        MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_ROW                  0

#define SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_SHIFT                 MK_SHIFT_CONST(7)
#define SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_FIELD                 MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_RANGE                 MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_ROW                   0

#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_SHIFT                        MK_SHIFT_CONST(8)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_RANGE                        MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_ROW                  0

#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_SHIFT                        MK_SHIFT_CONST(9)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_RANGE                        MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_ROW                  0

#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_SHIFT                    MK_SHIFT_CONST(10)
#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_FIELD                    MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_RANGE                    MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_ROW                      0

#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_SHIFT                     MK_SHIFT_CONST(11)
#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_FIELD                     MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_RANGE                     MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_ROW                       0

#define SLICE5_ICTLR_FIELDS_0_SECURE_AON_FABRIC_SHIFT                   MK_SHIFT_CONST(12)
#define SLICE5_ICTLR_FIELDS_0_SECURE_AON_FABRIC_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SECURE_AON_FABRIC_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_SECURE_AON_FABRIC_RANGE                   MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE5_ICTLR_FIELDS_0_SECURE_AON_FABRIC_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_SECURE_SCE_FABRIC_SHIFT                   MK_SHIFT_CONST(13)
#define SLICE5_ICTLR_FIELDS_0_SECURE_SCE_FABRIC_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SECURE_SCE_FABRIC_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_SECURE_SCE_FABRIC_RANGE                   MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE5_ICTLR_FIELDS_0_SECURE_SCE_FABRIC_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_FABRIC_SHIFT                  MK_SHIFT_CONST(14)
#define SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_FABRIC_FIELD                  MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_FABRIC_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_FABRIC_RANGE                  MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_FABRIC_ROW                    0

#define SLICE5_ICTLR_FIELDS_0_SECURE_RCE_FABRIC_SHIFT                   MK_SHIFT_CONST(15)
#define SLICE5_ICTLR_FIELDS_0_SECURE_RCE_FABRIC_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SECURE_RCE_FABRIC_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_SECURE_RCE_FABRIC_RANGE                   MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE5_ICTLR_FIELDS_0_SECURE_RCE_FABRIC_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_SHIFT                  MK_SHIFT_CONST(16)
#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_FIELD                  MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_RANGE                  MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_ROW                    0

#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_SHIFT                      MK_SHIFT_CONST(17)
#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_FIELD                      MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_RANGE                      MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_ROW                        0

#define SLICE5_ICTLR_FIELDS_0_RESERVED_178_SHIFT                        MK_SHIFT_CONST(18)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_178_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RESERVED_178_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_178_RANGE                        MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_178_ROW                  0

#define SLICE5_ICTLR_FIELDS_0_RESERVED_179_SHIFT                        MK_SHIFT_CONST(19)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_179_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RESERVED_179_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_179_RANGE                        MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_179_ROW                  0

#define SLICE5_ICTLR_FIELDS_0_RESERVED_180_SHIFT                        MK_SHIFT_CONST(20)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_180_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RESERVED_180_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_180_RANGE                        MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_180_ROW                  0

#define SLICE5_ICTLR_FIELDS_0_RESERVED_181_SHIFT                        MK_SHIFT_CONST(21)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_181_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RESERVED_181_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_181_RANGE                        MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE5_ICTLR_FIELDS_0_RESERVED_181_ROW                  0

#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_0_SHIFT                      MK_SHIFT_CONST(22)
#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_0_FIELD                      MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_0_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_0_RANGE                      MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_0_ROW                        0

#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_1_SHIFT                      MK_SHIFT_CONST(23)
#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_1_FIELD                      MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_1_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_1_RANGE                      MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_1_ROW                        0

#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_2_SHIFT                      MK_SHIFT_CONST(24)
#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_2_FIELD                      MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_2_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_2_RANGE                      MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_2_ROW                        0

#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_3_SHIFT                      MK_SHIFT_CONST(25)
#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_3_FIELD                      MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_3_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_3_RANGE                      MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_3_ROW                        0

#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_0_SHIFT                   MK_SHIFT_CONST(26)
#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_0_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_VM_0_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_0_RANGE                   MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_0_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_1_SHIFT                   MK_SHIFT_CONST(27)
#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_1_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_VM_1_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_1_RANGE                   MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_1_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_2_SHIFT                   MK_SHIFT_CONST(28)
#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_2_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_VM_2_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_2_RANGE                   MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_2_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_3_SHIFT                   MK_SHIFT_CONST(29)
#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_3_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_VM_3_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_3_RANGE                   MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_3_ROW                     0

#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_NON_SECURE_SHIFT                      MK_SHIFT_CONST(30)
#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_NON_SECURE_FIELD                      MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_NON_SECURE_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_NON_SECURE_RANGE                      MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_NON_SECURE_ROW                        0

#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_SECURE_SHIFT                  MK_SHIFT_CONST(31)
#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_SECURE_FIELD                  MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_SECURE_SHIFT)
#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_SECURE_RANGE                  MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_SECURE_ROW                    0


// Packet SLICE6_ICTLR_FIELDS_0
#define SLICE6_ICTLR_FIELDS_0_SIZE 32

#define SLICE6_ICTLR_FIELDS_0_TACH0_SHIFT                       MK_SHIFT_CONST(0)
#define SLICE6_ICTLR_FIELDS_0_TACH0_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_TACH0_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_TACH0_RANGE                       MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE6_ICTLR_FIELDS_0_TACH0_ROW                 0

#define SLICE6_ICTLR_FIELDS_0_TACH1_SHIFT                       MK_SHIFT_CONST(1)
#define SLICE6_ICTLR_FIELDS_0_TACH1_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_TACH1_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_TACH1_RANGE                       MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE6_ICTLR_FIELDS_0_TACH1_ROW                 0

#define SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_SHIFT                 MK_SHIFT_CONST(2)
#define SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_FIELD                 MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_RANGE                 MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_ROW                   0

#define SLICE6_ICTLR_FIELDS_0_I2S7_SHIFT                        MK_SHIFT_CONST(3)
#define SLICE6_ICTLR_FIELDS_0_I2S7_FIELD                        MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_I2S7_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_I2S7_RANGE                        MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE6_ICTLR_FIELDS_0_I2S7_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_I2S8_SHIFT                        MK_SHIFT_CONST(4)
#define SLICE6_ICTLR_FIELDS_0_I2S8_FIELD                        MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_I2S8_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_I2S8_RANGE                        MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE6_ICTLR_FIELDS_0_I2S8_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_NVJPG1_SHIFT                      MK_SHIFT_CONST(5)
#define SLICE6_ICTLR_FIELDS_0_NVJPG1_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_NVJPG1_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_NVJPG1_RANGE                      MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE6_ICTLR_FIELDS_0_NVJPG1_ROW                        0

#define SLICE6_ICTLR_FIELDS_0_NVJPG_SHIFT                       MK_SHIFT_CONST(6)
#define SLICE6_ICTLR_FIELDS_0_NVJPG_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_NVJPG_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_NVJPG_RANGE                       MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE6_ICTLR_FIELDS_0_NVJPG_ROW                 0

#define SLICE6_ICTLR_FIELDS_0_NVDEC_SHIFT                       MK_SHIFT_CONST(7)
#define SLICE6_ICTLR_FIELDS_0_NVDEC_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_NVDEC_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_NVDEC_RANGE                       MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE6_ICTLR_FIELDS_0_NVDEC_ROW                 0

#define SLICE6_ICTLR_FIELDS_0_NVENC_SHIFT                       MK_SHIFT_CONST(8)
#define SLICE6_ICTLR_FIELDS_0_NVENC_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_NVENC_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_NVENC_RANGE                       MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE6_ICTLR_FIELDS_0_NVENC_ROW                 0

#define SLICE6_ICTLR_FIELDS_0_VI_THI_SHIFT                      MK_SHIFT_CONST(9)
#define SLICE6_ICTLR_FIELDS_0_VI_THI_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_VI_THI_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_VI_THI_RANGE                      MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE6_ICTLR_FIELDS_0_VI_THI_ROW                        0

#define SLICE6_ICTLR_FIELDS_0_RESERVED_202_SHIFT                        MK_SHIFT_CONST(10)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_202_FIELD                        MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_RESERVED_202_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_202_RANGE                        MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE6_ICTLR_FIELDS_0_RESERVED_202_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_PEX2_L0_P2U_SW_SHIFT                      MK_SHIFT_CONST(11)
#define SLICE6_ICTLR_FIELDS_0_PEX2_L0_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PEX2_L0_P2U_SW_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_PEX2_L0_P2U_SW_RANGE                      MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE6_ICTLR_FIELDS_0_PEX2_L0_P2U_SW_ROW                        0

#define SLICE6_ICTLR_FIELDS_0_ISP_1_SHIFT                       MK_SHIFT_CONST(12)
#define SLICE6_ICTLR_FIELDS_0_ISP_1_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_ISP_1_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_ISP_1_RANGE                       MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE6_ICTLR_FIELDS_0_ISP_1_ROW                 0

#define SLICE6_ICTLR_FIELDS_0_ISP_SHIFT                 MK_SHIFT_CONST(13)
#define SLICE6_ICTLR_FIELDS_0_ISP_FIELD                 MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_ISP_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_ISP_RANGE                 MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE6_ICTLR_FIELDS_0_ISP_ROW                   0

#define SLICE6_ICTLR_FIELDS_0_VIC_SHIFT                 MK_SHIFT_CONST(14)
#define SLICE6_ICTLR_FIELDS_0_VIC_FIELD                 MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_VIC_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_VIC_RANGE                 MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE6_ICTLR_FIELDS_0_VIC_ROW                   0

#define SLICE6_ICTLR_FIELDS_0_UARTH_SHIFT                       MK_SHIFT_CONST(15)
#define SLICE6_ICTLR_FIELDS_0_UARTH_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_UARTH_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_UARTH_RANGE                       MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE6_ICTLR_FIELDS_0_UARTH_ROW                 0

#define SLICE6_ICTLR_FIELDS_0_CVC_SHIFT                 MK_SHIFT_CONST(16)
#define SLICE6_ICTLR_FIELDS_0_CVC_FIELD                 MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_CVC_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_CVC_RANGE                 MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE6_ICTLR_FIELDS_0_CVC_ROW                   0

#define SLICE6_ICTLR_FIELDS_0_PMIC_EXT_SHIFT                    MK_SHIFT_CONST(17)
#define SLICE6_ICTLR_FIELDS_0_PMIC_EXT_FIELD                    MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PMIC_EXT_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_PMIC_EXT_RANGE                    MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE6_ICTLR_FIELDS_0_PMIC_EXT_ROW                      0

#define SLICE6_ICTLR_FIELDS_0_ACTMON_SHIFT                      MK_SHIFT_CONST(18)
#define SLICE6_ICTLR_FIELDS_0_ACTMON_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_ACTMON_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_ACTMON_RANGE                      MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE6_ICTLR_FIELDS_0_ACTMON_ROW                        0

#define SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_SHIFT                        MK_SHIFT_CONST(19)
#define SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_FIELD                        MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_RANGE                        MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_SHIFT                  MK_SHIFT_CONST(20)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_FIELD                  MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_RANGE                  MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_ROW                    0

#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_SHIFT                  MK_SHIFT_CONST(21)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_FIELD                  MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_RANGE                  MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_ROW                    0

#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_SHIFT                  MK_SHIFT_CONST(22)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_FIELD                  MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_RANGE                  MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_ROW                    0

#define SLICE6_ICTLR_FIELDS_0_OFA0_SHIFT                        MK_SHIFT_CONST(23)
#define SLICE6_ICTLR_FIELDS_0_OFA0_FIELD                        MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_OFA0_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_OFA0_RANGE                        MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE6_ICTLR_FIELDS_0_OFA0_ROW                  0

#define SLICE6_ICTLR_FIELDS_0_AON_PM_SHIFT                      MK_SHIFT_CONST(24)
#define SLICE6_ICTLR_FIELDS_0_AON_PM_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_AON_PM_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_AON_PM_RANGE                      MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE6_ICTLR_FIELDS_0_AON_PM_ROW                        0

#define SLICE6_ICTLR_FIELDS_0_DFD_0_SHIFT                       MK_SHIFT_CONST(25)
#define SLICE6_ICTLR_FIELDS_0_DFD_0_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_DFD_0_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_DFD_0_RANGE                       MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE6_ICTLR_FIELDS_0_DFD_0_ROW                 0

#define SLICE6_ICTLR_FIELDS_0_THERMAL_SHIFT                     MK_SHIFT_CONST(26)
#define SLICE6_ICTLR_FIELDS_0_THERMAL_FIELD                     MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_THERMAL_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_THERMAL_RANGE                     MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE6_ICTLR_FIELDS_0_THERMAL_ROW                       0

#define SLICE6_ICTLR_FIELDS_0_EDP_SHIFT                 MK_SHIFT_CONST(27)
#define SLICE6_ICTLR_FIELDS_0_EDP_FIELD                 MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_EDP_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_EDP_RANGE                 MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE6_ICTLR_FIELDS_0_EDP_ROW                   0

#define SLICE6_ICTLR_FIELDS_0_PEX2_L1_P2U_SW_SHIFT                      MK_SHIFT_CONST(28)
#define SLICE6_ICTLR_FIELDS_0_PEX2_L1_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PEX2_L1_P2U_SW_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_PEX2_L1_P2U_SW_RANGE                      MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE6_ICTLR_FIELDS_0_PEX2_L1_P2U_SW_ROW                        0

#define SLICE6_ICTLR_FIELDS_0_PEX2_L2_P2U_SW_SHIFT                      MK_SHIFT_CONST(29)
#define SLICE6_ICTLR_FIELDS_0_PEX2_L2_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PEX2_L2_P2U_SW_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_PEX2_L2_P2U_SW_RANGE                      MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE6_ICTLR_FIELDS_0_PEX2_L2_P2U_SW_ROW                        0

#define SLICE6_ICTLR_FIELDS_0_PEX2_L3_P2U_SW_SHIFT                      MK_SHIFT_CONST(30)
#define SLICE6_ICTLR_FIELDS_0_PEX2_L3_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PEX2_L3_P2U_SW_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_PEX2_L3_P2U_SW_RANGE                      MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE6_ICTLR_FIELDS_0_PEX2_L3_P2U_SW_ROW                        0

#define SLICE6_ICTLR_FIELDS_0_MC_SHIFT                  MK_SHIFT_CONST(31)
#define SLICE6_ICTLR_FIELDS_0_MC_FIELD                  MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_MC_SHIFT)
#define SLICE6_ICTLR_FIELDS_0_MC_RANGE                  MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE6_ICTLR_FIELDS_0_MC_ROW                    0


// Packet SLICE7_ICTLR_FIELDS_0
#define SLICE7_ICTLR_FIELDS_0_SIZE 32

#define SLICE7_ICTLR_FIELDS_0_EMC_SHIFT                 MK_SHIFT_CONST(0)
#define SLICE7_ICTLR_FIELDS_0_EMC_FIELD                 MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_EMC_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_EMC_RANGE                 MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE7_ICTLR_FIELDS_0_EMC_ROW                   0

#define SLICE7_ICTLR_FIELDS_0_RESERVED_225_SHIFT                        MK_SHIFT_CONST(1)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_225_FIELD                        MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_RESERVED_225_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_225_RANGE                        MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_225_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_AON_CAR_SHIFT                     MK_SHIFT_CONST(2)
#define SLICE7_ICTLR_FIELDS_0_AON_CAR_FIELD                     MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_AON_CAR_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_AON_CAR_RANGE                     MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE7_ICTLR_FIELDS_0_AON_CAR_ROW                       0

#define SLICE7_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_SHIFT                    MK_SHIFT_CONST(3)
#define SLICE7_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_FIELD                    MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_RANGE                    MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE7_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_ROW                      0

#define SLICE7_ICTLR_FIELDS_0_TSEC_SHIFT                        MK_SHIFT_CONST(4)
#define SLICE7_ICTLR_FIELDS_0_TSEC_FIELD                        MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TSEC_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TSEC_RANGE                        MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE7_ICTLR_FIELDS_0_TSEC_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_RESERVED_229_SHIFT                        MK_SHIFT_CONST(5)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_229_FIELD                        MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_RESERVED_229_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_229_RANGE                        MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_229_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_RESERVED_230_SHIFT                        MK_SHIFT_CONST(6)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_230_FIELD                        MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_RESERVED_230_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_230_RANGE                        MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_230_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_CBB_SECURE_SHIFT                  MK_SHIFT_CONST(7)
#define SLICE7_ICTLR_FIELDS_0_CBB_SECURE_FIELD                  MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_CBB_SECURE_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_CBB_SECURE_RANGE                  MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE7_ICTLR_FIELDS_0_CBB_SECURE_ROW                    0

#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_NS_SHIFT                   MK_SHIFT_CONST(8)
#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_NS_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_NS_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_NS_RANGE                   MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_NS_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_S_SHIFT                    MK_SHIFT_CONST(9)
#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_S_FIELD                    MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_S_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_S_RANGE                    MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_S_ROW                      0

#define SLICE7_ICTLR_FIELDS_0_PVA0_SHIFT                        MK_SHIFT_CONST(10)
#define SLICE7_ICTLR_FIELDS_0_PVA0_FIELD                        MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_PVA0_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_PVA0_RANGE                        MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE7_ICTLR_FIELDS_0_PVA0_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_RESERVED_235_SHIFT                        MK_SHIFT_CONST(11)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_235_FIELD                        MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_RESERVED_235_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_235_RANGE                        MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE7_ICTLR_FIELDS_0_RESERVED_235_ROW                  0

#define SLICE7_ICTLR_FIELDS_0_NVDLA0_SHIFT                      MK_SHIFT_CONST(12)
#define SLICE7_ICTLR_FIELDS_0_NVDLA0_FIELD                      MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_NVDLA0_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_NVDLA0_RANGE                      MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE7_ICTLR_FIELDS_0_NVDLA0_ROW                        0

#define SLICE7_ICTLR_FIELDS_0_NVDLA1_SHIFT                      MK_SHIFT_CONST(13)
#define SLICE7_ICTLR_FIELDS_0_NVDLA1_FIELD                      MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_NVDLA1_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_NVDLA1_RANGE                      MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE7_ICTLR_FIELDS_0_NVDLA1_ROW                        0

#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_NS_SHIFT                   MK_SHIFT_CONST(14)
#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_NS_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_NS_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_NS_RANGE                   MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_NS_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_S_SHIFT                    MK_SHIFT_CONST(15)
#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_S_FIELD                    MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_S_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_S_RANGE                    MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_S_ROW                      0

#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_NS_SHIFT                   MK_SHIFT_CONST(16)
#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_NS_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_NS_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_NS_RANGE                   MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_NS_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_S_SHIFT                    MK_SHIFT_CONST(17)
#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_S_FIELD                    MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_S_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_S_RANGE                    MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_S_ROW                      0

#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_NS_SHIFT                   MK_SHIFT_CONST(18)
#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_NS_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_NS_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_NS_RANGE                   MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_NS_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_S_SHIFT                    MK_SHIFT_CONST(19)
#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_S_FIELD                    MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_S_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_S_RANGE                    MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_S_ROW                      0

#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_5_SHIFT                   MK_SHIFT_CONST(20)
#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_5_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_5_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_5_RANGE                   MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_5_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_6_SHIFT                   MK_SHIFT_CONST(21)
#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_6_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_6_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_6_RANGE                   MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_6_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_7_SHIFT                   MK_SHIFT_CONST(22)
#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_7_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_7_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_7_RANGE                   MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_7_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_VI_VMID_0_SHIFT                   MK_SHIFT_CONST(23)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_0_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_0_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_0_RANGE                   MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_0_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_VI_VMID_1_SHIFT                   MK_SHIFT_CONST(24)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_1_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_1_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_1_RANGE                   MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_1_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_VI_VMID_2_SHIFT                   MK_SHIFT_CONST(25)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_2_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_2_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_2_RANGE                   MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_2_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_VI_VMID_3_SHIFT                   MK_SHIFT_CONST(26)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_3_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_3_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_3_RANGE                   MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_3_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_VI_VMID_4_SHIFT                   MK_SHIFT_CONST(27)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_4_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_4_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_4_RANGE                   MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_4_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_VI_VMID_5_SHIFT                   MK_SHIFT_CONST(28)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_5_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_5_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_5_RANGE                   MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_5_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_VI_VMID_6_SHIFT                   MK_SHIFT_CONST(29)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_6_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_6_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_6_RANGE                   MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_6_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_VI_VMID_7_SHIFT                   MK_SHIFT_CONST(30)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_7_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_7_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_7_RANGE                   MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_7_ROW                     0

#define SLICE7_ICTLR_FIELDS_0_VI_VMID_8_SHIFT                   MK_SHIFT_CONST(31)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_8_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_8_SHIFT)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_8_RANGE                   MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE7_ICTLR_FIELDS_0_VI_VMID_8_ROW                     0


// Packet SLICE8_ICTLR_FIELDS_0
#define SLICE8_ICTLR_FIELDS_0_SIZE 32

#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_10_SHIFT                   MK_SHIFT_CONST(0)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_10_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_10_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_10_RANGE                   MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_10_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_11_SHIFT                   MK_SHIFT_CONST(1)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_11_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_11_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_11_RANGE                   MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_11_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_12_SHIFT                   MK_SHIFT_CONST(2)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_12_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_12_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_12_RANGE                   MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_12_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_13_SHIFT                   MK_SHIFT_CONST(3)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_13_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_13_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_13_RANGE                   MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_13_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_14_SHIFT                   MK_SHIFT_CONST(4)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_14_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_14_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_14_RANGE                   MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_14_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_15_SHIFT                   MK_SHIFT_CONST(5)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_15_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_15_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_15_RANGE                   MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_15_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_RESERVED_262_SHIFT                        MK_SHIFT_CONST(6)
#define SLICE8_ICTLR_FIELDS_0_RESERVED_262_FIELD                        MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_RESERVED_262_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_RESERVED_262_RANGE                        MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE8_ICTLR_FIELDS_0_RESERVED_262_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_SHIFT                      MK_SHIFT_CONST(7)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_FIELD                      MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_RANGE                      MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_ROW                        0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_SHIFT                   MK_SHIFT_CONST(8)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_RANGE                   MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_0_SHIFT                   MK_SHIFT_CONST(9)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_0_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_0_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_0_RANGE                   MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_0_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_1_SHIFT                   MK_SHIFT_CONST(10)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_1_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_1_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_1_RANGE                   MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_1_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_2_SHIFT                   MK_SHIFT_CONST(11)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_2_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_2_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_2_RANGE                   MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_2_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_3_SHIFT                   MK_SHIFT_CONST(12)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_3_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_3_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_3_RANGE                   MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_3_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_4_SHIFT                   MK_SHIFT_CONST(13)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_4_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_4_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_4_RANGE                   MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_4_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_5_SHIFT                   MK_SHIFT_CONST(14)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_5_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_5_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_5_RANGE                   MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_5_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_6_SHIFT                   MK_SHIFT_CONST(15)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_6_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_6_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_6_RANGE                   MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_6_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_7_SHIFT                   MK_SHIFT_CONST(16)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_7_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_7_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_7_RANGE                   MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_7_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_SHIFT                   MK_SHIFT_CONST(17)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_RANGE                   MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_SHIFT                        MK_SHIFT_CONST(18)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_FIELD                        MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_RANGE                        MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_SHIFT                     MK_SHIFT_CONST(19)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_FIELD                     MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_RANGE                     MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_ROW                       0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_SHIFT                  MK_SHIFT_CONST(20)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_FIELD                  MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_RANGE                  MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_ROW                    0

#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_SHIFT                  MK_SHIFT_CONST(21)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_FIELD                  MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_RANGE                  MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_ROW                    0

#define SLICE8_ICTLR_FIELDS_0_RESERVED_278_SHIFT                        MK_SHIFT_CONST(22)
#define SLICE8_ICTLR_FIELDS_0_RESERVED_278_FIELD                        MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_RESERVED_278_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_RESERVED_278_RANGE                        MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE8_ICTLR_FIELDS_0_RESERVED_278_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_CEC_SHIFT                 MK_SHIFT_CONST(23)
#define SLICE8_ICTLR_FIELDS_0_CEC_FIELD                 MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_CEC_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_CEC_RANGE                 MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE8_ICTLR_FIELDS_0_CEC_ROW                   0

#define SLICE8_ICTLR_FIELDS_0_VFMON_INTR_SHIFT                  MK_SHIFT_CONST(24)
#define SLICE8_ICTLR_FIELDS_0_VFMON_INTR_FIELD                  MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_VFMON_INTR_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_VFMON_INTR_RANGE                  MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE8_ICTLR_FIELDS_0_VFMON_INTR_ROW                    0

#define SLICE8_ICTLR_FIELDS_0_SE_APB_SHIFT                      MK_SHIFT_CONST(25)
#define SLICE8_ICTLR_FIELDS_0_SE_APB_FIELD                      MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SE_APB_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_SE_APB_RANGE                      MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE8_ICTLR_FIELDS_0_SE_APB_ROW                        0

#define SLICE8_ICTLR_FIELDS_0_SE_HOST1X_SHIFT                   MK_SHIFT_CONST(26)
#define SLICE8_ICTLR_FIELDS_0_SE_HOST1X_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SE_HOST1X_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_SE_HOST1X_RANGE                   MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE8_ICTLR_FIELDS_0_SE_HOST1X_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_RESERVED_283_SHIFT                        MK_SHIFT_CONST(27)
#define SLICE8_ICTLR_FIELDS_0_RESERVED_283_FIELD                        MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_RESERVED_283_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_RESERVED_283_RANGE                        MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE8_ICTLR_FIELDS_0_RESERVED_283_ROW                  0

#define SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_SHIFT                   MK_SHIFT_CONST(28)
#define SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_RANGE                   MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_ROW                     0

#define SLICE8_ICTLR_FIELDS_0_UARTI_SHIFT                       MK_SHIFT_CONST(29)
#define SLICE8_ICTLR_FIELDS_0_UARTI_FIELD                       MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_UARTI_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_UARTI_RANGE                       MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE8_ICTLR_FIELDS_0_UARTI_ROW                 0

#define SLICE8_ICTLR_FIELDS_0_UARTJ_SHIFT                       MK_SHIFT_CONST(30)
#define SLICE8_ICTLR_FIELDS_0_UARTJ_FIELD                       MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_UARTJ_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_UARTJ_RANGE                       MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE8_ICTLR_FIELDS_0_UARTJ_ROW                 0

#define SLICE8_ICTLR_FIELDS_0_RESERVED_287_SHIFT                        MK_SHIFT_CONST(31)
#define SLICE8_ICTLR_FIELDS_0_RESERVED_287_FIELD                        MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_RESERVED_287_SHIFT)
#define SLICE8_ICTLR_FIELDS_0_RESERVED_287_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE8_ICTLR_FIELDS_0_RESERVED_287_ROW                  0


// Packet SLICE9_ICTLR_FIELDS_0
#define SLICE9_ICTLR_FIELDS_0_SIZE 32

#define SLICE9_ICTLR_FIELDS_0_GPIO0_0_SHIFT                     MK_SHIFT_CONST(0)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_0_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_0_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_0_RANGE                     MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_0_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO0_1_SHIFT                     MK_SHIFT_CONST(1)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_1_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_1_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_1_RANGE                     MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_1_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO0_2_SHIFT                     MK_SHIFT_CONST(2)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_2_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_2_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_2_RANGE                     MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_2_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO0_3_SHIFT                     MK_SHIFT_CONST(3)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_3_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_3_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_3_RANGE                     MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_3_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO0_4_SHIFT                     MK_SHIFT_CONST(4)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_4_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_4_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_4_RANGE                     MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_4_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO0_5_SHIFT                     MK_SHIFT_CONST(5)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_5_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_5_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_5_RANGE                     MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_5_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO0_6_SHIFT                     MK_SHIFT_CONST(6)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_6_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_6_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_6_RANGE                     MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_6_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO0_7_SHIFT                     MK_SHIFT_CONST(7)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_7_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_7_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_7_RANGE                     MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE9_ICTLR_FIELDS_0_GPIO0_7_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO1_0_SHIFT                     MK_SHIFT_CONST(8)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_0_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_0_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_0_RANGE                     MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_0_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO1_1_SHIFT                     MK_SHIFT_CONST(9)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_1_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_1_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_1_RANGE                     MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_1_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO1_2_SHIFT                     MK_SHIFT_CONST(10)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_2_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_2_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_2_RANGE                     MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_2_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO1_3_SHIFT                     MK_SHIFT_CONST(11)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_3_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_3_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_3_RANGE                     MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_3_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO1_4_SHIFT                     MK_SHIFT_CONST(12)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_4_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_4_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_4_RANGE                     MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_4_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO1_5_SHIFT                     MK_SHIFT_CONST(13)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_5_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_5_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_5_RANGE                     MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_5_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO1_6_SHIFT                     MK_SHIFT_CONST(14)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_6_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_6_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_6_RANGE                     MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_6_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO1_7_SHIFT                     MK_SHIFT_CONST(15)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_7_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_7_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_7_RANGE                     MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE9_ICTLR_FIELDS_0_GPIO1_7_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO2_0_SHIFT                     MK_SHIFT_CONST(16)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_0_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_0_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_0_RANGE                     MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_0_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO2_1_SHIFT                     MK_SHIFT_CONST(17)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_1_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_1_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_1_RANGE                     MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_1_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO2_2_SHIFT                     MK_SHIFT_CONST(18)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_2_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_2_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_2_RANGE                     MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_2_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO2_3_SHIFT                     MK_SHIFT_CONST(19)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_3_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_3_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_3_RANGE                     MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_3_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO2_4_SHIFT                     MK_SHIFT_CONST(20)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_4_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_4_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_4_RANGE                     MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_4_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO2_5_SHIFT                     MK_SHIFT_CONST(21)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_5_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_5_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_5_RANGE                     MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_5_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO2_6_SHIFT                     MK_SHIFT_CONST(22)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_6_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_6_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_6_RANGE                     MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_6_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO2_7_SHIFT                     MK_SHIFT_CONST(23)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_7_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_7_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_7_RANGE                     MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE9_ICTLR_FIELDS_0_GPIO2_7_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO3_0_SHIFT                     MK_SHIFT_CONST(24)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_0_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_0_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_0_RANGE                     MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_0_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO3_1_SHIFT                     MK_SHIFT_CONST(25)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_1_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_1_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_1_RANGE                     MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_1_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO3_2_SHIFT                     MK_SHIFT_CONST(26)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_2_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_2_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_2_RANGE                     MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_2_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO3_3_SHIFT                     MK_SHIFT_CONST(27)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_3_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_3_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_3_RANGE                     MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_3_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO3_4_SHIFT                     MK_SHIFT_CONST(28)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_4_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_4_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_4_RANGE                     MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_4_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO3_5_SHIFT                     MK_SHIFT_CONST(29)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_5_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_5_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_5_RANGE                     MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_5_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO3_6_SHIFT                     MK_SHIFT_CONST(30)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_6_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_6_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_6_RANGE                     MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_6_ROW                       0

#define SLICE9_ICTLR_FIELDS_0_GPIO3_7_SHIFT                     MK_SHIFT_CONST(31)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_7_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_7_SHIFT)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_7_RANGE                     MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE9_ICTLR_FIELDS_0_GPIO3_7_ROW                       0


// Packet SLICE10_ICTLR_FIELDS_0
#define SLICE10_ICTLR_FIELDS_0_SIZE 32

#define SLICE10_ICTLR_FIELDS_0_GPIO4_0_SHIFT                    MK_SHIFT_CONST(0)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_0_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_0_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_0_RANGE                    MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_0_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO4_1_SHIFT                    MK_SHIFT_CONST(1)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_1_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_1_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_1_RANGE                    MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_1_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO4_2_SHIFT                    MK_SHIFT_CONST(2)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_2_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_2_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_2_RANGE                    MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_2_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO4_3_SHIFT                    MK_SHIFT_CONST(3)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_3_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_3_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_3_RANGE                    MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_3_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO4_4_SHIFT                    MK_SHIFT_CONST(4)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_4_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_4_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_4_RANGE                    MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_4_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO4_5_SHIFT                    MK_SHIFT_CONST(5)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_5_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_5_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_5_RANGE                    MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_5_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO4_6_SHIFT                    MK_SHIFT_CONST(6)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_6_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_6_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_6_RANGE                    MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_6_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO4_7_SHIFT                    MK_SHIFT_CONST(7)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_7_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_7_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_7_RANGE                    MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE10_ICTLR_FIELDS_0_GPIO4_7_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO5_0_SHIFT                    MK_SHIFT_CONST(8)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_0_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_0_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_0_RANGE                    MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_0_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO5_1_SHIFT                    MK_SHIFT_CONST(9)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_1_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_1_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_1_RANGE                    MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_1_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO5_2_SHIFT                    MK_SHIFT_CONST(10)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_2_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_2_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_2_RANGE                    MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_2_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO5_3_SHIFT                    MK_SHIFT_CONST(11)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_3_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_3_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_3_RANGE                    MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_3_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO5_4_SHIFT                    MK_SHIFT_CONST(12)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_4_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_4_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_4_RANGE                    MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_4_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO5_5_SHIFT                    MK_SHIFT_CONST(13)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_5_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_5_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_5_RANGE                    MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_5_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO5_6_SHIFT                    MK_SHIFT_CONST(14)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_6_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_6_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_6_RANGE                    MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_6_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_GPIO5_7_SHIFT                    MK_SHIFT_CONST(15)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_7_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_7_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_7_RANGE                    MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE10_ICTLR_FIELDS_0_GPIO5_7_ROW                      0

#define SLICE10_ICTLR_FIELDS_0_PEX0_L0_P2U_SW_SHIFT                     MK_SHIFT_CONST(16)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L0_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L0_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L0_P2U_SW_RANGE                     MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L0_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX0_L1_P2U_SW_SHIFT                     MK_SHIFT_CONST(17)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L1_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L1_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L1_P2U_SW_RANGE                     MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L1_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX0_L2_P2U_SW_SHIFT                     MK_SHIFT_CONST(18)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L2_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L2_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L2_P2U_SW_RANGE                     MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L2_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX0_L3_P2U_SW_SHIFT                     MK_SHIFT_CONST(19)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L3_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L3_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L3_P2U_SW_RANGE                     MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L3_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX0_L4_P2U_SW_SHIFT                     MK_SHIFT_CONST(20)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L4_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L4_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L4_P2U_SW_RANGE                     MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L4_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX0_L5_P2U_SW_SHIFT                     MK_SHIFT_CONST(21)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L5_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L5_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L5_P2U_SW_RANGE                     MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L5_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX0_L6_P2U_SW_SHIFT                     MK_SHIFT_CONST(22)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L6_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L6_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L6_P2U_SW_RANGE                     MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L6_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX0_L7_P2U_SW_SHIFT                     MK_SHIFT_CONST(23)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L7_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L7_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L7_P2U_SW_RANGE                     MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE10_ICTLR_FIELDS_0_PEX0_L7_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX1_L0_P2U_SW_SHIFT                     MK_SHIFT_CONST(24)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L0_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L0_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L0_P2U_SW_RANGE                     MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L0_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX1_L1_P2U_SW_SHIFT                     MK_SHIFT_CONST(25)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L1_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L1_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L1_P2U_SW_RANGE                     MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L1_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX1_L2_P2U_SW_SHIFT                     MK_SHIFT_CONST(26)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L2_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L2_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L2_P2U_SW_RANGE                     MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L2_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX1_L3_P2U_SW_SHIFT                     MK_SHIFT_CONST(27)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L3_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L3_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L3_P2U_SW_RANGE                     MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L3_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX1_L4_P2U_SW_SHIFT                     MK_SHIFT_CONST(28)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L4_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L4_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L4_P2U_SW_RANGE                     MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L4_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX1_L5_P2U_SW_SHIFT                     MK_SHIFT_CONST(29)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L5_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L5_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L5_P2U_SW_RANGE                     MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L5_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX1_L6_P2U_SW_SHIFT                     MK_SHIFT_CONST(30)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L6_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L6_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L6_P2U_SW_RANGE                     MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L6_P2U_SW_ROW                       0

#define SLICE10_ICTLR_FIELDS_0_PEX1_L7_P2U_SW_SHIFT                     MK_SHIFT_CONST(31)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L7_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L7_P2U_SW_SHIFT)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L7_P2U_SW_RANGE                     MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE10_ICTLR_FIELDS_0_PEX1_L7_P2U_SW_ROW                       0


// Packet SLICE11_ICTLR_FIELDS_0
#define SLICE11_ICTLR_FIELDS_0_SIZE 32

#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_0_SHIFT                      MK_SHIFT_CONST(0)
#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_0_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_0_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_0_RANGE                      MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_0_ROW                        0

#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_1_SHIFT                      MK_SHIFT_CONST(1)
#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_1_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_1_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_1_RANGE                      MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_1_ROW                        0

#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_0_SHIFT                      MK_SHIFT_CONST(2)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_0_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_0_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_0_RANGE                      MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_0_ROW                        0

#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_1_SHIFT                      MK_SHIFT_CONST(3)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_1_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_1_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_1_RANGE                      MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_1_ROW                        0

#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_0_SHIFT                      MK_SHIFT_CONST(4)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_0_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_0_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_0_RANGE                      MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_0_ROW                        0

#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_1_SHIFT                      MK_SHIFT_CONST(5)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_1_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_1_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_1_RANGE                      MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_1_ROW                        0

#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_0_SHIFT                      MK_SHIFT_CONST(6)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_0_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_0_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_0_RANGE                      MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_0_ROW                        0

#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_1_SHIFT                      MK_SHIFT_CONST(7)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_1_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_1_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_1_RANGE                      MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_1_ROW                        0

#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_0_SHIFT                     MK_SHIFT_CONST(8)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_0_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_0_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_0_RANGE                     MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_0_ROW                       0

#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_1_SHIFT                     MK_SHIFT_CONST(9)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_1_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_1_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_1_RANGE                     MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_1_ROW                       0

#define SLICE11_ICTLR_FIELDS_0_PSC_MB0_SHIFT                    MK_SHIFT_CONST(10)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB0_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB0_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB0_RANGE                    MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB0_ROW                      0

#define SLICE11_ICTLR_FIELDS_0_PSC_MB1_SHIFT                    MK_SHIFT_CONST(11)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB1_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB1_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB1_RANGE                    MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB1_ROW                      0

#define SLICE11_ICTLR_FIELDS_0_PSC_MB2_SHIFT                    MK_SHIFT_CONST(12)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB2_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB2_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB2_RANGE                    MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB2_ROW                      0

#define SLICE11_ICTLR_FIELDS_0_PSC_MB3_SHIFT                    MK_SHIFT_CONST(13)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB3_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB3_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB3_RANGE                    MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB3_ROW                      0

#define SLICE11_ICTLR_FIELDS_0_PSC_MB4_SHIFT                    MK_SHIFT_CONST(14)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB4_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB4_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB4_RANGE                    MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB4_ROW                      0

#define SLICE11_ICTLR_FIELDS_0_PSC_MB5_SHIFT                    MK_SHIFT_CONST(15)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB5_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB5_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB5_RANGE                    MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB5_ROW                      0

#define SLICE11_ICTLR_FIELDS_0_PSC_MB6_SHIFT                    MK_SHIFT_CONST(16)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB6_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB6_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB6_RANGE                    MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB6_ROW                      0

#define SLICE11_ICTLR_FIELDS_0_PSC_MB7_SHIFT                    MK_SHIFT_CONST(17)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB7_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB7_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB7_RANGE                    MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB7_ROW                      0

#define SLICE11_ICTLR_FIELDS_0_PSC_MB8_SHIFT                    MK_SHIFT_CONST(18)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB8_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB8_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB8_RANGE                    MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB8_ROW                      0

#define SLICE11_ICTLR_FIELDS_0_PSC_MB9_SHIFT                    MK_SHIFT_CONST(19)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB9_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB9_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB9_RANGE                    MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB9_ROW                      0

#define SLICE11_ICTLR_FIELDS_0_PSC_MB10_SHIFT                   MK_SHIFT_CONST(20)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB10_FIELD                   MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB10_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB10_RANGE                   MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB10_ROW                     0

#define SLICE11_ICTLR_FIELDS_0_PSC_MB11_SHIFT                   MK_SHIFT_CONST(21)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB11_FIELD                   MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB11_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB11_RANGE                   MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE11_ICTLR_FIELDS_0_PSC_MB11_ROW                     0

#define SLICE11_ICTLR_FIELDS_0_RESERVED_374_SHIFT                       MK_SHIFT_CONST(22)
#define SLICE11_ICTLR_FIELDS_0_RESERVED_374_FIELD                       MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_RESERVED_374_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_RESERVED_374_RANGE                       MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE11_ICTLR_FIELDS_0_RESERVED_374_ROW                 0

#define SLICE11_ICTLR_FIELDS_0_RESERVED_375_SHIFT                       MK_SHIFT_CONST(23)
#define SLICE11_ICTLR_FIELDS_0_RESERVED_375_FIELD                       MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_RESERVED_375_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_RESERVED_375_RANGE                       MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE11_ICTLR_FIELDS_0_RESERVED_375_ROW                 0

#define SLICE11_ICTLR_FIELDS_0_DCE_WDT_REMOTE_SHIFT                     MK_SHIFT_CONST(24)
#define SLICE11_ICTLR_FIELDS_0_DCE_WDT_REMOTE_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_DCE_WDT_REMOTE_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_DCE_WDT_REMOTE_RANGE                     MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE11_ICTLR_FIELDS_0_DCE_WDT_REMOTE_ROW                       0

#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_0_SHIFT                     MK_SHIFT_CONST(25)
#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_0_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_0_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_0_RANGE                     MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_0_ROW                       0

#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_1_SHIFT                     MK_SHIFT_CONST(26)
#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_1_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_1_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_1_RANGE                     MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_1_ROW                       0

#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_2_SHIFT                     MK_SHIFT_CONST(27)
#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_2_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_2_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_2_RANGE                     MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_2_ROW                       0

#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_3_SHIFT                     MK_SHIFT_CONST(28)
#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_3_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_3_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_3_RANGE                     MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_3_ROW                       0

#define SLICE11_ICTLR_FIELDS_0_SECURE_DCE_FABRIC_SHIFT                  MK_SHIFT_CONST(29)
#define SLICE11_ICTLR_FIELDS_0_SECURE_DCE_FABRIC_FIELD                  MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_SECURE_DCE_FABRIC_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_SECURE_DCE_FABRIC_RANGE                  MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE11_ICTLR_FIELDS_0_SECURE_DCE_FABRIC_ROW                    0

#define SLICE11_ICTLR_FIELDS_0_RESERVED_382_SHIFT                       MK_SHIFT_CONST(30)
#define SLICE11_ICTLR_FIELDS_0_RESERVED_382_FIELD                       MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_RESERVED_382_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_RESERVED_382_RANGE                       MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE11_ICTLR_FIELDS_0_RESERVED_382_ROW                 0

#define SLICE11_ICTLR_FIELDS_0_RESERVED_383_SHIFT                       MK_SHIFT_CONST(31)
#define SLICE11_ICTLR_FIELDS_0_RESERVED_383_FIELD                       MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_RESERVED_383_SHIFT)
#define SLICE11_ICTLR_FIELDS_0_RESERVED_383_RANGE                       MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE11_ICTLR_FIELDS_0_RESERVED_383_ROW                 0


// Packet SLICE12_ICTLR_FIELDS_0
#define SLICE12_ICTLR_FIELDS_0_SIZE 32

#define SLICE12_ICTLR_FIELDS_0_MGBE0_COMMON_SHIFT                       MK_SHIFT_CONST(0)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_COMMON_FIELD                       MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_COMMON_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_COMMON_RANGE                       MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_COMMON_ROW                 0

#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_0_SHIFT                 MK_SHIFT_CONST(1)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_0_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_VM_0_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_0_RANGE                 MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_0_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_1_SHIFT                 MK_SHIFT_CONST(2)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_1_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_VM_1_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_1_RANGE                 MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_1_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_2_SHIFT                 MK_SHIFT_CONST(3)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_2_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_VM_2_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_2_RANGE                 MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_2_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_3_SHIFT                 MK_SHIFT_CONST(4)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_3_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_VM_3_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_3_RANGE                 MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_3_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_4_SHIFT                 MK_SHIFT_CONST(5)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_4_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_VM_4_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_4_RANGE                 MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_4_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_NON_SECURE_SHIFT                    MK_SHIFT_CONST(6)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_NON_SECURE_FIELD                    MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_NON_SECURE_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_NON_SECURE_RANGE                    MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_NON_SECURE_ROW                      0

#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_SECURE_SHIFT                        MK_SHIFT_CONST(7)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_SECURE_FIELD                        MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_SECURE_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_SECURE_RANGE                        MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_SECURE_ROW                  0

#define SLICE12_ICTLR_FIELDS_0_MGBE1_COMMON_SHIFT                       MK_SHIFT_CONST(8)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_COMMON_FIELD                       MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_COMMON_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_COMMON_RANGE                       MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_COMMON_ROW                 0

#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_0_SHIFT                 MK_SHIFT_CONST(9)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_0_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_VM_0_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_0_RANGE                 MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_0_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_1_SHIFT                 MK_SHIFT_CONST(10)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_1_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_VM_1_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_1_RANGE                 MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_1_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_2_SHIFT                 MK_SHIFT_CONST(11)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_2_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_VM_2_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_2_RANGE                 MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_2_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_3_SHIFT                 MK_SHIFT_CONST(12)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_3_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_VM_3_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_3_RANGE                 MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_3_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_4_SHIFT                 MK_SHIFT_CONST(13)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_4_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_VM_4_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_4_RANGE                 MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_4_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_NON_SECURE_SHIFT                    MK_SHIFT_CONST(14)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_NON_SECURE_FIELD                    MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_NON_SECURE_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_NON_SECURE_RANGE                    MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_NON_SECURE_ROW                      0

#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_SECURE_SHIFT                        MK_SHIFT_CONST(15)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_SECURE_FIELD                        MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_SECURE_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_SECURE_RANGE                        MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_SECURE_ROW                  0

#define SLICE12_ICTLR_FIELDS_0_MGBE2_COMMON_SHIFT                       MK_SHIFT_CONST(16)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_COMMON_FIELD                       MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_COMMON_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_COMMON_RANGE                       MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_COMMON_ROW                 0

#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_0_SHIFT                 MK_SHIFT_CONST(17)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_0_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_VM_0_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_0_RANGE                 MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_0_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_1_SHIFT                 MK_SHIFT_CONST(18)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_1_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_VM_1_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_1_RANGE                 MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_1_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_2_SHIFT                 MK_SHIFT_CONST(19)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_2_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_VM_2_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_2_RANGE                 MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_2_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_3_SHIFT                 MK_SHIFT_CONST(20)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_3_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_VM_3_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_3_RANGE                 MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_3_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_4_SHIFT                 MK_SHIFT_CONST(21)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_4_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_VM_4_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_4_RANGE                 MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_4_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_NON_SECURE_SHIFT                    MK_SHIFT_CONST(22)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_NON_SECURE_FIELD                    MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_NON_SECURE_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_NON_SECURE_RANGE                    MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_NON_SECURE_ROW                      0

#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_SECURE_SHIFT                        MK_SHIFT_CONST(23)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_SECURE_FIELD                        MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_SECURE_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_SECURE_RANGE                        MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_SECURE_ROW                  0

#define SLICE12_ICTLR_FIELDS_0_MGBE3_COMMON_SHIFT                       MK_SHIFT_CONST(24)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_COMMON_FIELD                       MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_COMMON_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_COMMON_RANGE                       MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_COMMON_ROW                 0

#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_0_SHIFT                 MK_SHIFT_CONST(25)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_0_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_VM_0_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_0_RANGE                 MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_0_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_1_SHIFT                 MK_SHIFT_CONST(26)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_1_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_VM_1_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_1_RANGE                 MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_1_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_2_SHIFT                 MK_SHIFT_CONST(27)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_2_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_VM_2_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_2_RANGE                 MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_2_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_3_SHIFT                 MK_SHIFT_CONST(28)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_3_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_VM_3_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_3_RANGE                 MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_3_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_4_SHIFT                 MK_SHIFT_CONST(29)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_4_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_VM_4_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_4_RANGE                 MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_4_ROW                   0

#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_NON_SECURE_SHIFT                    MK_SHIFT_CONST(30)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_NON_SECURE_FIELD                    MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_NON_SECURE_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_NON_SECURE_RANGE                    MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_NON_SECURE_ROW                      0

#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_SECURE_SHIFT                        MK_SHIFT_CONST(31)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_SECURE_FIELD                        MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_SECURE_SHIFT)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_SECURE_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_SECURE_ROW                  0


// Packet SLICE13_ICTLR_FIELDS_0
#define SLICE13_ICTLR_FIELDS_0_SIZE 32

#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2HOST_SHIFT                      MK_SHIFT_CONST(0)
#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2HOST_FIELD                      MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_DISPLAY_2HOST_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2HOST_RANGE                      MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2HOST_ROW                        0

#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2GSP_SHIFT                       MK_SHIFT_CONST(1)
#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2GSP_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_DISPLAY_2GSP_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2GSP_RANGE                       MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2GSP_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2PMU_SHIFT                       MK_SHIFT_CONST(2)
#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2PMU_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_DISPLAY_2PMU_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2PMU_RANGE                       MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2PMU_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_DPAUX0_SHIFT                     MK_SHIFT_CONST(3)
#define SLICE13_ICTLR_FIELDS_0_DPAUX0_FIELD                     MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_DPAUX0_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_DPAUX0_RANGE                     MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE13_ICTLR_FIELDS_0_DPAUX0_ROW                       0

#define SLICE13_ICTLR_FIELDS_0_RESERVED_420_SHIFT                       MK_SHIFT_CONST(4)
#define SLICE13_ICTLR_FIELDS_0_RESERVED_420_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_RESERVED_420_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_RESERVED_420_RANGE                       MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE13_ICTLR_FIELDS_0_RESERVED_420_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_RESERVED_421_SHIFT                       MK_SHIFT_CONST(5)
#define SLICE13_ICTLR_FIELDS_0_RESERVED_421_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_RESERVED_421_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_RESERVED_421_RANGE                       MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE13_ICTLR_FIELDS_0_RESERVED_421_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_RESERVED_422_SHIFT                       MK_SHIFT_CONST(6)
#define SLICE13_ICTLR_FIELDS_0_RESERVED_422_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_RESERVED_422_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_RESERVED_422_RANGE                       MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE13_ICTLR_FIELDS_0_RESERVED_422_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_SE1_APB_SHIFT                    MK_SHIFT_CONST(7)
#define SLICE13_ICTLR_FIELDS_0_SE1_APB_FIELD                    MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_SE1_APB_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_SE1_APB_RANGE                    MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE13_ICTLR_FIELDS_0_SE1_APB_ROW                      0

#define SLICE13_ICTLR_FIELDS_0_SE1_HOST1X_SHIFT                 MK_SHIFT_CONST(8)
#define SLICE13_ICTLR_FIELDS_0_SE1_HOST1X_FIELD                 MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_SE1_HOST1X_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_SE1_HOST1X_RANGE                 MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE13_ICTLR_FIELDS_0_SE1_HOST1X_ROW                   0

#define SLICE13_ICTLR_FIELDS_0_SE1_ELPPKA_SHIFT                 MK_SHIFT_CONST(9)
#define SLICE13_ICTLR_FIELDS_0_SE1_ELPPKA_FIELD                 MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_SE1_ELPPKA_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_SE1_ELPPKA_RANGE                 MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE13_ICTLR_FIELDS_0_SE1_ELPPKA_ROW                   0

#define SLICE13_ICTLR_FIELDS_0_SE1_ELPRNG_SHIFT                 MK_SHIFT_CONST(10)
#define SLICE13_ICTLR_FIELDS_0_SE1_ELPRNG_FIELD                 MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_SE1_ELPRNG_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_SE1_ELPRNG_RANGE                 MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE13_ICTLR_FIELDS_0_SE1_ELPRNG_ROW                   0

#define SLICE13_ICTLR_FIELDS_0_RESERVED_427_SHIFT                       MK_SHIFT_CONST(11)
#define SLICE13_ICTLR_FIELDS_0_RESERVED_427_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_RESERVED_427_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_RESERVED_427_RANGE                       MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE13_ICTLR_FIELDS_0_RESERVED_427_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTA_SHIFT                       MK_SHIFT_CONST(12)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTA_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTA_RANGE                       MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTA_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTB_SHIFT                       MK_SHIFT_CONST(13)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTB_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTB_RANGE                       MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTB_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTC_SHIFT                       MK_SHIFT_CONST(14)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTC_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTC_RANGE                       MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTC_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTD_SHIFT                       MK_SHIFT_CONST(15)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTD_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTD_RANGE                       MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTD_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_0_SHIFT                  MK_SHIFT_CONST(16)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_0_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_0_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_0_RANGE                  MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_0_ROW                    0

#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_1_SHIFT                  MK_SHIFT_CONST(17)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_1_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_1_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_1_RANGE                  MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_1_ROW                    0

#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_2_SHIFT                  MK_SHIFT_CONST(18)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_2_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_2_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_2_RANGE                  MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_2_ROW                    0

#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_3_SHIFT                  MK_SHIFT_CONST(19)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_3_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_3_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_3_RANGE                  MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_3_ROW                    0

#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_4_SHIFT                  MK_SHIFT_CONST(20)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_4_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_4_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_4_RANGE                  MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_4_ROW                    0

#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_5_SHIFT                  MK_SHIFT_CONST(21)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_5_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_5_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_5_RANGE                  MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_5_ROW                    0

#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_6_SHIFT                  MK_SHIFT_CONST(22)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_6_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_6_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_6_RANGE                  MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_6_ROW                    0

#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_7_SHIFT                  MK_SHIFT_CONST(23)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_7_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_7_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_7_RANGE                  MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_7_ROW                    0

#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTA_SHIFT                       MK_SHIFT_CONST(24)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTA_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTA_RANGE                       MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTA_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTB_SHIFT                       MK_SHIFT_CONST(25)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTB_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTB_RANGE                       MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTB_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTC_SHIFT                       MK_SHIFT_CONST(26)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTC_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTC_RANGE                       MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTC_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTD_SHIFT                       MK_SHIFT_CONST(27)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTD_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTD_RANGE                       MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTD_ROW                 0

#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTA_SHIFT                      MK_SHIFT_CONST(28)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTA_FIELD                      MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTA_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTA_RANGE                      MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTA_ROW                        0

#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTB_SHIFT                      MK_SHIFT_CONST(29)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTB_FIELD                      MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTB_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTB_RANGE                      MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTB_ROW                        0

#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTC_SHIFT                      MK_SHIFT_CONST(30)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTC_FIELD                      MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTC_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTC_RANGE                      MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTC_ROW                        0

#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTD_SHIFT                      MK_SHIFT_CONST(31)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTD_FIELD                      MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTD_SHIFT)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTD_RANGE                      MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTD_ROW                        0


// Packet SLICE14_ICTLR_FIELDS_0
#define SLICE14_ICTLR_FIELDS_0_SIZE 32

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(0)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_0_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_0_SYNCPT_RANGE                        MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_0_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(1)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_1_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_1_SYNCPT_RANGE                        MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_1_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(2)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_2_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_2_SYNCPT_RANGE                        MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_2_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(3)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_3_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_3_SYNCPT_RANGE                        MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_3_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(4)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_4_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_4_SYNCPT_RANGE                        MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_4_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(5)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_5_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_5_SYNCPT_RANGE                        MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_5_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(6)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_6_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_6_SYNCPT_RANGE                        MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_6_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(7)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_7_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_7_SYNCPT_RANGE                        MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_7_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(8)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_0_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_0_SYNCPT_RANGE                        MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_0_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(9)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_1_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_1_SYNCPT_RANGE                        MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_1_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(10)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_2_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_2_SYNCPT_RANGE                        MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_2_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(11)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_3_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_3_SYNCPT_RANGE                        MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_3_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(12)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_4_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_4_SYNCPT_RANGE                        MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_4_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(13)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_5_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_5_SYNCPT_RANGE                        MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_5_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(14)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_6_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_6_SYNCPT_RANGE                        MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_6_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(15)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_7_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_7_SYNCPT_RANGE                        MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_7_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(16)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_0_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_0_SYNCPT_RANGE                        MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_0_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(17)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_1_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_1_SYNCPT_RANGE                        MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_1_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(18)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_2_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_2_SYNCPT_RANGE                        MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_2_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(19)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_3_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_3_SYNCPT_RANGE                        MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_3_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(20)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_4_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_4_SYNCPT_RANGE                        MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_4_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(21)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_5_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_5_SYNCPT_RANGE                        MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_5_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(22)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_6_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_6_SYNCPT_RANGE                        MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_6_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(23)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_7_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_7_SYNCPT_RANGE                        MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_7_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(24)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_0_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_0_SYNCPT_RANGE                        MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_0_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(25)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_1_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_1_SYNCPT_RANGE                        MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_1_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(26)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_2_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_2_SYNCPT_RANGE                        MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_2_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(27)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_3_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_3_SYNCPT_RANGE                        MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_3_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(28)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_4_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_4_SYNCPT_RANGE                        MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_4_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(29)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_5_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_5_SYNCPT_RANGE                        MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_5_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(30)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_6_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_6_SYNCPT_RANGE                        MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_6_SYNCPT_ROW                  0

#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(31)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_7_SYNCPT_SHIFT)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_7_SYNCPT_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_7_SYNCPT_ROW                  0


// Packet SLICE15_ICTLR_FIELDS_0
#define SLICE15_ICTLR_FIELDS_0_SIZE 32

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(0)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_0_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_0_SYNCPT_RANGE                        MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_0_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(1)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_1_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_1_SYNCPT_RANGE                        MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_1_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(2)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_2_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_2_SYNCPT_RANGE                        MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_2_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(3)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_3_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_3_SYNCPT_RANGE                        MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_3_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(4)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_4_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_4_SYNCPT_RANGE                        MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_4_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(5)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_5_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_5_SYNCPT_RANGE                        MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_5_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(6)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_6_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_6_SYNCPT_RANGE                        MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_6_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(7)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_7_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_7_SYNCPT_RANGE                        MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_7_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(8)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_0_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_0_SYNCPT_RANGE                        MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_0_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(9)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_1_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_1_SYNCPT_RANGE                        MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_1_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(10)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_2_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_2_SYNCPT_RANGE                        MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_2_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(11)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_3_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_3_SYNCPT_RANGE                        MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_3_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(12)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_4_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_4_SYNCPT_RANGE                        MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_4_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(13)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_5_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_5_SYNCPT_RANGE                        MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_5_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(14)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_6_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_6_SYNCPT_RANGE                        MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_6_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(15)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_7_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_7_SYNCPT_RANGE                        MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_7_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(16)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_0_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_0_SYNCPT_RANGE                        MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_0_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(17)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_1_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_1_SYNCPT_RANGE                        MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_1_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(18)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_2_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_2_SYNCPT_RANGE                        MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_2_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(19)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_3_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_3_SYNCPT_RANGE                        MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_3_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(20)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_4_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_4_SYNCPT_RANGE                        MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_4_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(21)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_5_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_5_SYNCPT_RANGE                        MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_5_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(22)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_6_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_6_SYNCPT_RANGE                        MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_6_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(23)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_7_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_7_SYNCPT_RANGE                        MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_7_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(24)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_0_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_0_SYNCPT_RANGE                        MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_0_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(25)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_1_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_1_SYNCPT_RANGE                        MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_1_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(26)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_2_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_2_SYNCPT_RANGE                        MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_2_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(27)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_3_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_3_SYNCPT_RANGE                        MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_3_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(28)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_4_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_4_SYNCPT_RANGE                        MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_4_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(29)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_5_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_5_SYNCPT_RANGE                        MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_5_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(30)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_6_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_6_SYNCPT_RANGE                        MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_6_SYNCPT_ROW                  0

#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(31)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_7_SYNCPT_SHIFT)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_7_SYNCPT_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_7_SYNCPT_ROW                  0


// Packet SLICE16_ICTLR_FIELDS_0
#define SLICE16_ICTLR_FIELDS_0_SIZE 32

#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTA_SHIFT                       MK_SHIFT_CONST(0)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTA_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTA_RANGE                       MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTA_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTB_SHIFT                       MK_SHIFT_CONST(1)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTB_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTB_RANGE                       MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTB_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTC_SHIFT                       MK_SHIFT_CONST(2)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTC_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTC_RANGE                       MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTC_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTD_SHIFT                       MK_SHIFT_CONST(3)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTD_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTD_RANGE                       MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTD_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTA_SHIFT                       MK_SHIFT_CONST(4)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTA_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTA_RANGE                       MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTA_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTB_SHIFT                       MK_SHIFT_CONST(5)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTB_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTB_RANGE                       MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTB_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTC_SHIFT                       MK_SHIFT_CONST(6)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTC_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTC_RANGE                       MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTC_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTD_SHIFT                       MK_SHIFT_CONST(7)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTD_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTD_RANGE                       MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTD_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTA_SHIFT                       MK_SHIFT_CONST(8)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTA_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTA_RANGE                       MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTA_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTB_SHIFT                       MK_SHIFT_CONST(9)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTB_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTB_RANGE                       MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTB_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTC_SHIFT                       MK_SHIFT_CONST(10)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTC_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTC_RANGE                       MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTC_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTD_SHIFT                       MK_SHIFT_CONST(11)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTD_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTD_RANGE                       MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTD_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTA_SHIFT                       MK_SHIFT_CONST(12)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTA_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTA_RANGE                       MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTA_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTB_SHIFT                       MK_SHIFT_CONST(13)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTB_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTB_RANGE                       MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTB_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTC_SHIFT                       MK_SHIFT_CONST(14)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTC_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTC_RANGE                       MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTC_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTD_SHIFT                       MK_SHIFT_CONST(15)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTD_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTD_RANGE                       MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTD_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTA_SHIFT                       MK_SHIFT_CONST(16)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTA_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTA_RANGE                       MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTA_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTB_SHIFT                       MK_SHIFT_CONST(17)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTB_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTB_RANGE                       MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTB_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTC_SHIFT                       MK_SHIFT_CONST(18)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTC_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTC_RANGE                       MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTC_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTD_SHIFT                       MK_SHIFT_CONST(19)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTD_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTD_RANGE                       MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTD_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTA_SHIFT                       MK_SHIFT_CONST(20)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTA_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTA_RANGE                       MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTA_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTB_SHIFT                       MK_SHIFT_CONST(21)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTB_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTB_RANGE                       MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTB_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTC_SHIFT                       MK_SHIFT_CONST(22)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTC_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTC_RANGE                       MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTC_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTD_SHIFT                       MK_SHIFT_CONST(23)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTD_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTD_RANGE                       MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTD_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTA_SHIFT                       MK_SHIFT_CONST(24)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTA_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTA_RANGE                       MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTA_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTB_SHIFT                       MK_SHIFT_CONST(25)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTB_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTB_RANGE                       MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTB_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTC_SHIFT                       MK_SHIFT_CONST(26)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTC_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTC_RANGE                       MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTC_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTD_SHIFT                       MK_SHIFT_CONST(27)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTD_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTD_RANGE                       MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTD_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTA_SHIFT                       MK_SHIFT_CONST(28)
#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTA_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTA_RANGE                       MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTA_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTB_SHIFT                       MK_SHIFT_CONST(29)
#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTB_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTB_RANGE                       MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTB_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTC_SHIFT                       MK_SHIFT_CONST(30)
#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTC_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTC_RANGE                       MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTC_ROW                 0

#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTD_SHIFT                       MK_SHIFT_CONST(31)
#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTD_SHIFT)
#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTD_RANGE                       MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTD_ROW                 0


//
// REGISTER LIST
//
#define LIST_ARINTR_CTLR_REGS(_op_) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE9_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE9_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE9_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE10_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE10_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE10_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE11_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE11_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE11_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE12_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE12_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE12_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE13_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE13_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE13_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE14_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE14_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE14_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE15_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE15_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE15_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE16_IER_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE16_ISR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE16_IDR_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0) \
_op_(INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE9_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE9_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE9_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE10_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE10_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE10_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE11_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE11_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE11_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE12_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE12_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE12_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE13_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE13_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE13_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE14_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE14_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE14_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE15_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE15_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE15_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE16_IER_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE16_ISR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE16_IDR_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0) \
_op_(INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE9_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE9_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE9_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE10_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE10_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE10_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE11_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE11_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE11_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE12_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE12_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE12_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE13_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE13_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE13_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE14_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE14_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE14_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE15_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE15_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE15_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE16_IER_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE16_ISR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE16_IDR_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0) \
_op_(INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE9_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE9_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE9_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE10_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE10_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE10_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE11_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE11_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE11_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE12_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE12_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE12_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE13_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE13_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE13_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE14_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE14_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE14_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE15_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE15_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE15_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE16_IER_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE16_ISR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE16_IDR_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0) \
_op_(INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE9_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE9_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE9_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE10_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE10_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE10_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE11_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE11_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE11_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE12_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE12_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE12_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE13_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE13_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE13_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE14_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE14_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE14_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE15_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE15_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE15_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE16_IER_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE16_ISR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE16_IDR_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0) \
_op_(INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE9_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE9_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE9_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE10_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE10_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE10_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE11_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE11_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE11_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE12_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE12_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE12_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE13_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE13_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE13_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE14_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE14_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE14_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE15_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE15_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE15_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE16_IER_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE16_ISR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE16_IDR_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0) \
_op_(INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE9_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE9_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE9_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE10_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE10_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE10_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE11_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE11_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE11_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE12_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE12_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE12_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE13_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE13_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE13_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE14_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE14_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE14_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE15_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE15_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE15_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE16_IER_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE16_ISR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE16_IDR_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0) \
_op_(INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE9_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE9_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE9_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE10_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE10_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE10_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE11_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE11_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE11_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE12_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE12_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE12_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE13_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE13_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE13_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE14_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE14_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE14_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE15_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE15_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE15_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE16_IER_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE16_ISR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE16_IDR_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0) \
_op_(INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE9_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE9_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE9_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE10_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE10_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE10_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE11_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE11_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE11_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE12_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE12_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE12_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE13_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE13_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE13_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE14_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE14_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE14_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE15_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE15_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE15_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE16_IER_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE16_ISR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE16_IDR_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0) \
_op_(INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE9_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE9_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE9_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE10_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE10_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE10_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE11_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE11_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE11_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE12_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE12_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE12_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE13_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE13_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE13_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE14_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE14_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE14_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE15_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE15_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE15_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE16_IER_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE16_ISR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE16_IDR_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0) \
_op_(INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE9_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE9_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE9_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE10_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE10_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE10_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE11_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE11_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE11_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE12_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE12_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE12_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE13_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE13_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE13_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE14_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE14_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE14_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE15_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE15_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE15_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE16_IER_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE16_ISR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE16_IDR_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0) \
_op_(INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE0_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE0_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE0_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE1_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE1_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE1_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE2_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE2_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE2_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE3_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE3_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE3_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE4_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE4_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE4_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE5_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE5_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE5_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE6_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE6_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE6_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE7_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE7_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE7_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE8_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE8_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE8_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE9_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE9_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE9_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE10_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE10_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE10_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE11_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE11_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE11_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE12_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE12_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE12_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE13_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE13_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE13_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE14_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE14_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE14_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE15_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE15_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE15_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE16_IER_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE16_ISR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE16_IDR_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0) \
_op_(INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0) \
_op_(INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0) \
_op_(INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0) \
_op_(INTR_CTLR_COMMON_SLICE0_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE0_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE0_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE0_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE0_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE0_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE1_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE1_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE1_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE1_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE1_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE1_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE2_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE2_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE2_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE2_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE2_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE2_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE3_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE3_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE3_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE3_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE3_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE3_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE4_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE4_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE4_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE4_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE4_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE4_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE5_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE5_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE5_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE5_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE5_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE5_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE6_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE6_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE6_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE6_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE6_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE6_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE7_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE7_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE7_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE7_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE7_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE7_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE8_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE8_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE8_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE8_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE8_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE8_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE9_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE9_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE9_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE9_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE9_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE9_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE10_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE10_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE10_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE10_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE10_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE10_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE11_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE11_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE11_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE11_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE11_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE11_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE12_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE12_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE12_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE12_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE12_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE12_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE13_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE13_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE13_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE13_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE13_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE13_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE14_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE14_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE14_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE14_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE14_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE14_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE15_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE15_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE15_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE15_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE15_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE15_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE16_GISR_0) \
_op_(INTR_CTLR_COMMON_SLICE16_FIR_0) \
_op_(INTR_CTLR_COMMON_SLICE16_FIR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE16_FIR_CLR_0) \
_op_(INTR_CTLR_COMMON_SLICE16_CIDR_0) \
_op_(INTR_CTLR_COMMON_SLICE16_CIDR_SET_0) \
_op_(INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0) \
_op_(INTR_CTLR_COMMON_SCR_SCR_COMMON_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_INTR_CTLR  0x00000000
#define BASE_ADDRESS_INTR_CTLR_CHANNEL0 0x00000000
#define BASE_ADDRESS_INTR_CTLR_CHANNEL0_SCR     0x000007c0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL1 0x00000800
#define BASE_ADDRESS_INTR_CTLR_CHANNEL1_SCR     0x00000fc0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL2 0x00001000
#define BASE_ADDRESS_INTR_CTLR_CHANNEL2_SCR     0x000017c0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL3 0x00001800
#define BASE_ADDRESS_INTR_CTLR_CHANNEL3_SCR     0x00001fc0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL4 0x00002000
#define BASE_ADDRESS_INTR_CTLR_CHANNEL4_SCR     0x000027c0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL5 0x00002800
#define BASE_ADDRESS_INTR_CTLR_CHANNEL5_SCR     0x00002fc0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL6 0x00003000
#define BASE_ADDRESS_INTR_CTLR_CHANNEL6_SCR     0x000037c0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL7 0x00003800
#define BASE_ADDRESS_INTR_CTLR_CHANNEL7_SCR     0x00003fc0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL8 0x00004000
#define BASE_ADDRESS_INTR_CTLR_CHANNEL8_SCR     0x000047c0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL9 0x00004800
#define BASE_ADDRESS_INTR_CTLR_CHANNEL9_SCR     0x00004fc0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL10        0x00005000
#define BASE_ADDRESS_INTR_CTLR_CHANNEL10_SCR    0x000057c0
#define BASE_ADDRESS_INTR_CTLR_CHANNEL11        0x00005800
#define BASE_ADDRESS_INTR_CTLR_CHANNEL11_SCR    0x00005fc0
#define BASE_ADDRESS_INTR_CTLR_COMMON   0x0000f800
#define BASE_ADDRESS_INTR_CTLR_COMMON_SCR       0x0000ffc4

//
// ARINTR_CTLR REGISTER BANKS
//

#define INTR_CTLR_CHANNEL0_0_FIRST_REG 0x0000 // INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL0_0_LAST_REG 0x0024 // INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_1_FIRST_REG 0x0040 // INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL0_1_LAST_REG 0x0064 // INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_2_FIRST_REG 0x0080 // INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL0_2_LAST_REG 0x00a4 // INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_3_FIRST_REG 0x00c0 // INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL0_3_LAST_REG 0x00e4 // INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_4_FIRST_REG 0x0100 // INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL0_4_LAST_REG 0x0124 // INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_5_FIRST_REG 0x0140 // INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL0_5_LAST_REG 0x0164 // INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_6_FIRST_REG 0x0180 // INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL0_6_LAST_REG 0x01a4 // INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_7_FIRST_REG 0x01c0 // INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL0_7_LAST_REG 0x01e4 // INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_8_FIRST_REG 0x0200 // INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL0_8_LAST_REG 0x0224 // INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_9_FIRST_REG 0x0240 // INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL0_9_LAST_REG 0x0264 // INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_10_FIRST_REG 0x0280 // INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL0_10_LAST_REG 0x02a4 // INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_11_FIRST_REG 0x02c0 // INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL0_11_LAST_REG 0x02e4 // INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_12_FIRST_REG 0x0300 // INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL0_12_LAST_REG 0x0324 // INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_13_FIRST_REG 0x0340 // INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL0_13_LAST_REG 0x0364 // INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_14_FIRST_REG 0x0380 // INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL0_14_LAST_REG 0x03a4 // INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_15_FIRST_REG 0x03c0 // INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL0_15_LAST_REG 0x03e4 // INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_16_FIRST_REG 0x0400 // INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL0_16_LAST_REG 0x0424 // INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL0_SCR_0_FIRST_REG 0x07c0 // INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
#define INTR_CTLR_CHANNEL0_SCR_0_LAST_REG 0x07c4 // INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
#define INTR_CTLR_CHANNEL1_0_FIRST_REG 0x0800 // INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL1_0_LAST_REG 0x0824 // INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_1_FIRST_REG 0x0840 // INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL1_1_LAST_REG 0x0864 // INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_2_FIRST_REG 0x0880 // INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL1_2_LAST_REG 0x08a4 // INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_3_FIRST_REG 0x08c0 // INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL1_3_LAST_REG 0x08e4 // INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_4_FIRST_REG 0x0900 // INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL1_4_LAST_REG 0x0924 // INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_5_FIRST_REG 0x0940 // INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL1_5_LAST_REG 0x0964 // INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_6_FIRST_REG 0x0980 // INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL1_6_LAST_REG 0x09a4 // INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_7_FIRST_REG 0x09c0 // INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL1_7_LAST_REG 0x09e4 // INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_8_FIRST_REG 0x0a00 // INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL1_8_LAST_REG 0x0a24 // INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_9_FIRST_REG 0x0a40 // INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL1_9_LAST_REG 0x0a64 // INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_10_FIRST_REG 0x0a80 // INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL1_10_LAST_REG 0x0aa4 // INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_11_FIRST_REG 0x0ac0 // INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL1_11_LAST_REG 0x0ae4 // INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_12_FIRST_REG 0x0b00 // INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL1_12_LAST_REG 0x0b24 // INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_13_FIRST_REG 0x0b40 // INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL1_13_LAST_REG 0x0b64 // INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_14_FIRST_REG 0x0b80 // INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL1_14_LAST_REG 0x0ba4 // INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_15_FIRST_REG 0x0bc0 // INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL1_15_LAST_REG 0x0be4 // INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_16_FIRST_REG 0x0c00 // INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL1_16_LAST_REG 0x0c24 // INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL1_SCR_0_FIRST_REG 0x0fc0 // INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
#define INTR_CTLR_CHANNEL1_SCR_0_LAST_REG 0x0fc4 // INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
#define INTR_CTLR_CHANNEL2_0_FIRST_REG 0x1000 // INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL2_0_LAST_REG 0x1024 // INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_1_FIRST_REG 0x1040 // INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL2_1_LAST_REG 0x1064 // INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_2_FIRST_REG 0x1080 // INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL2_2_LAST_REG 0x10a4 // INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_3_FIRST_REG 0x10c0 // INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL2_3_LAST_REG 0x10e4 // INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_4_FIRST_REG 0x1100 // INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL2_4_LAST_REG 0x1124 // INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_5_FIRST_REG 0x1140 // INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL2_5_LAST_REG 0x1164 // INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_6_FIRST_REG 0x1180 // INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL2_6_LAST_REG 0x11a4 // INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_7_FIRST_REG 0x11c0 // INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL2_7_LAST_REG 0x11e4 // INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_8_FIRST_REG 0x1200 // INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL2_8_LAST_REG 0x1224 // INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_9_FIRST_REG 0x1240 // INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL2_9_LAST_REG 0x1264 // INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_10_FIRST_REG 0x1280 // INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL2_10_LAST_REG 0x12a4 // INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_11_FIRST_REG 0x12c0 // INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL2_11_LAST_REG 0x12e4 // INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_12_FIRST_REG 0x1300 // INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL2_12_LAST_REG 0x1324 // INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_13_FIRST_REG 0x1340 // INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL2_13_LAST_REG 0x1364 // INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_14_FIRST_REG 0x1380 // INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL2_14_LAST_REG 0x13a4 // INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_15_FIRST_REG 0x13c0 // INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL2_15_LAST_REG 0x13e4 // INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_16_FIRST_REG 0x1400 // INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL2_16_LAST_REG 0x1424 // INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL2_SCR_0_FIRST_REG 0x17c0 // INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
#define INTR_CTLR_CHANNEL2_SCR_0_LAST_REG 0x17c4 // INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
#define INTR_CTLR_CHANNEL3_0_FIRST_REG 0x1800 // INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL3_0_LAST_REG 0x1824 // INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_1_FIRST_REG 0x1840 // INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL3_1_LAST_REG 0x1864 // INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_2_FIRST_REG 0x1880 // INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL3_2_LAST_REG 0x18a4 // INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_3_FIRST_REG 0x18c0 // INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL3_3_LAST_REG 0x18e4 // INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_4_FIRST_REG 0x1900 // INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL3_4_LAST_REG 0x1924 // INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_5_FIRST_REG 0x1940 // INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL3_5_LAST_REG 0x1964 // INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_6_FIRST_REG 0x1980 // INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL3_6_LAST_REG 0x19a4 // INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_7_FIRST_REG 0x19c0 // INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL3_7_LAST_REG 0x19e4 // INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_8_FIRST_REG 0x1a00 // INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL3_8_LAST_REG 0x1a24 // INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_9_FIRST_REG 0x1a40 // INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL3_9_LAST_REG 0x1a64 // INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_10_FIRST_REG 0x1a80 // INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL3_10_LAST_REG 0x1aa4 // INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_11_FIRST_REG 0x1ac0 // INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL3_11_LAST_REG 0x1ae4 // INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_12_FIRST_REG 0x1b00 // INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL3_12_LAST_REG 0x1b24 // INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_13_FIRST_REG 0x1b40 // INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL3_13_LAST_REG 0x1b64 // INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_14_FIRST_REG 0x1b80 // INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL3_14_LAST_REG 0x1ba4 // INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_15_FIRST_REG 0x1bc0 // INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL3_15_LAST_REG 0x1be4 // INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_16_FIRST_REG 0x1c00 // INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL3_16_LAST_REG 0x1c24 // INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL3_SCR_0_FIRST_REG 0x1fc0 // INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
#define INTR_CTLR_CHANNEL3_SCR_0_LAST_REG 0x1fc4 // INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
#define INTR_CTLR_CHANNEL4_0_FIRST_REG 0x2000 // INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL4_0_LAST_REG 0x2024 // INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_1_FIRST_REG 0x2040 // INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL4_1_LAST_REG 0x2064 // INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_2_FIRST_REG 0x2080 // INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL4_2_LAST_REG 0x20a4 // INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_3_FIRST_REG 0x20c0 // INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL4_3_LAST_REG 0x20e4 // INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_4_FIRST_REG 0x2100 // INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL4_4_LAST_REG 0x2124 // INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_5_FIRST_REG 0x2140 // INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL4_5_LAST_REG 0x2164 // INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_6_FIRST_REG 0x2180 // INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL4_6_LAST_REG 0x21a4 // INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_7_FIRST_REG 0x21c0 // INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL4_7_LAST_REG 0x21e4 // INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_8_FIRST_REG 0x2200 // INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL4_8_LAST_REG 0x2224 // INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_9_FIRST_REG 0x2240 // INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL4_9_LAST_REG 0x2264 // INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_10_FIRST_REG 0x2280 // INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL4_10_LAST_REG 0x22a4 // INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_11_FIRST_REG 0x22c0 // INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL4_11_LAST_REG 0x22e4 // INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_12_FIRST_REG 0x2300 // INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL4_12_LAST_REG 0x2324 // INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_13_FIRST_REG 0x2340 // INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL4_13_LAST_REG 0x2364 // INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_14_FIRST_REG 0x2380 // INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL4_14_LAST_REG 0x23a4 // INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_15_FIRST_REG 0x23c0 // INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL4_15_LAST_REG 0x23e4 // INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_16_FIRST_REG 0x2400 // INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL4_16_LAST_REG 0x2424 // INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL4_SCR_0_FIRST_REG 0x27c0 // INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
#define INTR_CTLR_CHANNEL4_SCR_0_LAST_REG 0x27c4 // INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
#define INTR_CTLR_CHANNEL5_0_FIRST_REG 0x2800 // INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL5_0_LAST_REG 0x2824 // INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_1_FIRST_REG 0x2840 // INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL5_1_LAST_REG 0x2864 // INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_2_FIRST_REG 0x2880 // INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL5_2_LAST_REG 0x28a4 // INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_3_FIRST_REG 0x28c0 // INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL5_3_LAST_REG 0x28e4 // INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_4_FIRST_REG 0x2900 // INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL5_4_LAST_REG 0x2924 // INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_5_FIRST_REG 0x2940 // INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL5_5_LAST_REG 0x2964 // INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_6_FIRST_REG 0x2980 // INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL5_6_LAST_REG 0x29a4 // INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_7_FIRST_REG 0x29c0 // INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL5_7_LAST_REG 0x29e4 // INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_8_FIRST_REG 0x2a00 // INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL5_8_LAST_REG 0x2a24 // INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_9_FIRST_REG 0x2a40 // INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL5_9_LAST_REG 0x2a64 // INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_10_FIRST_REG 0x2a80 // INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL5_10_LAST_REG 0x2aa4 // INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_11_FIRST_REG 0x2ac0 // INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL5_11_LAST_REG 0x2ae4 // INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_12_FIRST_REG 0x2b00 // INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL5_12_LAST_REG 0x2b24 // INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_13_FIRST_REG 0x2b40 // INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL5_13_LAST_REG 0x2b64 // INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_14_FIRST_REG 0x2b80 // INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL5_14_LAST_REG 0x2ba4 // INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_15_FIRST_REG 0x2bc0 // INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL5_15_LAST_REG 0x2be4 // INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_16_FIRST_REG 0x2c00 // INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL5_16_LAST_REG 0x2c24 // INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL5_SCR_0_FIRST_REG 0x2fc0 // INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
#define INTR_CTLR_CHANNEL5_SCR_0_LAST_REG 0x2fc4 // INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
#define INTR_CTLR_CHANNEL6_0_FIRST_REG 0x3000 // INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL6_0_LAST_REG 0x3024 // INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_1_FIRST_REG 0x3040 // INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL6_1_LAST_REG 0x3064 // INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_2_FIRST_REG 0x3080 // INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL6_2_LAST_REG 0x30a4 // INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_3_FIRST_REG 0x30c0 // INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL6_3_LAST_REG 0x30e4 // INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_4_FIRST_REG 0x3100 // INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL6_4_LAST_REG 0x3124 // INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_5_FIRST_REG 0x3140 // INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL6_5_LAST_REG 0x3164 // INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_6_FIRST_REG 0x3180 // INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL6_6_LAST_REG 0x31a4 // INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_7_FIRST_REG 0x31c0 // INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL6_7_LAST_REG 0x31e4 // INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_8_FIRST_REG 0x3200 // INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL6_8_LAST_REG 0x3224 // INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_9_FIRST_REG 0x3240 // INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL6_9_LAST_REG 0x3264 // INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_10_FIRST_REG 0x3280 // INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL6_10_LAST_REG 0x32a4 // INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_11_FIRST_REG 0x32c0 // INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL6_11_LAST_REG 0x32e4 // INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_12_FIRST_REG 0x3300 // INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL6_12_LAST_REG 0x3324 // INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_13_FIRST_REG 0x3340 // INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL6_13_LAST_REG 0x3364 // INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_14_FIRST_REG 0x3380 // INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL6_14_LAST_REG 0x33a4 // INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_15_FIRST_REG 0x33c0 // INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL6_15_LAST_REG 0x33e4 // INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_16_FIRST_REG 0x3400 // INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL6_16_LAST_REG 0x3424 // INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL6_SCR_0_FIRST_REG 0x37c0 // INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
#define INTR_CTLR_CHANNEL6_SCR_0_LAST_REG 0x37c4 // INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
#define INTR_CTLR_CHANNEL7_0_FIRST_REG 0x3800 // INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL7_0_LAST_REG 0x3824 // INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_1_FIRST_REG 0x3840 // INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL7_1_LAST_REG 0x3864 // INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_2_FIRST_REG 0x3880 // INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL7_2_LAST_REG 0x38a4 // INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_3_FIRST_REG 0x38c0 // INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL7_3_LAST_REG 0x38e4 // INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_4_FIRST_REG 0x3900 // INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL7_4_LAST_REG 0x3924 // INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_5_FIRST_REG 0x3940 // INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL7_5_LAST_REG 0x3964 // INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_6_FIRST_REG 0x3980 // INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL7_6_LAST_REG 0x39a4 // INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_7_FIRST_REG 0x39c0 // INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL7_7_LAST_REG 0x39e4 // INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_8_FIRST_REG 0x3a00 // INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL7_8_LAST_REG 0x3a24 // INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_9_FIRST_REG 0x3a40 // INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL7_9_LAST_REG 0x3a64 // INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_10_FIRST_REG 0x3a80 // INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL7_10_LAST_REG 0x3aa4 // INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_11_FIRST_REG 0x3ac0 // INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL7_11_LAST_REG 0x3ae4 // INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_12_FIRST_REG 0x3b00 // INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL7_12_LAST_REG 0x3b24 // INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_13_FIRST_REG 0x3b40 // INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL7_13_LAST_REG 0x3b64 // INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_14_FIRST_REG 0x3b80 // INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL7_14_LAST_REG 0x3ba4 // INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_15_FIRST_REG 0x3bc0 // INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL7_15_LAST_REG 0x3be4 // INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_16_FIRST_REG 0x3c00 // INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL7_16_LAST_REG 0x3c24 // INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL7_SCR_0_FIRST_REG 0x3fc0 // INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
#define INTR_CTLR_CHANNEL7_SCR_0_LAST_REG 0x3fc4 // INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
#define INTR_CTLR_CHANNEL8_0_FIRST_REG 0x4000 // INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL8_0_LAST_REG 0x4024 // INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_1_FIRST_REG 0x4040 // INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL8_1_LAST_REG 0x4064 // INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_2_FIRST_REG 0x4080 // INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL8_2_LAST_REG 0x40a4 // INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_3_FIRST_REG 0x40c0 // INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL8_3_LAST_REG 0x40e4 // INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_4_FIRST_REG 0x4100 // INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL8_4_LAST_REG 0x4124 // INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_5_FIRST_REG 0x4140 // INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL8_5_LAST_REG 0x4164 // INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_6_FIRST_REG 0x4180 // INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL8_6_LAST_REG 0x41a4 // INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_7_FIRST_REG 0x41c0 // INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL8_7_LAST_REG 0x41e4 // INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_8_FIRST_REG 0x4200 // INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL8_8_LAST_REG 0x4224 // INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_9_FIRST_REG 0x4240 // INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL8_9_LAST_REG 0x4264 // INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_10_FIRST_REG 0x4280 // INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL8_10_LAST_REG 0x42a4 // INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_11_FIRST_REG 0x42c0 // INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL8_11_LAST_REG 0x42e4 // INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_12_FIRST_REG 0x4300 // INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL8_12_LAST_REG 0x4324 // INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_13_FIRST_REG 0x4340 // INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL8_13_LAST_REG 0x4364 // INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_14_FIRST_REG 0x4380 // INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL8_14_LAST_REG 0x43a4 // INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_15_FIRST_REG 0x43c0 // INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL8_15_LAST_REG 0x43e4 // INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_16_FIRST_REG 0x4400 // INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL8_16_LAST_REG 0x4424 // INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL8_SCR_0_FIRST_REG 0x47c0 // INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
#define INTR_CTLR_CHANNEL8_SCR_0_LAST_REG 0x47c4 // INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
#define INTR_CTLR_CHANNEL9_0_FIRST_REG 0x4800 // INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL9_0_LAST_REG 0x4824 // INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_1_FIRST_REG 0x4840 // INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL9_1_LAST_REG 0x4864 // INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_2_FIRST_REG 0x4880 // INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL9_2_LAST_REG 0x48a4 // INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_3_FIRST_REG 0x48c0 // INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL9_3_LAST_REG 0x48e4 // INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_4_FIRST_REG 0x4900 // INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL9_4_LAST_REG 0x4924 // INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_5_FIRST_REG 0x4940 // INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL9_5_LAST_REG 0x4964 // INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_6_FIRST_REG 0x4980 // INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL9_6_LAST_REG 0x49a4 // INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_7_FIRST_REG 0x49c0 // INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL9_7_LAST_REG 0x49e4 // INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_8_FIRST_REG 0x4a00 // INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL9_8_LAST_REG 0x4a24 // INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_9_FIRST_REG 0x4a40 // INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL9_9_LAST_REG 0x4a64 // INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_10_FIRST_REG 0x4a80 // INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL9_10_LAST_REG 0x4aa4 // INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_11_FIRST_REG 0x4ac0 // INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL9_11_LAST_REG 0x4ae4 // INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_12_FIRST_REG 0x4b00 // INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL9_12_LAST_REG 0x4b24 // INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_13_FIRST_REG 0x4b40 // INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL9_13_LAST_REG 0x4b64 // INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_14_FIRST_REG 0x4b80 // INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL9_14_LAST_REG 0x4ba4 // INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_15_FIRST_REG 0x4bc0 // INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL9_15_LAST_REG 0x4be4 // INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_16_FIRST_REG 0x4c00 // INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL9_16_LAST_REG 0x4c24 // INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL9_SCR_0_FIRST_REG 0x4fc0 // INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
#define INTR_CTLR_CHANNEL9_SCR_0_LAST_REG 0x4fc4 // INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
#define INTR_CTLR_CHANNEL10_0_FIRST_REG 0x5000 // INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL10_0_LAST_REG 0x5024 // INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_1_FIRST_REG 0x5040 // INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL10_1_LAST_REG 0x5064 // INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_2_FIRST_REG 0x5080 // INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL10_2_LAST_REG 0x50a4 // INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_3_FIRST_REG 0x50c0 // INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL10_3_LAST_REG 0x50e4 // INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_4_FIRST_REG 0x5100 // INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL10_4_LAST_REG 0x5124 // INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_5_FIRST_REG 0x5140 // INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL10_5_LAST_REG 0x5164 // INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_6_FIRST_REG 0x5180 // INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL10_6_LAST_REG 0x51a4 // INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_7_FIRST_REG 0x51c0 // INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL10_7_LAST_REG 0x51e4 // INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_8_FIRST_REG 0x5200 // INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL10_8_LAST_REG 0x5224 // INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_9_FIRST_REG 0x5240 // INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL10_9_LAST_REG 0x5264 // INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_10_FIRST_REG 0x5280 // INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL10_10_LAST_REG 0x52a4 // INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_11_FIRST_REG 0x52c0 // INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL10_11_LAST_REG 0x52e4 // INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_12_FIRST_REG 0x5300 // INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL10_12_LAST_REG 0x5324 // INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_13_FIRST_REG 0x5340 // INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL10_13_LAST_REG 0x5364 // INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_14_FIRST_REG 0x5380 // INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL10_14_LAST_REG 0x53a4 // INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_15_FIRST_REG 0x53c0 // INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL10_15_LAST_REG 0x53e4 // INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_16_FIRST_REG 0x5400 // INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL10_16_LAST_REG 0x5424 // INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL10_SCR_0_FIRST_REG 0x57c0 // INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
#define INTR_CTLR_CHANNEL10_SCR_0_LAST_REG 0x57c4 // INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
#define INTR_CTLR_CHANNEL11_0_FIRST_REG 0x5800 // INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0
#define INTR_CTLR_CHANNEL11_0_LAST_REG 0x5824 // INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_1_FIRST_REG 0x5840 // INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0
#define INTR_CTLR_CHANNEL11_1_LAST_REG 0x5864 // INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_2_FIRST_REG 0x5880 // INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0
#define INTR_CTLR_CHANNEL11_2_LAST_REG 0x58a4 // INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_3_FIRST_REG 0x58c0 // INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0
#define INTR_CTLR_CHANNEL11_3_LAST_REG 0x58e4 // INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_4_FIRST_REG 0x5900 // INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0
#define INTR_CTLR_CHANNEL11_4_LAST_REG 0x5924 // INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_5_FIRST_REG 0x5940 // INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0
#define INTR_CTLR_CHANNEL11_5_LAST_REG 0x5964 // INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_6_FIRST_REG 0x5980 // INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0
#define INTR_CTLR_CHANNEL11_6_LAST_REG 0x59a4 // INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_7_FIRST_REG 0x59c0 // INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0
#define INTR_CTLR_CHANNEL11_7_LAST_REG 0x59e4 // INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_8_FIRST_REG 0x5a00 // INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0
#define INTR_CTLR_CHANNEL11_8_LAST_REG 0x5a24 // INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_9_FIRST_REG 0x5a40 // INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0
#define INTR_CTLR_CHANNEL11_9_LAST_REG 0x5a64 // INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_10_FIRST_REG 0x5a80 // INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0
#define INTR_CTLR_CHANNEL11_10_LAST_REG 0x5aa4 // INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_11_FIRST_REG 0x5ac0 // INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0
#define INTR_CTLR_CHANNEL11_11_LAST_REG 0x5ae4 // INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_12_FIRST_REG 0x5b00 // INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0
#define INTR_CTLR_CHANNEL11_12_LAST_REG 0x5b24 // INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_13_FIRST_REG 0x5b40 // INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0
#define INTR_CTLR_CHANNEL11_13_LAST_REG 0x5b64 // INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_14_FIRST_REG 0x5b80 // INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0
#define INTR_CTLR_CHANNEL11_14_LAST_REG 0x5ba4 // INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_15_FIRST_REG 0x5bc0 // INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0
#define INTR_CTLR_CHANNEL11_15_LAST_REG 0x5be4 // INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_16_FIRST_REG 0x5c00 // INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0
#define INTR_CTLR_CHANNEL11_16_LAST_REG 0x5c24 // INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0
#define INTR_CTLR_CHANNEL11_SCR_0_FIRST_REG 0x5fc0 // INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
#define INTR_CTLR_CHANNEL11_SCR_0_LAST_REG 0x5fc4 // INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
#define INTR_CTLR_COMMON_0_FIRST_REG 0xf800 // INTR_CTLR_COMMON_SLICE0_GISR_0
#define INTR_CTLR_COMMON_0_LAST_REG 0xf818 // INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0
#define INTR_CTLR_COMMON_1_FIRST_REG 0xf840 // INTR_CTLR_COMMON_SLICE1_GISR_0
#define INTR_CTLR_COMMON_1_LAST_REG 0xf858 // INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0
#define INTR_CTLR_COMMON_2_FIRST_REG 0xf880 // INTR_CTLR_COMMON_SLICE2_GISR_0
#define INTR_CTLR_COMMON_2_LAST_REG 0xf898 // INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0
#define INTR_CTLR_COMMON_3_FIRST_REG 0xf8c0 // INTR_CTLR_COMMON_SLICE3_GISR_0
#define INTR_CTLR_COMMON_3_LAST_REG 0xf8d8 // INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0
#define INTR_CTLR_COMMON_4_FIRST_REG 0xf900 // INTR_CTLR_COMMON_SLICE4_GISR_0
#define INTR_CTLR_COMMON_4_LAST_REG 0xf918 // INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0
#define INTR_CTLR_COMMON_5_FIRST_REG 0xf940 // INTR_CTLR_COMMON_SLICE5_GISR_0
#define INTR_CTLR_COMMON_5_LAST_REG 0xf958 // INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0
#define INTR_CTLR_COMMON_6_FIRST_REG 0xf980 // INTR_CTLR_COMMON_SLICE6_GISR_0
#define INTR_CTLR_COMMON_6_LAST_REG 0xf998 // INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0
#define INTR_CTLR_COMMON_7_FIRST_REG 0xf9c0 // INTR_CTLR_COMMON_SLICE7_GISR_0
#define INTR_CTLR_COMMON_7_LAST_REG 0xf9d8 // INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0
#define INTR_CTLR_COMMON_8_FIRST_REG 0xfa00 // INTR_CTLR_COMMON_SLICE8_GISR_0
#define INTR_CTLR_COMMON_8_LAST_REG 0xfa18 // INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0
#define INTR_CTLR_COMMON_9_FIRST_REG 0xfa40 // INTR_CTLR_COMMON_SLICE9_GISR_0
#define INTR_CTLR_COMMON_9_LAST_REG 0xfa58 // INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0
#define INTR_CTLR_COMMON_10_FIRST_REG 0xfa80 // INTR_CTLR_COMMON_SLICE10_GISR_0
#define INTR_CTLR_COMMON_10_LAST_REG 0xfa98 // INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0
#define INTR_CTLR_COMMON_11_FIRST_REG 0xfac0 // INTR_CTLR_COMMON_SLICE11_GISR_0
#define INTR_CTLR_COMMON_11_LAST_REG 0xfad8 // INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0
#define INTR_CTLR_COMMON_12_FIRST_REG 0xfb00 // INTR_CTLR_COMMON_SLICE12_GISR_0
#define INTR_CTLR_COMMON_12_LAST_REG 0xfb18 // INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0
#define INTR_CTLR_COMMON_13_FIRST_REG 0xfb40 // INTR_CTLR_COMMON_SLICE13_GISR_0
#define INTR_CTLR_COMMON_13_LAST_REG 0xfb58 // INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0
#define INTR_CTLR_COMMON_14_FIRST_REG 0xfb80 // INTR_CTLR_COMMON_SLICE14_GISR_0
#define INTR_CTLR_COMMON_14_LAST_REG 0xfb98 // INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0
#define INTR_CTLR_COMMON_15_FIRST_REG 0xfbc0 // INTR_CTLR_COMMON_SLICE15_GISR_0
#define INTR_CTLR_COMMON_15_LAST_REG 0xfbd8 // INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0
#define INTR_CTLR_COMMON_16_FIRST_REG 0xfc00 // INTR_CTLR_COMMON_SLICE16_GISR_0
#define INTR_CTLR_COMMON_16_LAST_REG 0xfc18 // INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0
#define INTR_CTLR_COMMON_SCR_0_FIRST_REG 0xffc4 // INTR_CTLR_COMMON_SCR_SCR_COMMON_0
#define INTR_CTLR_COMMON_SCR_0_LAST_REG 0xffc4 // INTR_CTLR_COMMON_SCR_SCR_COMMON_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARINTR_CTLR_H_INC
