/*
 * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: BSD-3-Clause
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice, this
 * list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef ARFUSE_H_INC
#define ARFUSE_H_INC

// Register FUSE_OPT_FSI_DISABLE_0
#define FUSE_OPT_FSI_DISABLE_0                  MK_ADDR_CONST(0x9c8)
#define FUSE_OPT_FSI_DISABLE_0_SECURE                   0x0
#define FUSE_OPT_FSI_DISABLE_0_DUAL                     0x0
#define FUSE_OPT_FSI_DISABLE_0_SCR                      0
#define FUSE_OPT_FSI_DISABLE_0_SCRREG                   0
#define FUSE_OPT_FSI_DISABLE_0_WORD_COUNT                       0x1
#define FUSE_OPT_FSI_DISABLE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define FUSE_OPT_FSI_DISABLE_0_RESET_MASK                       MK_MASK_CONST(0x1)
#define FUSE_OPT_FSI_DISABLE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define FUSE_OPT_FSI_DISABLE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define FUSE_OPT_FSI_DISABLE_0_READ_MASK                        MK_MASK_CONST(0x1)
#define FUSE_OPT_FSI_DISABLE_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_SHIFT                    MK_SHIFT_CONST(0)
#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_FIELD                    MK_FIELD_CONST(0x1, FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_SHIFT)
#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_RANGE                    0:0
#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_MSB                      MK_SHIFT_CONST(0)
#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_LSB                      MK_SHIFT_CONST(0)
#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_WOFFSET                  0x0
#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

//
// REGISTER LIST
//
#define LIST_ARFUSE_REGS(_op_) \
_op_(FUSE_OPT_FSI_DISABLE_0) \

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARFUSE_H_INC
