/*
 * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */

#ifndef GPIO__TEGRA_GPIO_PRIV_H
#define GPIO__TEGRA_GPIO_PRIV_H
#define FSP__GPIO__TEGRA_GPIO_PRIV_H  1

/* Compiler headers */
#include <stdbool.h>                       // for bool
#include <stdint.h>                        // for uint32_t

/* Early FSP headers */
#include <misc/ct-assert.h>                // for CT_ASSERT
#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
#include <soc-common/hw-const.h>           // for MK_U32_CONSTANT

/* Hardware headers */

/*
 * Compile-time check for FSP header files
 *   Each FSP header file contains a signature unique to that file, and the
 *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
 *   check for this signature.  If it does not exist, then the build will
 *   abort.
 *
 *   This is a trap for projects which have their own include files of the
 *   same names, but different contents.  This trap ensures that only the
 *   files from the FSP project, are built into the FSP source code.
 */
#ifndef DOXYGEN_SHOULD_SKIP_THIS
START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
#endif
/**
 * Number of GPIO pins per port/bank
 */
#define GPIOS_PER_BANK    MK_U32_CONST(8)

/**
 * @struct gpio_irq_handler
 * @brief IRQ handler structure
 * @{
 */
struct gpio_irq_handler {
    /** Pointer to the interrupt service routine */
    void (*handler)(void *hdata);
    /** Data to be used by the interrupt handler */
    void *data;
};
/** @} */

/**
 * @struct tegra_gpio_id
 * @brief Tegra GPIO structure
 * @{
 */
struct tegra_gpio_id {
    /**  Base address of GPIO controller */
    uint32_t                base_addr;
    /** Number of GPIO banks/ports supported by the GPIO chip */
    uint32_t                bank_count;
    /** Pointer to an array storing base address of the GPIO banks. */
    const uint32_t          *bank_bases;
    /**
     * Pointer to any array storing irq number of all the GPIO
     * sub-controllers (HW controllers) supported by this instance.
     */
    uint32_t                *irqs;
    /** Number of irqs supported by this GPIO controller */
    uint32_t                nirqs;
    /**
     * Pointer to array storing IRQ handlers mapped one-to-one
     * with the gpio pins
     */
    struct gpio_irq_handler *irq_handlers;
    /** Offset of IRQ status register relative to the ENABLE_CONFIG register */
    uint32_t                irq_status_offset;
    /** Pointer to the array storing IRQ enable status per GPIO bank */
    uint8_t                 *bank_irq_status;
    /**
     * Boolean variable indicating GPIO interrupt handling mechanism. Set it
     * to false, if the client does not need GPIO interrupts or chooses to
     * use its own interrupt handling mechanism instead of registering to
     * the common GPIO IRQ handler.*/
    bool                    isr_status;
    /** Pointer to any array storing number of physical pins per bank */
    const uint8_t           *num_pins;
};
/** @} */
#endif
