//
// Copyright (c) 2021 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARAPS_AST_H_INC
#define ARAPS_AST_H_INC
#define NV_MOBILE_ARAPS_AST_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARAPS_AST_H_SCRREG_NOMENCLATURE INFERRED


// Register APS_AST_CONTROL_0
#define APS_AST_CONTROL_0                       MK_ADDR_CONST(0x0)
#define APS_AST_CONTROL_0_SECURE                        0x0
#define APS_AST_CONTROL_0_DUAL                  0x0
#define APS_AST_CONTROL_0_SCR                   AST_GBL_SEC_CONTROL_0
#define APS_AST_CONTROL_0_SCRREG                        APS_AST_SCR_AST_GBL_SEC_CONTROL_0
#define APS_AST_CONTROL_0_WORD_COUNT                    0x1
#define APS_AST_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1fc80000)
#define APS_AST_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0xffdf83e7)
#define APS_AST_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_READ_MASK                     MK_MASK_CONST(0xffdf83e7)
#define APS_AST_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0xffdf83e7)
#define APS_AST_CONTROL_0_ApbOvrOn_SHIFT                        MK_SHIFT_CONST(31)
#define APS_AST_CONTROL_0_ApbOvrOn_FIELD                        MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_ApbOvrOn_SHIFT)
#define APS_AST_CONTROL_0_ApbOvrOn_RANGE                        31:31
#define APS_AST_CONTROL_0_ApbOvrOn_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_CONTROL_0_ApbOvrOn_LSB                  MK_SHIFT_CONST(31)
#define APS_AST_CONTROL_0_ApbOvrOn_WOFFSET                      0x0
#define APS_AST_CONTROL_0_ApbOvrOn_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_ApbOvrOn_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define APS_AST_CONTROL_0_ApbOvrOn_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_ApbOvrOn_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_ApbOvrOn_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_ApbOvrOn_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define APS_AST_CONTROL_0_NicOvrOn_SHIFT                        MK_SHIFT_CONST(30)
#define APS_AST_CONTROL_0_NicOvrOn_FIELD                        MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_NicOvrOn_SHIFT)
#define APS_AST_CONTROL_0_NicOvrOn_RANGE                        30:30
#define APS_AST_CONTROL_0_NicOvrOn_MSB                  MK_SHIFT_CONST(30)
#define APS_AST_CONTROL_0_NicOvrOn_LSB                  MK_SHIFT_CONST(30)
#define APS_AST_CONTROL_0_NicOvrOn_WOFFSET                      0x0
#define APS_AST_CONTROL_0_NicOvrOn_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_NicOvrOn_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define APS_AST_CONTROL_0_NicOvrOn_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_NicOvrOn_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_NicOvrOn_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_NicOvrOn_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define APS_AST_CONTROL_0_CarveOutLock_SHIFT                    MK_SHIFT_CONST(20)
#define APS_AST_CONTROL_0_CarveOutLock_FIELD                    MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_CarveOutLock_SHIFT)
#define APS_AST_CONTROL_0_CarveOutLock_RANGE                    20:20
#define APS_AST_CONTROL_0_CarveOutLock_MSB                      MK_SHIFT_CONST(20)
#define APS_AST_CONTROL_0_CarveOutLock_LSB                      MK_SHIFT_CONST(20)
#define APS_AST_CONTROL_0_CarveOutLock_WOFFSET                  0x0
#define APS_AST_CONTROL_0_CarveOutLock_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_CarveOutLock_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define APS_AST_CONTROL_0_CarveOutLock_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_CarveOutLock_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_CarveOutLock_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_CarveOutLock_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define APS_AST_CONTROL_0_CarveOutLock_FALSE                    MK_ENUM_CONST(0)
#define APS_AST_CONTROL_0_CarveOutLock_TRUE                     MK_ENUM_CONST(1)

#define APS_AST_CONTROL_0_DefPhysical_SHIFT                     MK_SHIFT_CONST(19)
#define APS_AST_CONTROL_0_DefPhysical_FIELD                     MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_DefPhysical_SHIFT)
#define APS_AST_CONTROL_0_DefPhysical_RANGE                     19:19
#define APS_AST_CONTROL_0_DefPhysical_MSB                       MK_SHIFT_CONST(19)
#define APS_AST_CONTROL_0_DefPhysical_LSB                       MK_SHIFT_CONST(19)
#define APS_AST_CONTROL_0_DefPhysical_WOFFSET                   0x0
#define APS_AST_CONTROL_0_DefPhysical_DEFAULT                   MK_MASK_CONST(0x1)
#define APS_AST_CONTROL_0_DefPhysical_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_AST_CONTROL_0_DefPhysical_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefPhysical_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefPhysical_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefPhysical_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define APS_AST_CONTROL_0_DefVMIndex_SHIFT                      MK_SHIFT_CONST(15)
#define APS_AST_CONTROL_0_DefVMIndex_FIELD                      MK_FIELD_CONST(0xf, APS_AST_CONTROL_0_DefVMIndex_SHIFT)
#define APS_AST_CONTROL_0_DefVMIndex_RANGE                      18:15
#define APS_AST_CONTROL_0_DefVMIndex_MSB                        MK_SHIFT_CONST(18)
#define APS_AST_CONTROL_0_DefVMIndex_LSB                        MK_SHIFT_CONST(15)
#define APS_AST_CONTROL_0_DefVMIndex_WOFFSET                    0x0
#define APS_AST_CONTROL_0_DefVMIndex_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefVMIndex_DEFAULT_MASK                       MK_MASK_CONST(0xf)
#define APS_AST_CONTROL_0_DefVMIndex_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefVMIndex_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefVMIndex_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefVMIndex_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define APS_AST_CONTROL_0_DefCarveOutID_SHIFT                   MK_SHIFT_CONST(5)
#define APS_AST_CONTROL_0_DefCarveOutID_FIELD                   MK_FIELD_CONST(0x1f, APS_AST_CONTROL_0_DefCarveOutID_SHIFT)
#define APS_AST_CONTROL_0_DefCarveOutID_RANGE                   9:5
#define APS_AST_CONTROL_0_DefCarveOutID_MSB                     MK_SHIFT_CONST(9)
#define APS_AST_CONTROL_0_DefCarveOutID_LSB                     MK_SHIFT_CONST(5)
#define APS_AST_CONTROL_0_DefCarveOutID_WOFFSET                 0x0
#define APS_AST_CONTROL_0_DefCarveOutID_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefCarveOutID_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
#define APS_AST_CONTROL_0_DefCarveOutID_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefCarveOutID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefCarveOutID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefCarveOutID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_AST_CONTROL_0_DefSnoop_SHIFT                        MK_SHIFT_CONST(2)
#define APS_AST_CONTROL_0_DefSnoop_FIELD                        MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_DefSnoop_SHIFT)
#define APS_AST_CONTROL_0_DefSnoop_RANGE                        2:2
#define APS_AST_CONTROL_0_DefSnoop_MSB                  MK_SHIFT_CONST(2)
#define APS_AST_CONTROL_0_DefSnoop_LSB                  MK_SHIFT_CONST(2)
#define APS_AST_CONTROL_0_DefSnoop_WOFFSET                      0x0
#define APS_AST_CONTROL_0_DefSnoop_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefSnoop_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define APS_AST_CONTROL_0_DefSnoop_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefSnoop_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefSnoop_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_DefSnoop_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define APS_AST_CONTROL_0_DefSnoop_DISABLE                      MK_ENUM_CONST(0)
#define APS_AST_CONTROL_0_DefSnoop_ENABLE                       MK_ENUM_CONST(1)

#define APS_AST_CONTROL_0_MatchErrCtl_SHIFT                     MK_SHIFT_CONST(1)
#define APS_AST_CONTROL_0_MatchErrCtl_FIELD                     MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_MatchErrCtl_SHIFT)
#define APS_AST_CONTROL_0_MatchErrCtl_RANGE                     1:1
#define APS_AST_CONTROL_0_MatchErrCtl_MSB                       MK_SHIFT_CONST(1)
#define APS_AST_CONTROL_0_MatchErrCtl_LSB                       MK_SHIFT_CONST(1)
#define APS_AST_CONTROL_0_MatchErrCtl_WOFFSET                   0x0
#define APS_AST_CONTROL_0_MatchErrCtl_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_MatchErrCtl_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_AST_CONTROL_0_MatchErrCtl_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_MatchErrCtl_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_MatchErrCtl_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_MatchErrCtl_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define APS_AST_CONTROL_0_MatchErrCtl_NO_DECERR                 MK_ENUM_CONST(0)
#define APS_AST_CONTROL_0_MatchErrCtl_DECERR                    MK_ENUM_CONST(1)

#define APS_AST_CONTROL_0_Lock_SHIFT                    MK_SHIFT_CONST(0)
#define APS_AST_CONTROL_0_Lock_FIELD                    MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_Lock_SHIFT)
#define APS_AST_CONTROL_0_Lock_RANGE                    0:0
#define APS_AST_CONTROL_0_Lock_MSB                      MK_SHIFT_CONST(0)
#define APS_AST_CONTROL_0_Lock_LSB                      MK_SHIFT_CONST(0)
#define APS_AST_CONTROL_0_Lock_WOFFSET                  0x0
#define APS_AST_CONTROL_0_Lock_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_Lock_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define APS_AST_CONTROL_0_Lock_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_Lock_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_Lock_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define APS_AST_CONTROL_0_Lock_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define APS_AST_CONTROL_0_Lock_FALSE                    MK_ENUM_CONST(0)
#define APS_AST_CONTROL_0_Lock_TRUE                     MK_ENUM_CONST(1)


// Register APS_AST_ERROR_STATUS_0
#define APS_AST_ERROR_STATUS_0                  MK_ADDR_CONST(0x4)
#define APS_AST_ERROR_STATUS_0_SECURE                   0x0
#define APS_AST_ERROR_STATUS_0_DUAL                     0x0
#define APS_AST_ERROR_STATUS_0_SCR                      AST_GBL_SEC_CONTROL_0
#define APS_AST_ERROR_STATUS_0_SCRREG                   APS_AST_SCR_AST_GBL_SEC_CONTROL_0
#define APS_AST_ERROR_STATUS_0_WORD_COUNT                       0x1
#define APS_AST_ERROR_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
#define APS_AST_ERROR_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
#define APS_AST_ERROR_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x1)
#define APS_AST_ERROR_STATUS_0_Overflow_SHIFT                   MK_SHIFT_CONST(2)
#define APS_AST_ERROR_STATUS_0_Overflow_FIELD                   MK_FIELD_CONST(0x1, APS_AST_ERROR_STATUS_0_Overflow_SHIFT)
#define APS_AST_ERROR_STATUS_0_Overflow_RANGE                   2:2
#define APS_AST_ERROR_STATUS_0_Overflow_MSB                     MK_SHIFT_CONST(2)
#define APS_AST_ERROR_STATUS_0_Overflow_LSB                     MK_SHIFT_CONST(2)
#define APS_AST_ERROR_STATUS_0_Overflow_WOFFSET                 0x0
#define APS_AST_ERROR_STATUS_0_Overflow_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_Overflow_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_ERROR_STATUS_0_Overflow_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_Overflow_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_Overflow_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_Overflow_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_AST_ERROR_STATUS_0_VMIndxErr_SHIFT                  MK_SHIFT_CONST(1)
#define APS_AST_ERROR_STATUS_0_VMIndxErr_FIELD                  MK_FIELD_CONST(0x1, APS_AST_ERROR_STATUS_0_VMIndxErr_SHIFT)
#define APS_AST_ERROR_STATUS_0_VMIndxErr_RANGE                  1:1
#define APS_AST_ERROR_STATUS_0_VMIndxErr_MSB                    MK_SHIFT_CONST(1)
#define APS_AST_ERROR_STATUS_0_VMIndxErr_LSB                    MK_SHIFT_CONST(1)
#define APS_AST_ERROR_STATUS_0_VMIndxErr_WOFFSET                        0x0
#define APS_AST_ERROR_STATUS_0_VMIndxErr_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_VMIndxErr_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define APS_AST_ERROR_STATUS_0_VMIndxErr_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_VMIndxErr_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_VMIndxErr_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_VMIndxErr_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_ERROR_STATUS_0_Valid_SHIFT                      MK_SHIFT_CONST(0)
#define APS_AST_ERROR_STATUS_0_Valid_FIELD                      MK_FIELD_CONST(0x1, APS_AST_ERROR_STATUS_0_Valid_SHIFT)
#define APS_AST_ERROR_STATUS_0_Valid_RANGE                      0:0
#define APS_AST_ERROR_STATUS_0_Valid_MSB                        MK_SHIFT_CONST(0)
#define APS_AST_ERROR_STATUS_0_Valid_LSB                        MK_SHIFT_CONST(0)
#define APS_AST_ERROR_STATUS_0_Valid_WOFFSET                    0x0
#define APS_AST_ERROR_STATUS_0_Valid_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_Valid_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define APS_AST_ERROR_STATUS_0_Valid_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_Valid_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_Valid_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define APS_AST_ERROR_STATUS_0_Valid_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register APS_AST_ERROR_ADDR_LO_0
#define APS_AST_ERROR_ADDR_LO_0                 MK_ADDR_CONST(0x8)
#define APS_AST_ERROR_ADDR_LO_0_SECURE                  0x0
#define APS_AST_ERROR_ADDR_LO_0_DUAL                    0x0
#define APS_AST_ERROR_ADDR_LO_0_SCR                     AST_GBL_SEC_CONTROL_0
#define APS_AST_ERROR_ADDR_LO_0_SCRREG                  APS_AST_SCR_AST_GBL_SEC_CONTROL_0
#define APS_AST_ERROR_ADDR_LO_0_WORD_COUNT                      0x1
#define APS_AST_ERROR_ADDR_LO_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_LO_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_AST_ERROR_ADDR_LO_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_LO_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_LO_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_AST_ERROR_ADDR_LO_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_SHIFT                 MK_SHIFT_CONST(0)
#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_FIELD                 MK_FIELD_CONST(0xffffffff, APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_SHIFT)
#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_RANGE                 31:0
#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_MSB                   MK_SHIFT_CONST(31)
#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_LSB                   MK_SHIFT_CONST(0)
#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_WOFFSET                       0x0
#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register APS_AST_ERROR_ADDR_HI_0
#define APS_AST_ERROR_ADDR_HI_0                 MK_ADDR_CONST(0xc)
#define APS_AST_ERROR_ADDR_HI_0_SECURE                  0x0
#define APS_AST_ERROR_ADDR_HI_0_DUAL                    0x0
#define APS_AST_ERROR_ADDR_HI_0_SCR                     AST_GBL_SEC_CONTROL_0
#define APS_AST_ERROR_ADDR_HI_0_SCRREG                  APS_AST_SCR_AST_GBL_SEC_CONTROL_0
#define APS_AST_ERROR_ADDR_HI_0_WORD_COUNT                      0x1
#define APS_AST_ERROR_ADDR_HI_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_HI_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_AST_ERROR_ADDR_HI_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_HI_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_HI_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_AST_ERROR_ADDR_HI_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_SHIFT                 MK_SHIFT_CONST(0)
#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_FIELD                 MK_FIELD_CONST(0xffffffff, APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_SHIFT)
#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_RANGE                 31:0
#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_MSB                   MK_SHIFT_CONST(31)
#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_LSB                   MK_SHIFT_CONST(0)
#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_WOFFSET                       0x0
#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register APS_AST_STREAMID_CTL_0
#define APS_AST_STREAMID_CTL_0                  MK_ADDR_CONST(0x20)
#define APS_AST_STREAMID_CTL_0_SECURE                   0x0
#define APS_AST_STREAMID_CTL_0_DUAL                     0x0
#define APS_AST_STREAMID_CTL_0_SCR                      AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_0_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_0_WORD_COUNT                       0x1
#define APS_AST_STREAMID_CTL_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_0_RESET_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_0_READ_MASK                        MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_0_WRITE_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_0_StreamID_SHIFT                   MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_0_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_0_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_0_StreamID_RANGE                   15:8
#define APS_AST_STREAMID_CTL_0_StreamID_MSB                     MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_0_StreamID_LSB                     MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_0_StreamID_WOFFSET                 0x0
#define APS_AST_STREAMID_CTL_0_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_0_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_0_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_0_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_0_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_0_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_0_Enable_SHIFT                     MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_0_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_0_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_0_Enable_RANGE                     0:0
#define APS_AST_STREAMID_CTL_0_Enable_MSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_0_Enable_LSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_0_Enable_WOFFSET                   0x0
#define APS_AST_STREAMID_CTL_0_Enable_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_0_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_0_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_0_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_0_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_0_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_0_Enable_DISABLE                   MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_0_Enable_ENABLE                    MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL
#define APS_AST_STREAMID_CTL                    MK_ADDR_CONST(0x20)
#define APS_AST_STREAMID_CTL_SECURE                     0x0
#define APS_AST_STREAMID_CTL_DUAL                       0x0
#define APS_AST_STREAMID_CTL_SCR                        AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_SCRREG                     APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_WORD_COUNT                         0x1
#define APS_AST_STREAMID_CTL_RESET_VAL                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_RESET_MASK                         MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_READ_MASK                  MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_WRITE_MASK                         MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_StreamID_SHIFT                     MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_StreamID_FIELD                     MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_StreamID_RANGE                     15:8
#define APS_AST_STREAMID_CTL_StreamID_MSB                       MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_StreamID_LSB                       MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_StreamID_WOFFSET                   0x0
#define APS_AST_STREAMID_CTL_StreamID_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_StreamID_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_StreamID_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_StreamID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_StreamID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_StreamID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_Enable_SHIFT                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_Enable_FIELD                       MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_Enable_RANGE                       0:0
#define APS_AST_STREAMID_CTL_Enable_MSB                 MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_Enable_LSB                 MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_Enable_WOFFSET                     0x0
#define APS_AST_STREAMID_CTL_Enable_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_Enable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_Enable_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_Enable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_Enable_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_Enable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_Enable_DISABLE                     MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_Enable_ENABLE                      MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_1
#define APS_AST_STREAMID_CTL_1                  MK_ADDR_CONST(0x24)
#define APS_AST_STREAMID_CTL_1_SECURE                   0x0
#define APS_AST_STREAMID_CTL_1_DUAL                     0x0
#define APS_AST_STREAMID_CTL_1_SCR                      AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_1_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_1_WORD_COUNT                       0x1
#define APS_AST_STREAMID_CTL_1_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_1_RESET_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_1_READ_MASK                        MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_1_WRITE_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_1_StreamID_SHIFT                   MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_1_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_1_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_1_StreamID_RANGE                   15:8
#define APS_AST_STREAMID_CTL_1_StreamID_MSB                     MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_1_StreamID_LSB                     MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_1_StreamID_WOFFSET                 0x0
#define APS_AST_STREAMID_CTL_1_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_1_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_1_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_1_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_1_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_1_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_1_Enable_SHIFT                     MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_1_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_1_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_1_Enable_RANGE                     0:0
#define APS_AST_STREAMID_CTL_1_Enable_MSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_1_Enable_LSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_1_Enable_WOFFSET                   0x0
#define APS_AST_STREAMID_CTL_1_Enable_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_1_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_1_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_1_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_1_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_1_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_1_Enable_DISABLE                   MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_1_Enable_ENABLE                    MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_2
#define APS_AST_STREAMID_CTL_2                  MK_ADDR_CONST(0x28)
#define APS_AST_STREAMID_CTL_2_SECURE                   0x0
#define APS_AST_STREAMID_CTL_2_DUAL                     0x0
#define APS_AST_STREAMID_CTL_2_SCR                      AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_2_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_2_WORD_COUNT                       0x1
#define APS_AST_STREAMID_CTL_2_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_2_RESET_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_2_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_2_READ_MASK                        MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_2_WRITE_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_2_StreamID_SHIFT                   MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_2_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_2_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_2_StreamID_RANGE                   15:8
#define APS_AST_STREAMID_CTL_2_StreamID_MSB                     MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_2_StreamID_LSB                     MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_2_StreamID_WOFFSET                 0x0
#define APS_AST_STREAMID_CTL_2_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_2_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_2_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_2_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_2_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_2_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_2_Enable_SHIFT                     MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_2_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_2_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_2_Enable_RANGE                     0:0
#define APS_AST_STREAMID_CTL_2_Enable_MSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_2_Enable_LSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_2_Enable_WOFFSET                   0x0
#define APS_AST_STREAMID_CTL_2_Enable_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_2_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_2_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_2_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_2_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_2_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_2_Enable_DISABLE                   MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_2_Enable_ENABLE                    MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_3
#define APS_AST_STREAMID_CTL_3                  MK_ADDR_CONST(0x2c)
#define APS_AST_STREAMID_CTL_3_SECURE                   0x0
#define APS_AST_STREAMID_CTL_3_DUAL                     0x0
#define APS_AST_STREAMID_CTL_3_SCR                      AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_3_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_3_WORD_COUNT                       0x1
#define APS_AST_STREAMID_CTL_3_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_3_RESET_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_3_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_3_READ_MASK                        MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_3_WRITE_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_3_StreamID_SHIFT                   MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_3_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_3_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_3_StreamID_RANGE                   15:8
#define APS_AST_STREAMID_CTL_3_StreamID_MSB                     MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_3_StreamID_LSB                     MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_3_StreamID_WOFFSET                 0x0
#define APS_AST_STREAMID_CTL_3_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_3_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_3_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_3_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_3_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_3_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_3_Enable_SHIFT                     MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_3_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_3_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_3_Enable_RANGE                     0:0
#define APS_AST_STREAMID_CTL_3_Enable_MSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_3_Enable_LSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_3_Enable_WOFFSET                   0x0
#define APS_AST_STREAMID_CTL_3_Enable_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_3_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_3_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_3_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_3_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_3_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_3_Enable_DISABLE                   MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_3_Enable_ENABLE                    MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_4
#define APS_AST_STREAMID_CTL_4                  MK_ADDR_CONST(0x30)
#define APS_AST_STREAMID_CTL_4_SECURE                   0x0
#define APS_AST_STREAMID_CTL_4_DUAL                     0x0
#define APS_AST_STREAMID_CTL_4_SCR                      AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_4_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_4_WORD_COUNT                       0x1
#define APS_AST_STREAMID_CTL_4_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_4_RESET_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_4_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_4_READ_MASK                        MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_4_WRITE_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_4_StreamID_SHIFT                   MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_4_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_4_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_4_StreamID_RANGE                   15:8
#define APS_AST_STREAMID_CTL_4_StreamID_MSB                     MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_4_StreamID_LSB                     MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_4_StreamID_WOFFSET                 0x0
#define APS_AST_STREAMID_CTL_4_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_4_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_4_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_4_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_4_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_4_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_4_Enable_SHIFT                     MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_4_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_4_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_4_Enable_RANGE                     0:0
#define APS_AST_STREAMID_CTL_4_Enable_MSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_4_Enable_LSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_4_Enable_WOFFSET                   0x0
#define APS_AST_STREAMID_CTL_4_Enable_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_4_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_4_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_4_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_4_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_4_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_4_Enable_DISABLE                   MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_4_Enable_ENABLE                    MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_5
#define APS_AST_STREAMID_CTL_5                  MK_ADDR_CONST(0x34)
#define APS_AST_STREAMID_CTL_5_SECURE                   0x0
#define APS_AST_STREAMID_CTL_5_DUAL                     0x0
#define APS_AST_STREAMID_CTL_5_SCR                      AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_5_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_5_WORD_COUNT                       0x1
#define APS_AST_STREAMID_CTL_5_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_5_RESET_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_5_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_5_READ_MASK                        MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_5_WRITE_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_5_StreamID_SHIFT                   MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_5_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_5_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_5_StreamID_RANGE                   15:8
#define APS_AST_STREAMID_CTL_5_StreamID_MSB                     MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_5_StreamID_LSB                     MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_5_StreamID_WOFFSET                 0x0
#define APS_AST_STREAMID_CTL_5_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_5_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_5_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_5_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_5_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_5_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_5_Enable_SHIFT                     MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_5_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_5_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_5_Enable_RANGE                     0:0
#define APS_AST_STREAMID_CTL_5_Enable_MSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_5_Enable_LSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_5_Enable_WOFFSET                   0x0
#define APS_AST_STREAMID_CTL_5_Enable_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_5_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_5_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_5_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_5_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_5_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_5_Enable_DISABLE                   MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_5_Enable_ENABLE                    MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_6
#define APS_AST_STREAMID_CTL_6                  MK_ADDR_CONST(0x38)
#define APS_AST_STREAMID_CTL_6_SECURE                   0x0
#define APS_AST_STREAMID_CTL_6_DUAL                     0x0
#define APS_AST_STREAMID_CTL_6_SCR                      AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_6_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_6_WORD_COUNT                       0x1
#define APS_AST_STREAMID_CTL_6_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_6_RESET_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_6_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_6_READ_MASK                        MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_6_WRITE_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_6_StreamID_SHIFT                   MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_6_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_6_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_6_StreamID_RANGE                   15:8
#define APS_AST_STREAMID_CTL_6_StreamID_MSB                     MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_6_StreamID_LSB                     MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_6_StreamID_WOFFSET                 0x0
#define APS_AST_STREAMID_CTL_6_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_6_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_6_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_6_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_6_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_6_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_6_Enable_SHIFT                     MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_6_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_6_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_6_Enable_RANGE                     0:0
#define APS_AST_STREAMID_CTL_6_Enable_MSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_6_Enable_LSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_6_Enable_WOFFSET                   0x0
#define APS_AST_STREAMID_CTL_6_Enable_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_6_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_6_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_6_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_6_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_6_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_6_Enable_DISABLE                   MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_6_Enable_ENABLE                    MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_7
#define APS_AST_STREAMID_CTL_7                  MK_ADDR_CONST(0x3c)
#define APS_AST_STREAMID_CTL_7_SECURE                   0x0
#define APS_AST_STREAMID_CTL_7_DUAL                     0x0
#define APS_AST_STREAMID_CTL_7_SCR                      AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_7_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_7_WORD_COUNT                       0x1
#define APS_AST_STREAMID_CTL_7_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_7_RESET_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_7_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_7_READ_MASK                        MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_7_WRITE_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_7_StreamID_SHIFT                   MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_7_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_7_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_7_StreamID_RANGE                   15:8
#define APS_AST_STREAMID_CTL_7_StreamID_MSB                     MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_7_StreamID_LSB                     MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_7_StreamID_WOFFSET                 0x0
#define APS_AST_STREAMID_CTL_7_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_7_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_7_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_7_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_7_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_7_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_7_Enable_SHIFT                     MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_7_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_7_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_7_Enable_RANGE                     0:0
#define APS_AST_STREAMID_CTL_7_Enable_MSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_7_Enable_LSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_7_Enable_WOFFSET                   0x0
#define APS_AST_STREAMID_CTL_7_Enable_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_7_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_7_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_7_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_7_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_7_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_7_Enable_DISABLE                   MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_7_Enable_ENABLE                    MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_8
#define APS_AST_STREAMID_CTL_8                  MK_ADDR_CONST(0x40)
#define APS_AST_STREAMID_CTL_8_SECURE                   0x0
#define APS_AST_STREAMID_CTL_8_DUAL                     0x0
#define APS_AST_STREAMID_CTL_8_SCR                      AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_8_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_8_WORD_COUNT                       0x1
#define APS_AST_STREAMID_CTL_8_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_8_RESET_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_8_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_8_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_8_READ_MASK                        MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_8_WRITE_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_8_StreamID_SHIFT                   MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_8_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_8_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_8_StreamID_RANGE                   15:8
#define APS_AST_STREAMID_CTL_8_StreamID_MSB                     MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_8_StreamID_LSB                     MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_8_StreamID_WOFFSET                 0x0
#define APS_AST_STREAMID_CTL_8_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_8_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_8_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_8_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_8_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_8_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_8_Enable_SHIFT                     MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_8_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_8_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_8_Enable_RANGE                     0:0
#define APS_AST_STREAMID_CTL_8_Enable_MSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_8_Enable_LSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_8_Enable_WOFFSET                   0x0
#define APS_AST_STREAMID_CTL_8_Enable_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_8_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_8_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_8_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_8_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_8_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_8_Enable_DISABLE                   MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_8_Enable_ENABLE                    MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_9
#define APS_AST_STREAMID_CTL_9                  MK_ADDR_CONST(0x44)
#define APS_AST_STREAMID_CTL_9_SECURE                   0x0
#define APS_AST_STREAMID_CTL_9_DUAL                     0x0
#define APS_AST_STREAMID_CTL_9_SCR                      AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_9_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_9_WORD_COUNT                       0x1
#define APS_AST_STREAMID_CTL_9_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_9_RESET_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_9_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_9_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_9_READ_MASK                        MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_9_WRITE_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_9_StreamID_SHIFT                   MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_9_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_9_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_9_StreamID_RANGE                   15:8
#define APS_AST_STREAMID_CTL_9_StreamID_MSB                     MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_9_StreamID_LSB                     MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_9_StreamID_WOFFSET                 0x0
#define APS_AST_STREAMID_CTL_9_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_9_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_9_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_9_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_9_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_9_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_9_Enable_SHIFT                     MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_9_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_9_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_9_Enable_RANGE                     0:0
#define APS_AST_STREAMID_CTL_9_Enable_MSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_9_Enable_LSB                       MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_9_Enable_WOFFSET                   0x0
#define APS_AST_STREAMID_CTL_9_Enable_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_9_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_9_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_9_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_9_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_9_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_9_Enable_DISABLE                   MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_9_Enable_ENABLE                    MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_10
#define APS_AST_STREAMID_CTL_10                 MK_ADDR_CONST(0x48)
#define APS_AST_STREAMID_CTL_10_SECURE                  0x0
#define APS_AST_STREAMID_CTL_10_DUAL                    0x0
#define APS_AST_STREAMID_CTL_10_SCR                     AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_10_SCRREG                  APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_10_WORD_COUNT                      0x1
#define APS_AST_STREAMID_CTL_10_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_10_RESET_MASK                      MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_10_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_10_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_10_READ_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_10_WRITE_MASK                      MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_10_StreamID_SHIFT                  MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_10_StreamID_FIELD                  MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_10_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_10_StreamID_RANGE                  15:8
#define APS_AST_STREAMID_CTL_10_StreamID_MSB                    MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_10_StreamID_LSB                    MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_10_StreamID_WOFFSET                        0x0
#define APS_AST_STREAMID_CTL_10_StreamID_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_10_StreamID_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_10_StreamID_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_10_StreamID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_10_StreamID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_10_StreamID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_10_Enable_SHIFT                    MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_10_Enable_FIELD                    MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_10_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_10_Enable_RANGE                    0:0
#define APS_AST_STREAMID_CTL_10_Enable_MSB                      MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_10_Enable_LSB                      MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_10_Enable_WOFFSET                  0x0
#define APS_AST_STREAMID_CTL_10_Enable_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_10_Enable_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_10_Enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_10_Enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_10_Enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_10_Enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_10_Enable_DISABLE                  MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_10_Enable_ENABLE                   MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_11
#define APS_AST_STREAMID_CTL_11                 MK_ADDR_CONST(0x4c)
#define APS_AST_STREAMID_CTL_11_SECURE                  0x0
#define APS_AST_STREAMID_CTL_11_DUAL                    0x0
#define APS_AST_STREAMID_CTL_11_SCR                     AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_11_SCRREG                  APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_11_WORD_COUNT                      0x1
#define APS_AST_STREAMID_CTL_11_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_11_RESET_MASK                      MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_11_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_11_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_11_READ_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_11_WRITE_MASK                      MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_11_StreamID_SHIFT                  MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_11_StreamID_FIELD                  MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_11_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_11_StreamID_RANGE                  15:8
#define APS_AST_STREAMID_CTL_11_StreamID_MSB                    MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_11_StreamID_LSB                    MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_11_StreamID_WOFFSET                        0x0
#define APS_AST_STREAMID_CTL_11_StreamID_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_11_StreamID_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_11_StreamID_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_11_StreamID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_11_StreamID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_11_StreamID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_11_Enable_SHIFT                    MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_11_Enable_FIELD                    MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_11_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_11_Enable_RANGE                    0:0
#define APS_AST_STREAMID_CTL_11_Enable_MSB                      MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_11_Enable_LSB                      MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_11_Enable_WOFFSET                  0x0
#define APS_AST_STREAMID_CTL_11_Enable_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_11_Enable_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_11_Enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_11_Enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_11_Enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_11_Enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_11_Enable_DISABLE                  MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_11_Enable_ENABLE                   MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_12
#define APS_AST_STREAMID_CTL_12                 MK_ADDR_CONST(0x50)
#define APS_AST_STREAMID_CTL_12_SECURE                  0x0
#define APS_AST_STREAMID_CTL_12_DUAL                    0x0
#define APS_AST_STREAMID_CTL_12_SCR                     AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_12_SCRREG                  APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_12_WORD_COUNT                      0x1
#define APS_AST_STREAMID_CTL_12_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_12_RESET_MASK                      MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_12_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_12_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_12_READ_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_12_WRITE_MASK                      MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_12_StreamID_SHIFT                  MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_12_StreamID_FIELD                  MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_12_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_12_StreamID_RANGE                  15:8
#define APS_AST_STREAMID_CTL_12_StreamID_MSB                    MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_12_StreamID_LSB                    MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_12_StreamID_WOFFSET                        0x0
#define APS_AST_STREAMID_CTL_12_StreamID_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_12_StreamID_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_12_StreamID_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_12_StreamID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_12_StreamID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_12_StreamID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_12_Enable_SHIFT                    MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_12_Enable_FIELD                    MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_12_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_12_Enable_RANGE                    0:0
#define APS_AST_STREAMID_CTL_12_Enable_MSB                      MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_12_Enable_LSB                      MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_12_Enable_WOFFSET                  0x0
#define APS_AST_STREAMID_CTL_12_Enable_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_12_Enable_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_12_Enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_12_Enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_12_Enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_12_Enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_12_Enable_DISABLE                  MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_12_Enable_ENABLE                   MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_13
#define APS_AST_STREAMID_CTL_13                 MK_ADDR_CONST(0x54)
#define APS_AST_STREAMID_CTL_13_SECURE                  0x0
#define APS_AST_STREAMID_CTL_13_DUAL                    0x0
#define APS_AST_STREAMID_CTL_13_SCR                     AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_13_SCRREG                  APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_13_WORD_COUNT                      0x1
#define APS_AST_STREAMID_CTL_13_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_13_RESET_MASK                      MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_13_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_13_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_13_READ_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_13_WRITE_MASK                      MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_13_StreamID_SHIFT                  MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_13_StreamID_FIELD                  MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_13_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_13_StreamID_RANGE                  15:8
#define APS_AST_STREAMID_CTL_13_StreamID_MSB                    MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_13_StreamID_LSB                    MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_13_StreamID_WOFFSET                        0x0
#define APS_AST_STREAMID_CTL_13_StreamID_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_13_StreamID_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_13_StreamID_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_13_StreamID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_13_StreamID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_13_StreamID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_13_Enable_SHIFT                    MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_13_Enable_FIELD                    MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_13_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_13_Enable_RANGE                    0:0
#define APS_AST_STREAMID_CTL_13_Enable_MSB                      MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_13_Enable_LSB                      MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_13_Enable_WOFFSET                  0x0
#define APS_AST_STREAMID_CTL_13_Enable_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_13_Enable_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_13_Enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_13_Enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_13_Enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_13_Enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_13_Enable_DISABLE                  MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_13_Enable_ENABLE                   MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_14
#define APS_AST_STREAMID_CTL_14                 MK_ADDR_CONST(0x58)
#define APS_AST_STREAMID_CTL_14_SECURE                  0x0
#define APS_AST_STREAMID_CTL_14_DUAL                    0x0
#define APS_AST_STREAMID_CTL_14_SCR                     AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_14_SCRREG                  APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_14_WORD_COUNT                      0x1
#define APS_AST_STREAMID_CTL_14_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_14_RESET_MASK                      MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_14_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_14_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_14_READ_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_14_WRITE_MASK                      MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_14_StreamID_SHIFT                  MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_14_StreamID_FIELD                  MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_14_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_14_StreamID_RANGE                  15:8
#define APS_AST_STREAMID_CTL_14_StreamID_MSB                    MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_14_StreamID_LSB                    MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_14_StreamID_WOFFSET                        0x0
#define APS_AST_STREAMID_CTL_14_StreamID_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_14_StreamID_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_14_StreamID_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_14_StreamID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_14_StreamID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_14_StreamID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_14_Enable_SHIFT                    MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_14_Enable_FIELD                    MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_14_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_14_Enable_RANGE                    0:0
#define APS_AST_STREAMID_CTL_14_Enable_MSB                      MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_14_Enable_LSB                      MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_14_Enable_WOFFSET                  0x0
#define APS_AST_STREAMID_CTL_14_Enable_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_14_Enable_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_14_Enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_14_Enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_14_Enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_14_Enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_14_Enable_DISABLE                  MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_14_Enable_ENABLE                   MK_ENUM_CONST(1)


// Register APS_AST_STREAMID_CTL_15
#define APS_AST_STREAMID_CTL_15                 MK_ADDR_CONST(0x5c)
#define APS_AST_STREAMID_CTL_15_SECURE                  0x0
#define APS_AST_STREAMID_CTL_15_DUAL                    0x0
#define APS_AST_STREAMID_CTL_15_SCR                     AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_15_SCRREG                  APS_AST_SCR_AST_HYP_SEC_CONTROL_0
#define APS_AST_STREAMID_CTL_15_WORD_COUNT                      0x1
#define APS_AST_STREAMID_CTL_15_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_15_RESET_MASK                      MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_15_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_15_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_15_READ_MASK                       MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_15_WRITE_MASK                      MK_MASK_CONST(0xff01)
#define APS_AST_STREAMID_CTL_15_StreamID_SHIFT                  MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_15_StreamID_FIELD                  MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_15_StreamID_SHIFT)
#define APS_AST_STREAMID_CTL_15_StreamID_RANGE                  15:8
#define APS_AST_STREAMID_CTL_15_StreamID_MSB                    MK_SHIFT_CONST(15)
#define APS_AST_STREAMID_CTL_15_StreamID_LSB                    MK_SHIFT_CONST(8)
#define APS_AST_STREAMID_CTL_15_StreamID_WOFFSET                        0x0
#define APS_AST_STREAMID_CTL_15_StreamID_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_15_StreamID_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define APS_AST_STREAMID_CTL_15_StreamID_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_15_StreamID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_15_StreamID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_15_StreamID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_STREAMID_CTL_15_Enable_SHIFT                    MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_15_Enable_FIELD                    MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_15_Enable_SHIFT)
#define APS_AST_STREAMID_CTL_15_Enable_RANGE                    0:0
#define APS_AST_STREAMID_CTL_15_Enable_MSB                      MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_15_Enable_LSB                      MK_SHIFT_CONST(0)
#define APS_AST_STREAMID_CTL_15_Enable_WOFFSET                  0x0
#define APS_AST_STREAMID_CTL_15_Enable_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_15_Enable_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_15_Enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_15_Enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_15_Enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define APS_AST_STREAMID_CTL_15_Enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define APS_AST_STREAMID_CTL_15_Enable_DISABLE                  MK_ENUM_CONST(0)
#define APS_AST_STREAMID_CTL_15_Enable_ENABLE                   MK_ENUM_CONST(1)


// Register APS_AST_WRITE_BLOCK_STATUS_0
#define APS_AST_WRITE_BLOCK_STATUS_0                    MK_ADDR_CONST(0x60)
#define APS_AST_WRITE_BLOCK_STATUS_0_SECURE                     0x0
#define APS_AST_WRITE_BLOCK_STATUS_0_DUAL                       0x0
#define APS_AST_WRITE_BLOCK_STATUS_0_SCR                        AST_GBL_SEC_CONTROL_0
#define APS_AST_WRITE_BLOCK_STATUS_0_SCRREG                     APS_AST_SCR_AST_GBL_SEC_CONTROL_0
#define APS_AST_WRITE_BLOCK_STATUS_0_WORD_COUNT                         0x1
#define APS_AST_WRITE_BLOCK_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define APS_AST_WRITE_BLOCK_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define APS_AST_WRITE_BLOCK_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_WRITE_BLOCK_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_AST_WRITE_BLOCK_STATUS_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_SHIFT)
#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_RANGE                   31:0
#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_WOFFSET                 0x0
#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_READ_BLOCK_STATUS_0
#define APS_AST_READ_BLOCK_STATUS_0                     MK_ADDR_CONST(0x64)
#define APS_AST_READ_BLOCK_STATUS_0_SECURE                      0x0
#define APS_AST_READ_BLOCK_STATUS_0_DUAL                        0x0
#define APS_AST_READ_BLOCK_STATUS_0_SCR                         AST_GBL_SEC_CONTROL_0
#define APS_AST_READ_BLOCK_STATUS_0_SCRREG                      APS_AST_SCR_AST_GBL_SEC_CONTROL_0
#define APS_AST_READ_BLOCK_STATUS_0_WORD_COUNT                  0x1
#define APS_AST_READ_BLOCK_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define APS_AST_READ_BLOCK_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_READ_BLOCK_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_READ_BLOCK_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_AST_READ_BLOCK_STATUS_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_READ_BLOCK_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_SHIFT                     MK_SHIFT_CONST(0)
#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_FIELD                     MK_FIELD_CONST(0xffffffff, APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_SHIFT)
#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_RANGE                     31:0
#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_MSB                       MK_SHIFT_CONST(31)
#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_LSB                       MK_SHIFT_CONST(0)
#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_WOFFSET                   0x0
#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_AST_REGION_0_SLAVE_BASE_LO_0
#define APS_AST_REGION_0_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x100)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SECURE                         0x0
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_DUAL                   0x0
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SCR                    AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_SHIFT)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_SHIFT)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_0_SLAVE_BASE_HI_0
#define APS_AST_REGION_0_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x104)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SECURE                         0x0
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_DUAL                   0x0
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SCR                    AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_SHIFT)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register APS_AST_REGION_0_MASK_LO_0
#define APS_AST_REGION_0_MASK_LO_0                      MK_ADDR_CONST(0x108)
#define APS_AST_REGION_0_MASK_LO_0_SECURE                       0x0
#define APS_AST_REGION_0_MASK_LO_0_DUAL                         0x0
#define APS_AST_REGION_0_MASK_LO_0_SCR                  AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_MASK_LO_0_WORD_COUNT                   0x1
#define APS_AST_REGION_0_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_0_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_0_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_0_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
#define APS_AST_REGION_0_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_0_MASK_LO_0_Mask_SHIFT)
#define APS_AST_REGION_0_MASK_LO_0_Mask_RANGE                   31:12
#define APS_AST_REGION_0_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_0_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
#define APS_AST_REGION_0_MASK_LO_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_0_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_0_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_0_MASK_HI_0
#define APS_AST_REGION_0_MASK_HI_0                      MK_ADDR_CONST(0x10c)
#define APS_AST_REGION_0_MASK_HI_0_SECURE                       0x0
#define APS_AST_REGION_0_MASK_HI_0_DUAL                         0x0
#define APS_AST_REGION_0_MASK_HI_0_SCR                  AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_MASK_HI_0_WORD_COUNT                   0x1
#define APS_AST_REGION_0_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_0_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_0_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_0_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_0_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_0_MASK_HI_0_Mask_SHIFT)
#define APS_AST_REGION_0_MASK_HI_0_Mask_RANGE                   31:0
#define APS_AST_REGION_0_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_0_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_0_MASK_HI_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_0_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_0_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_0_MASTER_BASE_LO_0
#define APS_AST_REGION_0_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x110)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_SECURE                        0x0
#define APS_AST_REGION_0_MASTER_BASE_LO_0_DUAL                  0x0
#define APS_AST_REGION_0_MASTER_BASE_LO_0_SCR                   AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_MASTER_BASE_LO_0_WORD_COUNT                    0x1
#define APS_AST_REGION_0_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_SHIFT)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_0_MASTER_BASE_HI_0
#define APS_AST_REGION_0_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x114)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_SECURE                        0x0
#define APS_AST_REGION_0_MASTER_BASE_HI_0_DUAL                  0x0
#define APS_AST_REGION_0_MASTER_BASE_HI_0_SCR                   AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_MASTER_BASE_HI_0_WORD_COUNT                    0x1
#define APS_AST_REGION_0_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_SHIFT)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_0_CONTROL_0
#define APS_AST_REGION_0_CONTROL_0                      MK_ADDR_CONST(0x118)
#define APS_AST_REGION_0_CONTROL_0_SECURE                       0x0
#define APS_AST_REGION_0_CONTROL_0_DUAL                         0x0
#define APS_AST_REGION_0_CONTROL_0_SCR                  AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
#define APS_AST_REGION_0_CONTROL_0_WORD_COUNT                   0x1
#define APS_AST_REGION_0_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_0_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_0_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_0_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
#define APS_AST_REGION_0_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_0_CONTROL_0_Physical_SHIFT)
#define APS_AST_REGION_0_CONTROL_0_Physical_RANGE                       19:19
#define APS_AST_REGION_0_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_0_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_0_CONTROL_0_Physical_WOFFSET                     0x0
#define APS_AST_REGION_0_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define APS_AST_REGION_0_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define APS_AST_REGION_0_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
#define APS_AST_REGION_0_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_0_CONTROL_0_VMIndex_SHIFT)
#define APS_AST_REGION_0_CONTROL_0_VMIndex_RANGE                        18:15
#define APS_AST_REGION_0_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
#define APS_AST_REGION_0_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
#define APS_AST_REGION_0_CONTROL_0_VMIndex_WOFFSET                      0x0
#define APS_AST_REGION_0_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define APS_AST_REGION_0_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define APS_AST_REGION_0_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
#define APS_AST_REGION_0_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_0_CONTROL_0_CarveOutID_SHIFT)
#define APS_AST_REGION_0_CONTROL_0_CarveOutID_RANGE                     9:5
#define APS_AST_REGION_0_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
#define APS_AST_REGION_0_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
#define APS_AST_REGION_0_CONTROL_0_CarveOutID_WOFFSET                   0x0
#define APS_AST_REGION_0_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define APS_AST_REGION_0_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define APS_AST_REGION_0_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
#define APS_AST_REGION_0_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_0_CONTROL_0_Snoop_SHIFT)
#define APS_AST_REGION_0_CONTROL_0_Snoop_RANGE                  2:2
#define APS_AST_REGION_0_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_0_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_0_CONTROL_0_Snoop_WOFFSET                        0x0
#define APS_AST_REGION_0_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define APS_AST_REGION_0_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define APS_AST_REGION_0_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
#define APS_AST_REGION_0_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)

#define APS_AST_REGION_0_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_0_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_0_CONTROL_0_Lock_SHIFT)
#define APS_AST_REGION_0_CONTROL_0_Lock_RANGE                   0:0
#define APS_AST_REGION_0_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_0_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_0_CONTROL_0_Lock_WOFFSET                 0x0
#define APS_AST_REGION_0_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_0_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_0_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_0_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_0_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_1_SLAVE_BASE_LO_0
#define APS_AST_REGION_1_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x120)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SECURE                         0x0
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_DUAL                   0x0
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SCR                    AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_SHIFT)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_SHIFT)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_1_SLAVE_BASE_HI_0
#define APS_AST_REGION_1_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x124)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SECURE                         0x0
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_DUAL                   0x0
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SCR                    AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_SHIFT)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register APS_AST_REGION_1_MASK_LO_0
#define APS_AST_REGION_1_MASK_LO_0                      MK_ADDR_CONST(0x128)
#define APS_AST_REGION_1_MASK_LO_0_SECURE                       0x0
#define APS_AST_REGION_1_MASK_LO_0_DUAL                         0x0
#define APS_AST_REGION_1_MASK_LO_0_SCR                  AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_MASK_LO_0_WORD_COUNT                   0x1
#define APS_AST_REGION_1_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_1_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_1_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_1_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
#define APS_AST_REGION_1_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_1_MASK_LO_0_Mask_SHIFT)
#define APS_AST_REGION_1_MASK_LO_0_Mask_RANGE                   31:12
#define APS_AST_REGION_1_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_1_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
#define APS_AST_REGION_1_MASK_LO_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_1_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_1_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_1_MASK_HI_0
#define APS_AST_REGION_1_MASK_HI_0                      MK_ADDR_CONST(0x12c)
#define APS_AST_REGION_1_MASK_HI_0_SECURE                       0x0
#define APS_AST_REGION_1_MASK_HI_0_DUAL                         0x0
#define APS_AST_REGION_1_MASK_HI_0_SCR                  AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_MASK_HI_0_WORD_COUNT                   0x1
#define APS_AST_REGION_1_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_1_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_1_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_1_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_1_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_1_MASK_HI_0_Mask_SHIFT)
#define APS_AST_REGION_1_MASK_HI_0_Mask_RANGE                   31:0
#define APS_AST_REGION_1_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_1_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_1_MASK_HI_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_1_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_1_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_1_MASTER_BASE_LO_0
#define APS_AST_REGION_1_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x130)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_SECURE                        0x0
#define APS_AST_REGION_1_MASTER_BASE_LO_0_DUAL                  0x0
#define APS_AST_REGION_1_MASTER_BASE_LO_0_SCR                   AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_MASTER_BASE_LO_0_WORD_COUNT                    0x1
#define APS_AST_REGION_1_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_SHIFT)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_1_MASTER_BASE_HI_0
#define APS_AST_REGION_1_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x134)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_SECURE                        0x0
#define APS_AST_REGION_1_MASTER_BASE_HI_0_DUAL                  0x0
#define APS_AST_REGION_1_MASTER_BASE_HI_0_SCR                   AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_MASTER_BASE_HI_0_WORD_COUNT                    0x1
#define APS_AST_REGION_1_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_SHIFT)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_1_CONTROL_0
#define APS_AST_REGION_1_CONTROL_0                      MK_ADDR_CONST(0x138)
#define APS_AST_REGION_1_CONTROL_0_SECURE                       0x0
#define APS_AST_REGION_1_CONTROL_0_DUAL                         0x0
#define APS_AST_REGION_1_CONTROL_0_SCR                  AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
#define APS_AST_REGION_1_CONTROL_0_WORD_COUNT                   0x1
#define APS_AST_REGION_1_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_1_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_1_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_1_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
#define APS_AST_REGION_1_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_1_CONTROL_0_Physical_SHIFT)
#define APS_AST_REGION_1_CONTROL_0_Physical_RANGE                       19:19
#define APS_AST_REGION_1_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_1_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_1_CONTROL_0_Physical_WOFFSET                     0x0
#define APS_AST_REGION_1_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define APS_AST_REGION_1_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define APS_AST_REGION_1_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
#define APS_AST_REGION_1_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_1_CONTROL_0_VMIndex_SHIFT)
#define APS_AST_REGION_1_CONTROL_0_VMIndex_RANGE                        18:15
#define APS_AST_REGION_1_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
#define APS_AST_REGION_1_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
#define APS_AST_REGION_1_CONTROL_0_VMIndex_WOFFSET                      0x0
#define APS_AST_REGION_1_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define APS_AST_REGION_1_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define APS_AST_REGION_1_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
#define APS_AST_REGION_1_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_1_CONTROL_0_CarveOutID_SHIFT)
#define APS_AST_REGION_1_CONTROL_0_CarveOutID_RANGE                     9:5
#define APS_AST_REGION_1_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
#define APS_AST_REGION_1_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
#define APS_AST_REGION_1_CONTROL_0_CarveOutID_WOFFSET                   0x0
#define APS_AST_REGION_1_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define APS_AST_REGION_1_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define APS_AST_REGION_1_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
#define APS_AST_REGION_1_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_1_CONTROL_0_Snoop_SHIFT)
#define APS_AST_REGION_1_CONTROL_0_Snoop_RANGE                  2:2
#define APS_AST_REGION_1_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_1_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_1_CONTROL_0_Snoop_WOFFSET                        0x0
#define APS_AST_REGION_1_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define APS_AST_REGION_1_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define APS_AST_REGION_1_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
#define APS_AST_REGION_1_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)

#define APS_AST_REGION_1_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_1_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_1_CONTROL_0_Lock_SHIFT)
#define APS_AST_REGION_1_CONTROL_0_Lock_RANGE                   0:0
#define APS_AST_REGION_1_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_1_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_1_CONTROL_0_Lock_WOFFSET                 0x0
#define APS_AST_REGION_1_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_1_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_1_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_1_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_1_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_2_SLAVE_BASE_LO_0
#define APS_AST_REGION_2_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x140)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SECURE                         0x0
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_DUAL                   0x0
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SCR                    AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_SHIFT)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_SHIFT)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_2_SLAVE_BASE_HI_0
#define APS_AST_REGION_2_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x144)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SECURE                         0x0
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_DUAL                   0x0
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SCR                    AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_SHIFT)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register APS_AST_REGION_2_MASK_LO_0
#define APS_AST_REGION_2_MASK_LO_0                      MK_ADDR_CONST(0x148)
#define APS_AST_REGION_2_MASK_LO_0_SECURE                       0x0
#define APS_AST_REGION_2_MASK_LO_0_DUAL                         0x0
#define APS_AST_REGION_2_MASK_LO_0_SCR                  AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_MASK_LO_0_WORD_COUNT                   0x1
#define APS_AST_REGION_2_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_2_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_2_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_2_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
#define APS_AST_REGION_2_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_2_MASK_LO_0_Mask_SHIFT)
#define APS_AST_REGION_2_MASK_LO_0_Mask_RANGE                   31:12
#define APS_AST_REGION_2_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_2_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
#define APS_AST_REGION_2_MASK_LO_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_2_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_2_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_2_MASK_HI_0
#define APS_AST_REGION_2_MASK_HI_0                      MK_ADDR_CONST(0x14c)
#define APS_AST_REGION_2_MASK_HI_0_SECURE                       0x0
#define APS_AST_REGION_2_MASK_HI_0_DUAL                         0x0
#define APS_AST_REGION_2_MASK_HI_0_SCR                  AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_MASK_HI_0_WORD_COUNT                   0x1
#define APS_AST_REGION_2_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_2_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_2_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_2_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_2_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_2_MASK_HI_0_Mask_SHIFT)
#define APS_AST_REGION_2_MASK_HI_0_Mask_RANGE                   31:0
#define APS_AST_REGION_2_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_2_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_2_MASK_HI_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_2_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_2_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_2_MASTER_BASE_LO_0
#define APS_AST_REGION_2_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x150)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_SECURE                        0x0
#define APS_AST_REGION_2_MASTER_BASE_LO_0_DUAL                  0x0
#define APS_AST_REGION_2_MASTER_BASE_LO_0_SCR                   AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_MASTER_BASE_LO_0_WORD_COUNT                    0x1
#define APS_AST_REGION_2_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_SHIFT)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_2_MASTER_BASE_HI_0
#define APS_AST_REGION_2_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x154)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_SECURE                        0x0
#define APS_AST_REGION_2_MASTER_BASE_HI_0_DUAL                  0x0
#define APS_AST_REGION_2_MASTER_BASE_HI_0_SCR                   AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_MASTER_BASE_HI_0_WORD_COUNT                    0x1
#define APS_AST_REGION_2_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_SHIFT)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_2_CONTROL_0
#define APS_AST_REGION_2_CONTROL_0                      MK_ADDR_CONST(0x158)
#define APS_AST_REGION_2_CONTROL_0_SECURE                       0x0
#define APS_AST_REGION_2_CONTROL_0_DUAL                         0x0
#define APS_AST_REGION_2_CONTROL_0_SCR                  AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
#define APS_AST_REGION_2_CONTROL_0_WORD_COUNT                   0x1
#define APS_AST_REGION_2_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_2_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_2_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_2_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
#define APS_AST_REGION_2_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_2_CONTROL_0_Physical_SHIFT)
#define APS_AST_REGION_2_CONTROL_0_Physical_RANGE                       19:19
#define APS_AST_REGION_2_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_2_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_2_CONTROL_0_Physical_WOFFSET                     0x0
#define APS_AST_REGION_2_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define APS_AST_REGION_2_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define APS_AST_REGION_2_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
#define APS_AST_REGION_2_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_2_CONTROL_0_VMIndex_SHIFT)
#define APS_AST_REGION_2_CONTROL_0_VMIndex_RANGE                        18:15
#define APS_AST_REGION_2_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
#define APS_AST_REGION_2_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
#define APS_AST_REGION_2_CONTROL_0_VMIndex_WOFFSET                      0x0
#define APS_AST_REGION_2_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define APS_AST_REGION_2_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define APS_AST_REGION_2_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
#define APS_AST_REGION_2_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_2_CONTROL_0_CarveOutID_SHIFT)
#define APS_AST_REGION_2_CONTROL_0_CarveOutID_RANGE                     9:5
#define APS_AST_REGION_2_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
#define APS_AST_REGION_2_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
#define APS_AST_REGION_2_CONTROL_0_CarveOutID_WOFFSET                   0x0
#define APS_AST_REGION_2_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define APS_AST_REGION_2_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define APS_AST_REGION_2_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
#define APS_AST_REGION_2_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_2_CONTROL_0_Snoop_SHIFT)
#define APS_AST_REGION_2_CONTROL_0_Snoop_RANGE                  2:2
#define APS_AST_REGION_2_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_2_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_2_CONTROL_0_Snoop_WOFFSET                        0x0
#define APS_AST_REGION_2_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define APS_AST_REGION_2_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define APS_AST_REGION_2_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
#define APS_AST_REGION_2_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)

#define APS_AST_REGION_2_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_2_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_2_CONTROL_0_Lock_SHIFT)
#define APS_AST_REGION_2_CONTROL_0_Lock_RANGE                   0:0
#define APS_AST_REGION_2_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_2_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_2_CONTROL_0_Lock_WOFFSET                 0x0
#define APS_AST_REGION_2_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_2_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_2_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_2_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_2_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_3_SLAVE_BASE_LO_0
#define APS_AST_REGION_3_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x160)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SECURE                         0x0
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_DUAL                   0x0
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SCR                    AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_SHIFT)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_SHIFT)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_3_SLAVE_BASE_HI_0
#define APS_AST_REGION_3_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x164)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SECURE                         0x0
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_DUAL                   0x0
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SCR                    AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_SHIFT)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register APS_AST_REGION_3_MASK_LO_0
#define APS_AST_REGION_3_MASK_LO_0                      MK_ADDR_CONST(0x168)
#define APS_AST_REGION_3_MASK_LO_0_SECURE                       0x0
#define APS_AST_REGION_3_MASK_LO_0_DUAL                         0x0
#define APS_AST_REGION_3_MASK_LO_0_SCR                  AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_MASK_LO_0_WORD_COUNT                   0x1
#define APS_AST_REGION_3_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_3_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_3_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_3_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
#define APS_AST_REGION_3_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_3_MASK_LO_0_Mask_SHIFT)
#define APS_AST_REGION_3_MASK_LO_0_Mask_RANGE                   31:12
#define APS_AST_REGION_3_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_3_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
#define APS_AST_REGION_3_MASK_LO_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_3_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_3_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_3_MASK_HI_0
#define APS_AST_REGION_3_MASK_HI_0                      MK_ADDR_CONST(0x16c)
#define APS_AST_REGION_3_MASK_HI_0_SECURE                       0x0
#define APS_AST_REGION_3_MASK_HI_0_DUAL                         0x0
#define APS_AST_REGION_3_MASK_HI_0_SCR                  AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_MASK_HI_0_WORD_COUNT                   0x1
#define APS_AST_REGION_3_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_3_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_3_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_3_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_3_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_3_MASK_HI_0_Mask_SHIFT)
#define APS_AST_REGION_3_MASK_HI_0_Mask_RANGE                   31:0
#define APS_AST_REGION_3_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_3_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_3_MASK_HI_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_3_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_3_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_3_MASTER_BASE_LO_0
#define APS_AST_REGION_3_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x170)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_SECURE                        0x0
#define APS_AST_REGION_3_MASTER_BASE_LO_0_DUAL                  0x0
#define APS_AST_REGION_3_MASTER_BASE_LO_0_SCR                   AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_MASTER_BASE_LO_0_WORD_COUNT                    0x1
#define APS_AST_REGION_3_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_SHIFT)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_3_MASTER_BASE_HI_0
#define APS_AST_REGION_3_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x174)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_SECURE                        0x0
#define APS_AST_REGION_3_MASTER_BASE_HI_0_DUAL                  0x0
#define APS_AST_REGION_3_MASTER_BASE_HI_0_SCR                   AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_MASTER_BASE_HI_0_WORD_COUNT                    0x1
#define APS_AST_REGION_3_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_SHIFT)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_3_CONTROL_0
#define APS_AST_REGION_3_CONTROL_0                      MK_ADDR_CONST(0x178)
#define APS_AST_REGION_3_CONTROL_0_SECURE                       0x0
#define APS_AST_REGION_3_CONTROL_0_DUAL                         0x0
#define APS_AST_REGION_3_CONTROL_0_SCR                  AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
#define APS_AST_REGION_3_CONTROL_0_WORD_COUNT                   0x1
#define APS_AST_REGION_3_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_3_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_3_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_3_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
#define APS_AST_REGION_3_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_3_CONTROL_0_Physical_SHIFT)
#define APS_AST_REGION_3_CONTROL_0_Physical_RANGE                       19:19
#define APS_AST_REGION_3_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_3_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_3_CONTROL_0_Physical_WOFFSET                     0x0
#define APS_AST_REGION_3_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define APS_AST_REGION_3_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define APS_AST_REGION_3_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
#define APS_AST_REGION_3_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_3_CONTROL_0_VMIndex_SHIFT)
#define APS_AST_REGION_3_CONTROL_0_VMIndex_RANGE                        18:15
#define APS_AST_REGION_3_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
#define APS_AST_REGION_3_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
#define APS_AST_REGION_3_CONTROL_0_VMIndex_WOFFSET                      0x0
#define APS_AST_REGION_3_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define APS_AST_REGION_3_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define APS_AST_REGION_3_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
#define APS_AST_REGION_3_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_3_CONTROL_0_CarveOutID_SHIFT)
#define APS_AST_REGION_3_CONTROL_0_CarveOutID_RANGE                     9:5
#define APS_AST_REGION_3_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
#define APS_AST_REGION_3_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
#define APS_AST_REGION_3_CONTROL_0_CarveOutID_WOFFSET                   0x0
#define APS_AST_REGION_3_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define APS_AST_REGION_3_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define APS_AST_REGION_3_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
#define APS_AST_REGION_3_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_3_CONTROL_0_Snoop_SHIFT)
#define APS_AST_REGION_3_CONTROL_0_Snoop_RANGE                  2:2
#define APS_AST_REGION_3_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_3_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_3_CONTROL_0_Snoop_WOFFSET                        0x0
#define APS_AST_REGION_3_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define APS_AST_REGION_3_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define APS_AST_REGION_3_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
#define APS_AST_REGION_3_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)

#define APS_AST_REGION_3_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_3_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_3_CONTROL_0_Lock_SHIFT)
#define APS_AST_REGION_3_CONTROL_0_Lock_RANGE                   0:0
#define APS_AST_REGION_3_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_3_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_3_CONTROL_0_Lock_WOFFSET                 0x0
#define APS_AST_REGION_3_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_3_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_3_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_3_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_3_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_4_SLAVE_BASE_LO_0
#define APS_AST_REGION_4_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x180)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SECURE                         0x0
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_DUAL                   0x0
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SCR                    AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_SHIFT)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_SHIFT)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_4_SLAVE_BASE_HI_0
#define APS_AST_REGION_4_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x184)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SECURE                         0x0
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_DUAL                   0x0
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SCR                    AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_SHIFT)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register APS_AST_REGION_4_MASK_LO_0
#define APS_AST_REGION_4_MASK_LO_0                      MK_ADDR_CONST(0x188)
#define APS_AST_REGION_4_MASK_LO_0_SECURE                       0x0
#define APS_AST_REGION_4_MASK_LO_0_DUAL                         0x0
#define APS_AST_REGION_4_MASK_LO_0_SCR                  AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_MASK_LO_0_WORD_COUNT                   0x1
#define APS_AST_REGION_4_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_4_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_4_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_4_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
#define APS_AST_REGION_4_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_4_MASK_LO_0_Mask_SHIFT)
#define APS_AST_REGION_4_MASK_LO_0_Mask_RANGE                   31:12
#define APS_AST_REGION_4_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_4_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
#define APS_AST_REGION_4_MASK_LO_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_4_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_4_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_4_MASK_HI_0
#define APS_AST_REGION_4_MASK_HI_0                      MK_ADDR_CONST(0x18c)
#define APS_AST_REGION_4_MASK_HI_0_SECURE                       0x0
#define APS_AST_REGION_4_MASK_HI_0_DUAL                         0x0
#define APS_AST_REGION_4_MASK_HI_0_SCR                  AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_MASK_HI_0_WORD_COUNT                   0x1
#define APS_AST_REGION_4_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_4_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_4_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_4_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_4_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_4_MASK_HI_0_Mask_SHIFT)
#define APS_AST_REGION_4_MASK_HI_0_Mask_RANGE                   31:0
#define APS_AST_REGION_4_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_4_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_4_MASK_HI_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_4_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_4_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_4_MASTER_BASE_LO_0
#define APS_AST_REGION_4_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x190)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_SECURE                        0x0
#define APS_AST_REGION_4_MASTER_BASE_LO_0_DUAL                  0x0
#define APS_AST_REGION_4_MASTER_BASE_LO_0_SCR                   AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_MASTER_BASE_LO_0_WORD_COUNT                    0x1
#define APS_AST_REGION_4_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_SHIFT)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_4_MASTER_BASE_HI_0
#define APS_AST_REGION_4_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x194)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_SECURE                        0x0
#define APS_AST_REGION_4_MASTER_BASE_HI_0_DUAL                  0x0
#define APS_AST_REGION_4_MASTER_BASE_HI_0_SCR                   AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_MASTER_BASE_HI_0_WORD_COUNT                    0x1
#define APS_AST_REGION_4_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_SHIFT)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_4_CONTROL_0
#define APS_AST_REGION_4_CONTROL_0                      MK_ADDR_CONST(0x198)
#define APS_AST_REGION_4_CONTROL_0_SECURE                       0x0
#define APS_AST_REGION_4_CONTROL_0_DUAL                         0x0
#define APS_AST_REGION_4_CONTROL_0_SCR                  AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
#define APS_AST_REGION_4_CONTROL_0_WORD_COUNT                   0x1
#define APS_AST_REGION_4_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_4_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_4_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_4_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
#define APS_AST_REGION_4_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_4_CONTROL_0_Physical_SHIFT)
#define APS_AST_REGION_4_CONTROL_0_Physical_RANGE                       19:19
#define APS_AST_REGION_4_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_4_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_4_CONTROL_0_Physical_WOFFSET                     0x0
#define APS_AST_REGION_4_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define APS_AST_REGION_4_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define APS_AST_REGION_4_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
#define APS_AST_REGION_4_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_4_CONTROL_0_VMIndex_SHIFT)
#define APS_AST_REGION_4_CONTROL_0_VMIndex_RANGE                        18:15
#define APS_AST_REGION_4_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
#define APS_AST_REGION_4_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
#define APS_AST_REGION_4_CONTROL_0_VMIndex_WOFFSET                      0x0
#define APS_AST_REGION_4_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define APS_AST_REGION_4_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define APS_AST_REGION_4_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
#define APS_AST_REGION_4_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_4_CONTROL_0_CarveOutID_SHIFT)
#define APS_AST_REGION_4_CONTROL_0_CarveOutID_RANGE                     9:5
#define APS_AST_REGION_4_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
#define APS_AST_REGION_4_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
#define APS_AST_REGION_4_CONTROL_0_CarveOutID_WOFFSET                   0x0
#define APS_AST_REGION_4_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define APS_AST_REGION_4_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define APS_AST_REGION_4_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
#define APS_AST_REGION_4_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_4_CONTROL_0_Snoop_SHIFT)
#define APS_AST_REGION_4_CONTROL_0_Snoop_RANGE                  2:2
#define APS_AST_REGION_4_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_4_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_4_CONTROL_0_Snoop_WOFFSET                        0x0
#define APS_AST_REGION_4_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define APS_AST_REGION_4_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define APS_AST_REGION_4_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
#define APS_AST_REGION_4_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)

#define APS_AST_REGION_4_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_4_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_4_CONTROL_0_Lock_SHIFT)
#define APS_AST_REGION_4_CONTROL_0_Lock_RANGE                   0:0
#define APS_AST_REGION_4_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_4_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_4_CONTROL_0_Lock_WOFFSET                 0x0
#define APS_AST_REGION_4_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_4_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_4_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_4_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_4_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_5_SLAVE_BASE_LO_0
#define APS_AST_REGION_5_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x1a0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SECURE                         0x0
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_DUAL                   0x0
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SCR                    AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_SHIFT)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_SHIFT)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_5_SLAVE_BASE_HI_0
#define APS_AST_REGION_5_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x1a4)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SECURE                         0x0
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_DUAL                   0x0
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SCR                    AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_SHIFT)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register APS_AST_REGION_5_MASK_LO_0
#define APS_AST_REGION_5_MASK_LO_0                      MK_ADDR_CONST(0x1a8)
#define APS_AST_REGION_5_MASK_LO_0_SECURE                       0x0
#define APS_AST_REGION_5_MASK_LO_0_DUAL                         0x0
#define APS_AST_REGION_5_MASK_LO_0_SCR                  AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_MASK_LO_0_WORD_COUNT                   0x1
#define APS_AST_REGION_5_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_5_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_5_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_5_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
#define APS_AST_REGION_5_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_5_MASK_LO_0_Mask_SHIFT)
#define APS_AST_REGION_5_MASK_LO_0_Mask_RANGE                   31:12
#define APS_AST_REGION_5_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_5_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
#define APS_AST_REGION_5_MASK_LO_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_5_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_5_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_5_MASK_HI_0
#define APS_AST_REGION_5_MASK_HI_0                      MK_ADDR_CONST(0x1ac)
#define APS_AST_REGION_5_MASK_HI_0_SECURE                       0x0
#define APS_AST_REGION_5_MASK_HI_0_DUAL                         0x0
#define APS_AST_REGION_5_MASK_HI_0_SCR                  AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_MASK_HI_0_WORD_COUNT                   0x1
#define APS_AST_REGION_5_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_5_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_5_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_5_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_5_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_5_MASK_HI_0_Mask_SHIFT)
#define APS_AST_REGION_5_MASK_HI_0_Mask_RANGE                   31:0
#define APS_AST_REGION_5_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_5_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_5_MASK_HI_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_5_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_5_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_5_MASTER_BASE_LO_0
#define APS_AST_REGION_5_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x1b0)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_SECURE                        0x0
#define APS_AST_REGION_5_MASTER_BASE_LO_0_DUAL                  0x0
#define APS_AST_REGION_5_MASTER_BASE_LO_0_SCR                   AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_MASTER_BASE_LO_0_WORD_COUNT                    0x1
#define APS_AST_REGION_5_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_SHIFT)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_5_MASTER_BASE_HI_0
#define APS_AST_REGION_5_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x1b4)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_SECURE                        0x0
#define APS_AST_REGION_5_MASTER_BASE_HI_0_DUAL                  0x0
#define APS_AST_REGION_5_MASTER_BASE_HI_0_SCR                   AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_MASTER_BASE_HI_0_WORD_COUNT                    0x1
#define APS_AST_REGION_5_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_SHIFT)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_5_CONTROL_0
#define APS_AST_REGION_5_CONTROL_0                      MK_ADDR_CONST(0x1b8)
#define APS_AST_REGION_5_CONTROL_0_SECURE                       0x0
#define APS_AST_REGION_5_CONTROL_0_DUAL                         0x0
#define APS_AST_REGION_5_CONTROL_0_SCR                  AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
#define APS_AST_REGION_5_CONTROL_0_WORD_COUNT                   0x1
#define APS_AST_REGION_5_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_5_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_5_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_5_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
#define APS_AST_REGION_5_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_5_CONTROL_0_Physical_SHIFT)
#define APS_AST_REGION_5_CONTROL_0_Physical_RANGE                       19:19
#define APS_AST_REGION_5_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_5_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_5_CONTROL_0_Physical_WOFFSET                     0x0
#define APS_AST_REGION_5_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define APS_AST_REGION_5_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define APS_AST_REGION_5_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
#define APS_AST_REGION_5_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_5_CONTROL_0_VMIndex_SHIFT)
#define APS_AST_REGION_5_CONTROL_0_VMIndex_RANGE                        18:15
#define APS_AST_REGION_5_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
#define APS_AST_REGION_5_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
#define APS_AST_REGION_5_CONTROL_0_VMIndex_WOFFSET                      0x0
#define APS_AST_REGION_5_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define APS_AST_REGION_5_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define APS_AST_REGION_5_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
#define APS_AST_REGION_5_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_5_CONTROL_0_CarveOutID_SHIFT)
#define APS_AST_REGION_5_CONTROL_0_CarveOutID_RANGE                     9:5
#define APS_AST_REGION_5_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
#define APS_AST_REGION_5_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
#define APS_AST_REGION_5_CONTROL_0_CarveOutID_WOFFSET                   0x0
#define APS_AST_REGION_5_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define APS_AST_REGION_5_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define APS_AST_REGION_5_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
#define APS_AST_REGION_5_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_5_CONTROL_0_Snoop_SHIFT)
#define APS_AST_REGION_5_CONTROL_0_Snoop_RANGE                  2:2
#define APS_AST_REGION_5_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_5_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_5_CONTROL_0_Snoop_WOFFSET                        0x0
#define APS_AST_REGION_5_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define APS_AST_REGION_5_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define APS_AST_REGION_5_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
#define APS_AST_REGION_5_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)

#define APS_AST_REGION_5_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_5_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_5_CONTROL_0_Lock_SHIFT)
#define APS_AST_REGION_5_CONTROL_0_Lock_RANGE                   0:0
#define APS_AST_REGION_5_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_5_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_5_CONTROL_0_Lock_WOFFSET                 0x0
#define APS_AST_REGION_5_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_5_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_5_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_5_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_5_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_6_SLAVE_BASE_LO_0
#define APS_AST_REGION_6_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x1c0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SECURE                         0x0
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_DUAL                   0x0
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SCR                    AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_SHIFT)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_SHIFT)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_6_SLAVE_BASE_HI_0
#define APS_AST_REGION_6_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x1c4)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SECURE                         0x0
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_DUAL                   0x0
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SCR                    AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_SHIFT)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register APS_AST_REGION_6_MASK_LO_0
#define APS_AST_REGION_6_MASK_LO_0                      MK_ADDR_CONST(0x1c8)
#define APS_AST_REGION_6_MASK_LO_0_SECURE                       0x0
#define APS_AST_REGION_6_MASK_LO_0_DUAL                         0x0
#define APS_AST_REGION_6_MASK_LO_0_SCR                  AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_MASK_LO_0_WORD_COUNT                   0x1
#define APS_AST_REGION_6_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_6_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_6_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_6_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
#define APS_AST_REGION_6_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_6_MASK_LO_0_Mask_SHIFT)
#define APS_AST_REGION_6_MASK_LO_0_Mask_RANGE                   31:12
#define APS_AST_REGION_6_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_6_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
#define APS_AST_REGION_6_MASK_LO_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_6_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_6_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_6_MASK_HI_0
#define APS_AST_REGION_6_MASK_HI_0                      MK_ADDR_CONST(0x1cc)
#define APS_AST_REGION_6_MASK_HI_0_SECURE                       0x0
#define APS_AST_REGION_6_MASK_HI_0_DUAL                         0x0
#define APS_AST_REGION_6_MASK_HI_0_SCR                  AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_MASK_HI_0_WORD_COUNT                   0x1
#define APS_AST_REGION_6_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_6_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_6_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_6_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_6_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_6_MASK_HI_0_Mask_SHIFT)
#define APS_AST_REGION_6_MASK_HI_0_Mask_RANGE                   31:0
#define APS_AST_REGION_6_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_6_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_6_MASK_HI_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_6_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_6_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_6_MASTER_BASE_LO_0
#define APS_AST_REGION_6_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x1d0)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_SECURE                        0x0
#define APS_AST_REGION_6_MASTER_BASE_LO_0_DUAL                  0x0
#define APS_AST_REGION_6_MASTER_BASE_LO_0_SCR                   AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_MASTER_BASE_LO_0_WORD_COUNT                    0x1
#define APS_AST_REGION_6_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_SHIFT)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_6_MASTER_BASE_HI_0
#define APS_AST_REGION_6_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x1d4)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_SECURE                        0x0
#define APS_AST_REGION_6_MASTER_BASE_HI_0_DUAL                  0x0
#define APS_AST_REGION_6_MASTER_BASE_HI_0_SCR                   AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_MASTER_BASE_HI_0_WORD_COUNT                    0x1
#define APS_AST_REGION_6_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_SHIFT)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_6_CONTROL_0
#define APS_AST_REGION_6_CONTROL_0                      MK_ADDR_CONST(0x1d8)
#define APS_AST_REGION_6_CONTROL_0_SECURE                       0x0
#define APS_AST_REGION_6_CONTROL_0_DUAL                         0x0
#define APS_AST_REGION_6_CONTROL_0_SCR                  AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
#define APS_AST_REGION_6_CONTROL_0_WORD_COUNT                   0x1
#define APS_AST_REGION_6_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_6_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_6_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_6_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
#define APS_AST_REGION_6_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_6_CONTROL_0_Physical_SHIFT)
#define APS_AST_REGION_6_CONTROL_0_Physical_RANGE                       19:19
#define APS_AST_REGION_6_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_6_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_6_CONTROL_0_Physical_WOFFSET                     0x0
#define APS_AST_REGION_6_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define APS_AST_REGION_6_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define APS_AST_REGION_6_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
#define APS_AST_REGION_6_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_6_CONTROL_0_VMIndex_SHIFT)
#define APS_AST_REGION_6_CONTROL_0_VMIndex_RANGE                        18:15
#define APS_AST_REGION_6_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
#define APS_AST_REGION_6_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
#define APS_AST_REGION_6_CONTROL_0_VMIndex_WOFFSET                      0x0
#define APS_AST_REGION_6_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define APS_AST_REGION_6_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define APS_AST_REGION_6_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
#define APS_AST_REGION_6_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_6_CONTROL_0_CarveOutID_SHIFT)
#define APS_AST_REGION_6_CONTROL_0_CarveOutID_RANGE                     9:5
#define APS_AST_REGION_6_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
#define APS_AST_REGION_6_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
#define APS_AST_REGION_6_CONTROL_0_CarveOutID_WOFFSET                   0x0
#define APS_AST_REGION_6_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define APS_AST_REGION_6_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define APS_AST_REGION_6_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
#define APS_AST_REGION_6_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_6_CONTROL_0_Snoop_SHIFT)
#define APS_AST_REGION_6_CONTROL_0_Snoop_RANGE                  2:2
#define APS_AST_REGION_6_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_6_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_6_CONTROL_0_Snoop_WOFFSET                        0x0
#define APS_AST_REGION_6_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define APS_AST_REGION_6_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define APS_AST_REGION_6_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
#define APS_AST_REGION_6_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)

#define APS_AST_REGION_6_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_6_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_6_CONTROL_0_Lock_SHIFT)
#define APS_AST_REGION_6_CONTROL_0_Lock_RANGE                   0:0
#define APS_AST_REGION_6_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_6_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_6_CONTROL_0_Lock_WOFFSET                 0x0
#define APS_AST_REGION_6_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_6_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_6_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_6_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_6_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_7_SLAVE_BASE_LO_0
#define APS_AST_REGION_7_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x1e0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SECURE                         0x0
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_DUAL                   0x0
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SCR                    AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_SHIFT)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_SHIFT)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)


// Register APS_AST_REGION_7_SLAVE_BASE_HI_0
#define APS_AST_REGION_7_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x1e4)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SECURE                         0x0
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_DUAL                   0x0
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SCR                    AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_SHIFT)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register APS_AST_REGION_7_MASK_LO_0
#define APS_AST_REGION_7_MASK_LO_0                      MK_ADDR_CONST(0x1e8)
#define APS_AST_REGION_7_MASK_LO_0_SECURE                       0x0
#define APS_AST_REGION_7_MASK_LO_0_DUAL                         0x0
#define APS_AST_REGION_7_MASK_LO_0_SCR                  AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_MASK_LO_0_WORD_COUNT                   0x1
#define APS_AST_REGION_7_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_7_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_7_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_7_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
#define APS_AST_REGION_7_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_7_MASK_LO_0_Mask_SHIFT)
#define APS_AST_REGION_7_MASK_LO_0_Mask_RANGE                   31:12
#define APS_AST_REGION_7_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_7_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
#define APS_AST_REGION_7_MASK_LO_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_7_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_7_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_7_MASK_HI_0
#define APS_AST_REGION_7_MASK_HI_0                      MK_ADDR_CONST(0x1ec)
#define APS_AST_REGION_7_MASK_HI_0_SECURE                       0x0
#define APS_AST_REGION_7_MASK_HI_0_DUAL                         0x0
#define APS_AST_REGION_7_MASK_HI_0_SCR                  AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_MASK_HI_0_WORD_COUNT                   0x1
#define APS_AST_REGION_7_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_7_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_7_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_7_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_7_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_7_MASK_HI_0_Mask_SHIFT)
#define APS_AST_REGION_7_MASK_HI_0_Mask_RANGE                   31:0
#define APS_AST_REGION_7_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
#define APS_AST_REGION_7_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_7_MASK_HI_0_Mask_WOFFSET                 0x0
#define APS_AST_REGION_7_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_7_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_AST_REGION_7_MASTER_BASE_LO_0
#define APS_AST_REGION_7_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x1f0)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_SECURE                        0x0
#define APS_AST_REGION_7_MASTER_BASE_LO_0_DUAL                  0x0
#define APS_AST_REGION_7_MASTER_BASE_LO_0_SCR                   AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_MASTER_BASE_LO_0_WORD_COUNT                    0x1
#define APS_AST_REGION_7_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_SHIFT)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_7_MASTER_BASE_HI_0
#define APS_AST_REGION_7_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x1f4)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_SECURE                        0x0
#define APS_AST_REGION_7_MASTER_BASE_HI_0_DUAL                  0x0
#define APS_AST_REGION_7_MASTER_BASE_HI_0_SCR                   AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_MASTER_BASE_HI_0_WORD_COUNT                    0x1
#define APS_AST_REGION_7_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_SHIFT)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_AST_REGION_7_CONTROL_0
#define APS_AST_REGION_7_CONTROL_0                      MK_ADDR_CONST(0x1f8)
#define APS_AST_REGION_7_CONTROL_0_SECURE                       0x0
#define APS_AST_REGION_7_CONTROL_0_DUAL                         0x0
#define APS_AST_REGION_7_CONTROL_0_SCR                  AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
#define APS_AST_REGION_7_CONTROL_0_WORD_COUNT                   0x1
#define APS_AST_REGION_7_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_7_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_7_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
#define APS_AST_REGION_7_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
#define APS_AST_REGION_7_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_7_CONTROL_0_Physical_SHIFT)
#define APS_AST_REGION_7_CONTROL_0_Physical_RANGE                       19:19
#define APS_AST_REGION_7_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_7_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
#define APS_AST_REGION_7_CONTROL_0_Physical_WOFFSET                     0x0
#define APS_AST_REGION_7_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define APS_AST_REGION_7_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define APS_AST_REGION_7_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
#define APS_AST_REGION_7_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_7_CONTROL_0_VMIndex_SHIFT)
#define APS_AST_REGION_7_CONTROL_0_VMIndex_RANGE                        18:15
#define APS_AST_REGION_7_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
#define APS_AST_REGION_7_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
#define APS_AST_REGION_7_CONTROL_0_VMIndex_WOFFSET                      0x0
#define APS_AST_REGION_7_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define APS_AST_REGION_7_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define APS_AST_REGION_7_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
#define APS_AST_REGION_7_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_7_CONTROL_0_CarveOutID_SHIFT)
#define APS_AST_REGION_7_CONTROL_0_CarveOutID_RANGE                     9:5
#define APS_AST_REGION_7_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
#define APS_AST_REGION_7_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
#define APS_AST_REGION_7_CONTROL_0_CarveOutID_WOFFSET                   0x0
#define APS_AST_REGION_7_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
#define APS_AST_REGION_7_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define APS_AST_REGION_7_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
#define APS_AST_REGION_7_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_7_CONTROL_0_Snoop_SHIFT)
#define APS_AST_REGION_7_CONTROL_0_Snoop_RANGE                  2:2
#define APS_AST_REGION_7_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_7_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
#define APS_AST_REGION_7_CONTROL_0_Snoop_WOFFSET                        0x0
#define APS_AST_REGION_7_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define APS_AST_REGION_7_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define APS_AST_REGION_7_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
#define APS_AST_REGION_7_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)

#define APS_AST_REGION_7_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
#define APS_AST_REGION_7_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_7_CONTROL_0_Lock_SHIFT)
#define APS_AST_REGION_7_CONTROL_0_Lock_RANGE                   0:0
#define APS_AST_REGION_7_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_7_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
#define APS_AST_REGION_7_CONTROL_0_Lock_WOFFSET                 0x0
#define APS_AST_REGION_7_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_AST_REGION_7_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_AST_REGION_7_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define APS_AST_REGION_7_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
#define APS_AST_REGION_7_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)


//
// REGISTER LIST
//
#define LIST_ARAPS_AST_REGS(_op_) \
_op_(APS_AST_CONTROL_0) \
_op_(APS_AST_ERROR_STATUS_0) \
_op_(APS_AST_ERROR_ADDR_LO_0) \
_op_(APS_AST_ERROR_ADDR_HI_0) \
_op_(APS_AST_STREAMID_CTL_0) \
_op_(APS_AST_STREAMID_CTL) \
_op_(APS_AST_STREAMID_CTL_1) \
_op_(APS_AST_STREAMID_CTL_2) \
_op_(APS_AST_STREAMID_CTL_3) \
_op_(APS_AST_STREAMID_CTL_4) \
_op_(APS_AST_STREAMID_CTL_5) \
_op_(APS_AST_STREAMID_CTL_6) \
_op_(APS_AST_STREAMID_CTL_7) \
_op_(APS_AST_STREAMID_CTL_8) \
_op_(APS_AST_STREAMID_CTL_9) \
_op_(APS_AST_STREAMID_CTL_10) \
_op_(APS_AST_STREAMID_CTL_11) \
_op_(APS_AST_STREAMID_CTL_12) \
_op_(APS_AST_STREAMID_CTL_13) \
_op_(APS_AST_STREAMID_CTL_14) \
_op_(APS_AST_STREAMID_CTL_15) \
_op_(APS_AST_WRITE_BLOCK_STATUS_0) \
_op_(APS_AST_READ_BLOCK_STATUS_0) \
_op_(APS_AST_REGION_0_SLAVE_BASE_LO_0) \
_op_(APS_AST_REGION_0_SLAVE_BASE_HI_0) \
_op_(APS_AST_REGION_0_MASK_LO_0) \
_op_(APS_AST_REGION_0_MASK_HI_0) \
_op_(APS_AST_REGION_0_MASTER_BASE_LO_0) \
_op_(APS_AST_REGION_0_MASTER_BASE_HI_0) \
_op_(APS_AST_REGION_0_CONTROL_0) \
_op_(APS_AST_REGION_1_SLAVE_BASE_LO_0) \
_op_(APS_AST_REGION_1_SLAVE_BASE_HI_0) \
_op_(APS_AST_REGION_1_MASK_LO_0) \
_op_(APS_AST_REGION_1_MASK_HI_0) \
_op_(APS_AST_REGION_1_MASTER_BASE_LO_0) \
_op_(APS_AST_REGION_1_MASTER_BASE_HI_0) \
_op_(APS_AST_REGION_1_CONTROL_0) \
_op_(APS_AST_REGION_2_SLAVE_BASE_LO_0) \
_op_(APS_AST_REGION_2_SLAVE_BASE_HI_0) \
_op_(APS_AST_REGION_2_MASK_LO_0) \
_op_(APS_AST_REGION_2_MASK_HI_0) \
_op_(APS_AST_REGION_2_MASTER_BASE_LO_0) \
_op_(APS_AST_REGION_2_MASTER_BASE_HI_0) \
_op_(APS_AST_REGION_2_CONTROL_0) \
_op_(APS_AST_REGION_3_SLAVE_BASE_LO_0) \
_op_(APS_AST_REGION_3_SLAVE_BASE_HI_0) \
_op_(APS_AST_REGION_3_MASK_LO_0) \
_op_(APS_AST_REGION_3_MASK_HI_0) \
_op_(APS_AST_REGION_3_MASTER_BASE_LO_0) \
_op_(APS_AST_REGION_3_MASTER_BASE_HI_0) \
_op_(APS_AST_REGION_3_CONTROL_0) \
_op_(APS_AST_REGION_4_SLAVE_BASE_LO_0) \
_op_(APS_AST_REGION_4_SLAVE_BASE_HI_0) \
_op_(APS_AST_REGION_4_MASK_LO_0) \
_op_(APS_AST_REGION_4_MASK_HI_0) \
_op_(APS_AST_REGION_4_MASTER_BASE_LO_0) \
_op_(APS_AST_REGION_4_MASTER_BASE_HI_0) \
_op_(APS_AST_REGION_4_CONTROL_0) \
_op_(APS_AST_REGION_5_SLAVE_BASE_LO_0) \
_op_(APS_AST_REGION_5_SLAVE_BASE_HI_0) \
_op_(APS_AST_REGION_5_MASK_LO_0) \
_op_(APS_AST_REGION_5_MASK_HI_0) \
_op_(APS_AST_REGION_5_MASTER_BASE_LO_0) \
_op_(APS_AST_REGION_5_MASTER_BASE_HI_0) \
_op_(APS_AST_REGION_5_CONTROL_0) \
_op_(APS_AST_REGION_6_SLAVE_BASE_LO_0) \
_op_(APS_AST_REGION_6_SLAVE_BASE_HI_0) \
_op_(APS_AST_REGION_6_MASK_LO_0) \
_op_(APS_AST_REGION_6_MASK_HI_0) \
_op_(APS_AST_REGION_6_MASTER_BASE_LO_0) \
_op_(APS_AST_REGION_6_MASTER_BASE_HI_0) \
_op_(APS_AST_REGION_6_CONTROL_0) \
_op_(APS_AST_REGION_7_SLAVE_BASE_LO_0) \
_op_(APS_AST_REGION_7_SLAVE_BASE_HI_0) \
_op_(APS_AST_REGION_7_MASK_LO_0) \
_op_(APS_AST_REGION_7_MASK_HI_0) \
_op_(APS_AST_REGION_7_MASTER_BASE_LO_0) \
_op_(APS_AST_REGION_7_MASTER_BASE_HI_0) \
_op_(APS_AST_REGION_7_CONTROL_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_APS_AST    0x00000000

//
// ARAPS_AST REGISTER BANKS
//

#define APS_AST0_FIRST_REG 0x0000 // APS_AST_CONTROL_0
#define APS_AST0_LAST_REG 0x000c // APS_AST_ERROR_ADDR_HI_0
#define APS_AST1_FIRST_REG 0x0020 // APS_AST_STREAMID_CTL_0
#define APS_AST1_LAST_REG 0x0064 // APS_AST_READ_BLOCK_STATUS_0
#define APS_AST2_FIRST_REG 0x0100 // APS_AST_REGION_0_SLAVE_BASE_LO_0
#define APS_AST2_LAST_REG 0x0118 // APS_AST_REGION_0_CONTROL_0
#define APS_AST3_FIRST_REG 0x0120 // APS_AST_REGION_1_SLAVE_BASE_LO_0
#define APS_AST3_LAST_REG 0x0138 // APS_AST_REGION_1_CONTROL_0
#define APS_AST4_FIRST_REG 0x0140 // APS_AST_REGION_2_SLAVE_BASE_LO_0
#define APS_AST4_LAST_REG 0x0158 // APS_AST_REGION_2_CONTROL_0
#define APS_AST5_FIRST_REG 0x0160 // APS_AST_REGION_3_SLAVE_BASE_LO_0
#define APS_AST5_LAST_REG 0x0178 // APS_AST_REGION_3_CONTROL_0
#define APS_AST6_FIRST_REG 0x0180 // APS_AST_REGION_4_SLAVE_BASE_LO_0
#define APS_AST6_LAST_REG 0x0198 // APS_AST_REGION_4_CONTROL_0
#define APS_AST7_FIRST_REG 0x01a0 // APS_AST_REGION_5_SLAVE_BASE_LO_0
#define APS_AST7_LAST_REG 0x01b8 // APS_AST_REGION_5_CONTROL_0
#define APS_AST8_FIRST_REG 0x01c0 // APS_AST_REGION_6_SLAVE_BASE_LO_0
#define APS_AST8_LAST_REG 0x01d8 // APS_AST_REGION_6_CONTROL_0
#define APS_AST9_FIRST_REG 0x01e0 // APS_AST_REGION_7_SLAVE_BASE_LO_0
#define APS_AST9_LAST_REG 0x01f8 // APS_AST_REGION_7_CONTROL_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARAPS_AST_H_INC
