/* Copyright (c) 2015-2022, NVIDIA CORPORATION.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *  * Neither the name of NVIDIA CORPORATION nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _MBOX_AON_H
#define _MBOX_AON_H

/* BPMP Mailbox */
#define MBOX_BPMP_BPMP			0
#define MBOX_BPMP_UART			1
#define MBOX_AON_BPMP			0
#define MBOX_AON_BPMP_UART		6

/* CCPLEX Mailbox */
#define MBOX_AON_CCPLEX_UART	1
#define MBOX_AON_CCPLEX_IVC_TX	4
#define MBOX_AON_CCPLEX_IVC_RX	5

/* PSC Mailbox */
#define MBOX_AON_PSC_UART		2

/* DCE Mailbox */
#define MBOX_AON_DCE_UART		3

/* SCE Mailbox */
#define MBOX_AON_SCE_UART		4
#define MBOX_SCE_UART			4

/* RCE Mailbox */
#define MBOX_AON_RCE_UART		5

/* TZ Mailbox */
#define MBOX_AON_TZ_UART		7

/* FSI Mailbox */
#define MBOX_TX_FSI_UART		7
#define MBOX_FSI_UART			7

#define MBOX_TAG_BIT			(1 << 31)

#endif
