/**
 * @file peregrine.h
 *
 * @brief Engine-specific differences in Peregrine
 *
 * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * * Redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer.
 * * Redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution.
 * * Neither the name of NVIDIA CORPORATION nor the names of its
 * contributors may be used to endorse or promote products derived
 * from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef CPU__PEREGRINE_H
#define CPU__PEREGRINE_H
#define FSP__CPU__PEREGRINE_H                       1

/*!
 * @file    engine.h
 * @brief   This file hides header differences between different Peregrines.
 */

// Register headers
#if (__riscv_xlen == 32)
    #include NVRISCV32_MANUAL_LOCAL_IO
#else
    #include NVRISCV64_MANUAL_LOCAL_IO
#endif // (__riscv_xlen == 32)

#if defined(NVRISCV_IS_ENGINE_gsp)
    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
        #include <dev_falcon_v4.h>
        #include <dev_riscv_pri.h>
        #define FALCON_BASE   NV_FALCON_GSP_BASE
    #endif
    #if NVRISCV_HAS_PRI
        #define RISCV_BASE    NV_FALCON2_GSP_BASE
    #endif
#elif defined(NVRISCV_IS_ENGINE_pmu)
    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
        #include <dev_falcon_v4.h>
        #include <dev_riscv_pri.h>
        #define FALCON_BASE   NV_FALCON_PWR_BASE
    #endif
    #if NVRISCV_HAS_PRI
        #define RISCV_BASE    NV_FALCON2_PWR_BASE
    #endif
#elif defined(NVRISCV_IS_ENGINE_minion)
    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
        #include <dev_falcon_v4.h>
        #include <dev_riscv_pri.h>
        #define FALCON_BASE   NV_FALCON_MINION_BASE
    #endif
    #if NVRISCV_HAS_PRI
        #define NV_FALCON2_MINION_BASE 0xA06400
        #define RISCV_BASE    NV_FALCON2_MINION_BASE
    #endif
#elif defined(NVRISCV_IS_ENGINE_sec)
    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
        #include <dev_falcon_v4.h>
        #include <dev_riscv_pri.h>
        #define FALCON_BASE   0x840000
    #endif
    #if NVRISCV_HAS_PRI
        #define RISCV_BASE    NV_FALCON2_SEC_BASE
    #endif
#elif defined(NVRISCV_IS_ENGINE_fsp)
    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
        #include <dev_falcon_v4.h>
        #include <dev_riscv_pri.h>
        #define FALCON_BASE   0x8F0000
    #endif
    #if NVRISCV_HAS_PRI
        #define RISCV_BASE    NV_FALCON2_FSP_BASE
    #endif
#elif defined(NVRISCV_IS_ENGINE_nvdec)
    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
        #include <dev_falcon_v4.h>
        #include <dev_riscv_pri.h>
        // Use NVDEC0 base
        #define FALCON_BASE   NV_FALCON_NVDEC0_BASE
    #endif
    #if NVRISCV_HAS_PRI
        // Use NVDEC0 base
        #define RISCV_BASE    NV_FALCON2_NVDEC0_BASE
    #endif
#elif NVRISCV_IS_ENGINE_soe
    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
        #include <dev_falcon_v4.h>
        #include <dev_riscv_pri.h>
        #define FALCON_BASE   0x840000
    #endif
    #if NVRISCV_HAS_PRI
        #define RISCV_BASE    NV_FALCON2_SOE_BASE
    #endif
#elif NVRISCV_IS_ENGINE_pxuc
    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
        #include <dev_falcon_v4.h>
        // TODO: restore to dev_riscv_pri.h when the FACLON2_*_BASE are restored
        // bug 3575785
        #include <dev_falcon_second_pri.h>
        #define FALCON_BASE   0x828000
    #endif
    #if NVRISCV_HAS_PRI
        #define RISCV_BASE    (FALCON_BASE + NV_PPXUC_FALCON2_BASE)
    #endif
#endif

#endif /* CPU__PEREGRINE_H  */
