//
// Copyright (c) 2022 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARI2C_H_INC
#define ARI2C_H_INC
#define NV_MOBILE_ARI2C_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARI2C_H_SCRREG_NOMENCLATURE INFERRED

// Register I2C_I2C_CNFG_0
#define I2C_I2C_CNFG_0                  MK_ADDR_CONST(0x0)
#define I2C_I2C_CNFG_0_SECURE                   0x0
#define I2C_I2C_CNFG_0_DUAL                     0x0
#define I2C_I2C_CNFG_0_SCR                      0
#define I2C_I2C_CNFG_0_SCRREG                   0
#define I2C_I2C_CNFG_0_WORD_COUNT                       0x1
#define I2C_I2C_CNFG_0_RESET_VAL                        MK_MASK_CONST(0x20800)
#define I2C_I2C_CNFG_0_RESET_MASK                       MK_MASK_CONST(0x3ffff)
#define I2C_I2C_CNFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_READ_MASK                        MK_MASK_CONST(0x3ffff)
#define I2C_I2C_CNFG_0_WRITE_MASK                       MK_MASK_CONST(0x3f7ff)
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_SHIFT                  MK_SHIFT_CONST(17)
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_MULTI_MASTER_MODE_SHIFT)
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_RANGE                  17:17
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_MSB                    MK_SHIFT_CONST(17)
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_LSB                    MK_SHIFT_CONST(17)
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_WOFFSET                        0x0
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_DEFAULT                        MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_INIT_ENUM                      ENABLE
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_DISABLE                        MK_ENUM_CONST(0)
#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_ENABLE                 MK_ENUM_CONST(1)

#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_SHIFT                     MK_SHIFT_CONST(16)
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_SHIFT)
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_RANGE                     16:16
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_MSB                       MK_SHIFT_CONST(16)
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_LSB                       MK_SHIFT_CONST(16)
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_WOFFSET                   0x0
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_INIT_ENUM                 DISABLE
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_DISABLE                   MK_ENUM_CONST(0)
#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_ENABLE                    MK_ENUM_CONST(1)

#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT                    MK_SHIFT_CONST(15)
#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT)
#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_RANGE                    15:15
#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_MSB                      MK_SHIFT_CONST(15)
#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_LSB                      MK_SHIFT_CONST(15)
#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_WOFFSET                  0x0
#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_SHIFT                       MK_SHIFT_CONST(12)
#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_FIELD                       MK_FIELD_CONST(0x7, I2C_I2C_CNFG_0_DEBOUNCE_CNT_SHIFT)
#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_RANGE                       14:12
#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_MSB                 MK_SHIFT_CONST(14)
#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_LSB                 MK_SHIFT_CONST(12)
#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_WOFFSET                     0x0
#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_SHIFT                     MK_SHIFT_CONST(11)
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_NEW_MASTER_FSM_SHIFT)
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_RANGE                     11:11
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_MSB                       MK_SHIFT_CONST(11)
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_LSB                       MK_SHIFT_CONST(11)
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_WOFFSET                   0x0
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_DEFAULT                   MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_DISABLE                   MK_ENUM_CONST(0)
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_ENABLE                    MK_ENUM_CONST(1)

#define I2C_I2C_CNFG_0_PACKET_MODE_EN_SHIFT                     MK_SHIFT_CONST(10)
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_PACKET_MODE_EN_SHIFT)
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_RANGE                     10:10
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_MSB                       MK_SHIFT_CONST(10)
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_LSB                       MK_SHIFT_CONST(10)
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_WOFFSET                   0x0
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_NOP                       MK_ENUM_CONST(0)
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_GO                        MK_ENUM_CONST(1)

#define I2C_I2C_CNFG_0_SEND_SHIFT                       MK_SHIFT_CONST(9)
#define I2C_I2C_CNFG_0_SEND_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_SEND_SHIFT)
#define I2C_I2C_CNFG_0_SEND_RANGE                       9:9
#define I2C_I2C_CNFG_0_SEND_MSB                 MK_SHIFT_CONST(9)
#define I2C_I2C_CNFG_0_SEND_LSB                 MK_SHIFT_CONST(9)
#define I2C_I2C_CNFG_0_SEND_WOFFSET                     0x0
#define I2C_I2C_CNFG_0_SEND_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_SEND_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_SEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_SEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_SEND_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_SEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_SEND_NOP                 MK_ENUM_CONST(0)
#define I2C_I2C_CNFG_0_SEND_GO                  MK_ENUM_CONST(1)

#define I2C_I2C_CNFG_0_NOACK_SHIFT                      MK_SHIFT_CONST(8)
#define I2C_I2C_CNFG_0_NOACK_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_NOACK_SHIFT)
#define I2C_I2C_CNFG_0_NOACK_RANGE                      8:8
#define I2C_I2C_CNFG_0_NOACK_MSB                        MK_SHIFT_CONST(8)
#define I2C_I2C_CNFG_0_NOACK_LSB                        MK_SHIFT_CONST(8)
#define I2C_I2C_CNFG_0_NOACK_WOFFSET                    0x0
#define I2C_I2C_CNFG_0_NOACK_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_NOACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_NOACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_NOACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_NOACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_NOACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_NOACK_DISABLE                    MK_ENUM_CONST(0)
#define I2C_I2C_CNFG_0_NOACK_ENABLE                     MK_ENUM_CONST(1)

#define I2C_I2C_CNFG_0_CMD2_SHIFT                       MK_SHIFT_CONST(7)
#define I2C_I2C_CNFG_0_CMD2_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_CMD2_SHIFT)
#define I2C_I2C_CNFG_0_CMD2_RANGE                       7:7
#define I2C_I2C_CNFG_0_CMD2_MSB                 MK_SHIFT_CONST(7)
#define I2C_I2C_CNFG_0_CMD2_LSB                 MK_SHIFT_CONST(7)
#define I2C_I2C_CNFG_0_CMD2_WOFFSET                     0x0
#define I2C_I2C_CNFG_0_CMD2_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_CMD2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_CMD2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_CMD2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_CMD2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_CMD2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_CMD2_DISABLE                     MK_ENUM_CONST(0)
#define I2C_I2C_CNFG_0_CMD2_ENABLE                      MK_ENUM_CONST(1)

#define I2C_I2C_CNFG_0_CMD1_SHIFT                       MK_SHIFT_CONST(6)
#define I2C_I2C_CNFG_0_CMD1_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_CMD1_SHIFT)
#define I2C_I2C_CNFG_0_CMD1_RANGE                       6:6
#define I2C_I2C_CNFG_0_CMD1_MSB                 MK_SHIFT_CONST(6)
#define I2C_I2C_CNFG_0_CMD1_LSB                 MK_SHIFT_CONST(6)
#define I2C_I2C_CNFG_0_CMD1_WOFFSET                     0x0
#define I2C_I2C_CNFG_0_CMD1_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_CMD1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_CMD1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_CMD1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_CMD1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_CMD1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_CMD1_DISABLE                     MK_ENUM_CONST(0)
#define I2C_I2C_CNFG_0_CMD1_ENABLE                      MK_ENUM_CONST(1)

#define I2C_I2C_CNFG_0_START_SHIFT                      MK_SHIFT_CONST(5)
#define I2C_I2C_CNFG_0_START_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_START_SHIFT)
#define I2C_I2C_CNFG_0_START_RANGE                      5:5
#define I2C_I2C_CNFG_0_START_MSB                        MK_SHIFT_CONST(5)
#define I2C_I2C_CNFG_0_START_LSB                        MK_SHIFT_CONST(5)
#define I2C_I2C_CNFG_0_START_WOFFSET                    0x0
#define I2C_I2C_CNFG_0_START_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_START_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_START_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_START_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_START_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_START_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_START_DISABLE                    MK_ENUM_CONST(0)
#define I2C_I2C_CNFG_0_START_ENABLE                     MK_ENUM_CONST(1)

#define I2C_I2C_CNFG_0_SLV2_SHIFT                       MK_SHIFT_CONST(4)
#define I2C_I2C_CNFG_0_SLV2_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_SLV2_SHIFT)
#define I2C_I2C_CNFG_0_SLV2_RANGE                       4:4
#define I2C_I2C_CNFG_0_SLV2_MSB                 MK_SHIFT_CONST(4)
#define I2C_I2C_CNFG_0_SLV2_LSB                 MK_SHIFT_CONST(4)
#define I2C_I2C_CNFG_0_SLV2_WOFFSET                     0x0
#define I2C_I2C_CNFG_0_SLV2_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_SLV2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_SLV2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_SLV2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_SLV2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_SLV2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_SLV2_DISABLE                     MK_ENUM_CONST(0)
#define I2C_I2C_CNFG_0_SLV2_ENABLE                      MK_ENUM_CONST(1)

#define I2C_I2C_CNFG_0_LENGTH_SHIFT                     MK_SHIFT_CONST(1)
#define I2C_I2C_CNFG_0_LENGTH_FIELD                     MK_FIELD_CONST(0x7, I2C_I2C_CNFG_0_LENGTH_SHIFT)
#define I2C_I2C_CNFG_0_LENGTH_RANGE                     3:1
#define I2C_I2C_CNFG_0_LENGTH_MSB                       MK_SHIFT_CONST(3)
#define I2C_I2C_CNFG_0_LENGTH_LSB                       MK_SHIFT_CONST(1)
#define I2C_I2C_CNFG_0_LENGTH_WOFFSET                   0x0
#define I2C_I2C_CNFG_0_LENGTH_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_LENGTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define I2C_I2C_CNFG_0_LENGTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_LENGTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_LENGTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_LENGTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define I2C_I2C_CNFG_0_A_MOD_SHIFT                      MK_SHIFT_CONST(0)
#define I2C_I2C_CNFG_0_A_MOD_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_A_MOD_SHIFT)
#define I2C_I2C_CNFG_0_A_MOD_RANGE                      0:0
#define I2C_I2C_CNFG_0_A_MOD_MSB                        MK_SHIFT_CONST(0)
#define I2C_I2C_CNFG_0_A_MOD_LSB                        MK_SHIFT_CONST(0)
#define I2C_I2C_CNFG_0_A_MOD_WOFFSET                    0x0
#define I2C_I2C_CNFG_0_A_MOD_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_A_MOD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_A_MOD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_A_MOD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_A_MOD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_CNFG_0_A_MOD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_CNFG_0_A_MOD_SEVEN_BIT_DEVICE_ADDRESS                   MK_ENUM_CONST(0)
#define I2C_I2C_CNFG_0_A_MOD_TEN_BIT_DEVICE_ADDRESS                     MK_ENUM_CONST(1)

// Register I2C_I2C_CMD_ADDR0_0
#define I2C_I2C_CMD_ADDR0_0                     MK_ADDR_CONST(0x4)
#define I2C_I2C_CMD_ADDR0_0_SECURE                      0x0
#define I2C_I2C_CMD_ADDR0_0_DUAL                        0x0
#define I2C_I2C_CMD_ADDR0_0_SCR                         0
#define I2C_I2C_CMD_ADDR0_0_SCRREG                      0
#define I2C_I2C_CMD_ADDR0_0_WORD_COUNT                  0x1
#define I2C_I2C_CMD_ADDR0_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR0_0_RESET_MASK                  MK_MASK_CONST(0x3ff)
#define I2C_I2C_CMD_ADDR0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR0_0_READ_MASK                   MK_MASK_CONST(0x3ff)
#define I2C_I2C_CMD_ADDR0_0_WRITE_MASK                  MK_MASK_CONST(0x3ff)
#define I2C_I2C_CMD_ADDR0_0_ADDR0_SHIFT                 MK_SHIFT_CONST(0)
#define I2C_I2C_CMD_ADDR0_0_ADDR0_FIELD                 MK_FIELD_CONST(0x3ff, I2C_I2C_CMD_ADDR0_0_ADDR0_SHIFT)
#define I2C_I2C_CMD_ADDR0_0_ADDR0_RANGE                 9:0
#define I2C_I2C_CMD_ADDR0_0_ADDR0_MSB                   MK_SHIFT_CONST(9)
#define I2C_I2C_CMD_ADDR0_0_ADDR0_LSB                   MK_SHIFT_CONST(0)
#define I2C_I2C_CMD_ADDR0_0_ADDR0_WOFFSET                       0x0
#define I2C_I2C_CMD_ADDR0_0_ADDR0_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR0_0_ADDR0_DEFAULT_MASK                  MK_MASK_CONST(0x3ff)
#define I2C_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR0_0_ADDR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR0_0_ADDR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Register I2C_I2C_CMD_ADDR1_0
#define I2C_I2C_CMD_ADDR1_0                     MK_ADDR_CONST(0x8)
#define I2C_I2C_CMD_ADDR1_0_SECURE                      0x0
#define I2C_I2C_CMD_ADDR1_0_DUAL                        0x0
#define I2C_I2C_CMD_ADDR1_0_SCR                         0
#define I2C_I2C_CMD_ADDR1_0_SCRREG                      0
#define I2C_I2C_CMD_ADDR1_0_WORD_COUNT                  0x1
#define I2C_I2C_CMD_ADDR1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR1_0_RESET_MASK                  MK_MASK_CONST(0x3ff)
#define I2C_I2C_CMD_ADDR1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR1_0_READ_MASK                   MK_MASK_CONST(0x3ff)
#define I2C_I2C_CMD_ADDR1_0_WRITE_MASK                  MK_MASK_CONST(0x3ff)
#define I2C_I2C_CMD_ADDR1_0_ADDR1_SHIFT                 MK_SHIFT_CONST(0)
#define I2C_I2C_CMD_ADDR1_0_ADDR1_FIELD                 MK_FIELD_CONST(0x3ff, I2C_I2C_CMD_ADDR1_0_ADDR1_SHIFT)
#define I2C_I2C_CMD_ADDR1_0_ADDR1_RANGE                 9:0
#define I2C_I2C_CMD_ADDR1_0_ADDR1_MSB                   MK_SHIFT_CONST(9)
#define I2C_I2C_CMD_ADDR1_0_ADDR1_LSB                   MK_SHIFT_CONST(0)
#define I2C_I2C_CMD_ADDR1_0_ADDR1_WOFFSET                       0x0
#define I2C_I2C_CMD_ADDR1_0_ADDR1_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR1_0_ADDR1_DEFAULT_MASK                  MK_MASK_CONST(0x3ff)
#define I2C_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR1_0_ADDR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_ADDR1_0_ADDR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Register I2C_I2C_CMD_DATA1_0
#define I2C_I2C_CMD_DATA1_0                     MK_ADDR_CONST(0xc)
#define I2C_I2C_CMD_DATA1_0_SECURE                      0x0
#define I2C_I2C_CMD_DATA1_0_DUAL                        0x0
#define I2C_I2C_CMD_DATA1_0_SCR                         0
#define I2C_I2C_CMD_DATA1_0_SCRREG                      0
#define I2C_I2C_CMD_DATA1_0_WORD_COUNT                  0x1
#define I2C_I2C_CMD_DATA1_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define I2C_I2C_CMD_DATA1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define I2C_I2C_CMD_DATA1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define I2C_I2C_CMD_DATA1_0_DATA4_SHIFT                 MK_SHIFT_CONST(24)
#define I2C_I2C_CMD_DATA1_0_DATA4_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA1_0_DATA4_SHIFT)
#define I2C_I2C_CMD_DATA1_0_DATA4_RANGE                 31:24
#define I2C_I2C_CMD_DATA1_0_DATA4_MSB                   MK_SHIFT_CONST(31)
#define I2C_I2C_CMD_DATA1_0_DATA4_LSB                   MK_SHIFT_CONST(24)
#define I2C_I2C_CMD_DATA1_0_DATA4_WOFFSET                       0x0
#define I2C_I2C_CMD_DATA1_0_DATA4_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA4_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define I2C_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define I2C_I2C_CMD_DATA1_0_DATA3_SHIFT                 MK_SHIFT_CONST(16)
#define I2C_I2C_CMD_DATA1_0_DATA3_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA1_0_DATA3_SHIFT)
#define I2C_I2C_CMD_DATA1_0_DATA3_RANGE                 23:16
#define I2C_I2C_CMD_DATA1_0_DATA3_MSB                   MK_SHIFT_CONST(23)
#define I2C_I2C_CMD_DATA1_0_DATA3_LSB                   MK_SHIFT_CONST(16)
#define I2C_I2C_CMD_DATA1_0_DATA3_WOFFSET                       0x0
#define I2C_I2C_CMD_DATA1_0_DATA3_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA3_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define I2C_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define I2C_I2C_CMD_DATA1_0_DATA2_SHIFT                 MK_SHIFT_CONST(8)
#define I2C_I2C_CMD_DATA1_0_DATA2_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA1_0_DATA2_SHIFT)
#define I2C_I2C_CMD_DATA1_0_DATA2_RANGE                 15:8
#define I2C_I2C_CMD_DATA1_0_DATA2_MSB                   MK_SHIFT_CONST(15)
#define I2C_I2C_CMD_DATA1_0_DATA2_LSB                   MK_SHIFT_CONST(8)
#define I2C_I2C_CMD_DATA1_0_DATA2_WOFFSET                       0x0
#define I2C_I2C_CMD_DATA1_0_DATA2_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA2_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define I2C_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define I2C_I2C_CMD_DATA1_0_DATA1_SHIFT                 MK_SHIFT_CONST(0)
#define I2C_I2C_CMD_DATA1_0_DATA1_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA1_0_DATA1_SHIFT)
#define I2C_I2C_CMD_DATA1_0_DATA1_RANGE                 7:0
#define I2C_I2C_CMD_DATA1_0_DATA1_MSB                   MK_SHIFT_CONST(7)
#define I2C_I2C_CMD_DATA1_0_DATA1_LSB                   MK_SHIFT_CONST(0)
#define I2C_I2C_CMD_DATA1_0_DATA1_WOFFSET                       0x0
#define I2C_I2C_CMD_DATA1_0_DATA1_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA1_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define I2C_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA1_0_DATA1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Register I2C_I2C_CMD_DATA2_0
#define I2C_I2C_CMD_DATA2_0                     MK_ADDR_CONST(0x10)
#define I2C_I2C_CMD_DATA2_0_SECURE                      0x0
#define I2C_I2C_CMD_DATA2_0_DUAL                        0x0
#define I2C_I2C_CMD_DATA2_0_SCR                         0
#define I2C_I2C_CMD_DATA2_0_SCRREG                      0
#define I2C_I2C_CMD_DATA2_0_WORD_COUNT                  0x1
#define I2C_I2C_CMD_DATA2_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
#define I2C_I2C_CMD_DATA2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
#define I2C_I2C_CMD_DATA2_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
#define I2C_I2C_CMD_DATA2_0_DATA8_SHIFT                 MK_SHIFT_CONST(24)
#define I2C_I2C_CMD_DATA2_0_DATA8_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA2_0_DATA8_SHIFT)
#define I2C_I2C_CMD_DATA2_0_DATA8_RANGE                 31:24
#define I2C_I2C_CMD_DATA2_0_DATA8_MSB                   MK_SHIFT_CONST(31)
#define I2C_I2C_CMD_DATA2_0_DATA8_LSB                   MK_SHIFT_CONST(24)
#define I2C_I2C_CMD_DATA2_0_DATA8_WOFFSET                       0x0
#define I2C_I2C_CMD_DATA2_0_DATA8_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA8_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define I2C_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA8_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA8_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define I2C_I2C_CMD_DATA2_0_DATA7_SHIFT                 MK_SHIFT_CONST(16)
#define I2C_I2C_CMD_DATA2_0_DATA7_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA2_0_DATA7_SHIFT)
#define I2C_I2C_CMD_DATA2_0_DATA7_RANGE                 23:16
#define I2C_I2C_CMD_DATA2_0_DATA7_MSB                   MK_SHIFT_CONST(23)
#define I2C_I2C_CMD_DATA2_0_DATA7_LSB                   MK_SHIFT_CONST(16)
#define I2C_I2C_CMD_DATA2_0_DATA7_WOFFSET                       0x0
#define I2C_I2C_CMD_DATA2_0_DATA7_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA7_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define I2C_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define I2C_I2C_CMD_DATA2_0_DATA6_SHIFT                 MK_SHIFT_CONST(8)
#define I2C_I2C_CMD_DATA2_0_DATA6_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA2_0_DATA6_SHIFT)
#define I2C_I2C_CMD_DATA2_0_DATA6_RANGE                 15:8
#define I2C_I2C_CMD_DATA2_0_DATA6_MSB                   MK_SHIFT_CONST(15)
#define I2C_I2C_CMD_DATA2_0_DATA6_LSB                   MK_SHIFT_CONST(8)
#define I2C_I2C_CMD_DATA2_0_DATA6_WOFFSET                       0x0
#define I2C_I2C_CMD_DATA2_0_DATA6_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA6_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define I2C_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define I2C_I2C_CMD_DATA2_0_DATA5_SHIFT                 MK_SHIFT_CONST(0)
#define I2C_I2C_CMD_DATA2_0_DATA5_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA2_0_DATA5_SHIFT)
#define I2C_I2C_CMD_DATA2_0_DATA5_RANGE                 7:0
#define I2C_I2C_CMD_DATA2_0_DATA5_MSB                   MK_SHIFT_CONST(7)
#define I2C_I2C_CMD_DATA2_0_DATA5_LSB                   MK_SHIFT_CONST(0)
#define I2C_I2C_CMD_DATA2_0_DATA5_WOFFSET                       0x0
#define I2C_I2C_CMD_DATA2_0_DATA5_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA5_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define I2C_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_CMD_DATA2_0_DATA5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Reserved address 0x14

// Reserved address 0x18

// Register I2C_I2C_STATUS_0
#define I2C_I2C_STATUS_0                        MK_ADDR_CONST(0x1c)
#define I2C_I2C_STATUS_0_SECURE                         0x0
#define I2C_I2C_STATUS_0_DUAL                   0x0
#define I2C_I2C_STATUS_0_SCR                    0
#define I2C_I2C_STATUS_0_SCRREG                         0
#define I2C_I2C_STATUS_0_WORD_COUNT                     0x1
#define I2C_I2C_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1ff)
#define I2C_I2C_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1ff)
#define I2C_I2C_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_BUSY_SHIFT                     MK_SHIFT_CONST(8)
#define I2C_I2C_STATUS_0_BUSY_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_STATUS_0_BUSY_SHIFT)
#define I2C_I2C_STATUS_0_BUSY_RANGE                     8:8
#define I2C_I2C_STATUS_0_BUSY_MSB                       MK_SHIFT_CONST(8)
#define I2C_I2C_STATUS_0_BUSY_LSB                       MK_SHIFT_CONST(8)
#define I2C_I2C_STATUS_0_BUSY_WOFFSET                   0x0
#define I2C_I2C_STATUS_0_BUSY_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_BUSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_STATUS_0_BUSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_BUSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_BUSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_BUSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_STATUS_0_BUSY_NOT_BUSY                  MK_ENUM_CONST(0)
#define I2C_I2C_STATUS_0_BUSY_BUSY                      MK_ENUM_CONST(1)

#define I2C_I2C_STATUS_0_CMD2_STAT_SHIFT                        MK_SHIFT_CONST(4)
#define I2C_I2C_STATUS_0_CMD2_STAT_FIELD                        MK_FIELD_CONST(0xf, I2C_I2C_STATUS_0_CMD2_STAT_SHIFT)
#define I2C_I2C_STATUS_0_CMD2_STAT_RANGE                        7:4
#define I2C_I2C_STATUS_0_CMD2_STAT_MSB                  MK_SHIFT_CONST(7)
#define I2C_I2C_STATUS_0_CMD2_STAT_LSB                  MK_SHIFT_CONST(4)
#define I2C_I2C_STATUS_0_CMD2_STAT_WOFFSET                      0x0
#define I2C_I2C_STATUS_0_CMD2_STAT_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_CMD2_STAT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define I2C_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_CMD2_STAT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_CMD2_STAT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_XFER_SUCCESSFUL                  MK_ENUM_CONST(0)
#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE1                  MK_ENUM_CONST(1)
#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE2                  MK_ENUM_CONST(2)
#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE3                  MK_ENUM_CONST(3)
#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE4                  MK_ENUM_CONST(4)
#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE5                  MK_ENUM_CONST(5)
#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE6                  MK_ENUM_CONST(6)
#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE7                  MK_ENUM_CONST(7)
#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE8                  MK_ENUM_CONST(8)
#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE9                  MK_ENUM_CONST(9)
#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE10                 MK_ENUM_CONST(10)

#define I2C_I2C_STATUS_0_CMD1_STAT_SHIFT                        MK_SHIFT_CONST(0)
#define I2C_I2C_STATUS_0_CMD1_STAT_FIELD                        MK_FIELD_CONST(0xf, I2C_I2C_STATUS_0_CMD1_STAT_SHIFT)
#define I2C_I2C_STATUS_0_CMD1_STAT_RANGE                        3:0
#define I2C_I2C_STATUS_0_CMD1_STAT_MSB                  MK_SHIFT_CONST(3)
#define I2C_I2C_STATUS_0_CMD1_STAT_LSB                  MK_SHIFT_CONST(0)
#define I2C_I2C_STATUS_0_CMD1_STAT_WOFFSET                      0x0
#define I2C_I2C_STATUS_0_CMD1_STAT_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_CMD1_STAT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define I2C_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_CMD1_STAT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_STATUS_0_CMD1_STAT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_XFER_SUCCESSFUL                  MK_ENUM_CONST(0)
#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE1                  MK_ENUM_CONST(1)
#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE2                  MK_ENUM_CONST(2)
#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE3                  MK_ENUM_CONST(3)
#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE4                  MK_ENUM_CONST(4)
#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE5                  MK_ENUM_CONST(5)
#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE6                  MK_ENUM_CONST(6)
#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE7                  MK_ENUM_CONST(7)
#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE8                  MK_ENUM_CONST(8)
#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE9                  MK_ENUM_CONST(9)
#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE10                 MK_ENUM_CONST(10)

#define DIVCLK_SETUP_PERIOD     6
#define FIFO_DEPTH      128
#define SLAVE1  0
#define SLAVE2  1
#define TLOW_MEXT_CNT_WIDTH     8
#define TLOW_SEXT_CNT_WIDTH     8
#define TIMEOUT_CNT_WIDTH       8

// Register I2C_I2C_SL_CNFG_0
#define I2C_I2C_SL_CNFG_0                       MK_ADDR_CONST(0x20)
#define I2C_I2C_SL_CNFG_0_SECURE                        0x0
#define I2C_I2C_SL_CNFG_0_DUAL                  0x0
#define I2C_I2C_SL_CNFG_0_SCR                   0
#define I2C_I2C_SL_CNFG_0_SCRREG                        0
#define I2C_I2C_SL_CNFG_0_WORD_COUNT                    0x1
#define I2C_I2C_SL_CNFG_0_RESET_VAL                     MK_MASK_CONST(0x4)
#define I2C_I2C_SL_CNFG_0_RESET_MASK                    MK_MASK_CONST(0x3fffff)
#define I2C_I2C_SL_CNFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_READ_MASK                     MK_MASK_CONST(0x3fffff)
#define I2C_I2C_SL_CNFG_0_WRITE_MASK                    MK_MASK_CONST(0x3ffffb)
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_SHIFT                     MK_SHIFT_CONST(21)
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_SHIFT)
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_RANGE                     21:21
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_MSB                       MK_SHIFT_CONST(21)
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_LSB                       MK_SHIFT_CONST(21)
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_WOFFSET                   0x0
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_DISABLE                   MK_ENUM_CONST(0)
#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_ENABLE                    MK_ENUM_CONST(1)

#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_SHIFT                    MK_SHIFT_CONST(20)
#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_SHIFT)
#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_RANGE                    20:20
#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_MSB                      MK_SHIFT_CONST(20)
#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_LSB                      MK_SHIFT_CONST(20)
#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_WOFFSET                  0x0
#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_DISABLE                  MK_ENUM_CONST(0)
#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_ENABLE                   MK_ENUM_CONST(1)

#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_SHIFT                     MK_SHIFT_CONST(8)
#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_FIELD                     MK_FIELD_CONST(0xfff, I2C_I2C_SL_CNFG_0_BUFFER_SIZE_SHIFT)
#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_RANGE                     19:8
#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_MSB                       MK_SHIFT_CONST(19)
#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_LSB                       MK_SHIFT_CONST(8)
#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_WOFFSET                   0x0
#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_DEFAULT_MASK                      MK_MASK_CONST(0xfff)
#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_SHIFT                     MK_SHIFT_CONST(7)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_SHIFT)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_RANGE                     7:7
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_MSB                       MK_SHIFT_CONST(7)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_LSB                       MK_SHIFT_CONST(7)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_WOFFSET                   0x0
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_DISABLE                   MK_ENUM_CONST(0)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_ENABLE                    MK_ENUM_CONST(1)

#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_SHIFT                   MK_SHIFT_CONST(6)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_SHIFT)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_RANGE                   6:6
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_MSB                     MK_SHIFT_CONST(6)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_LSB                     MK_SHIFT_CONST(6)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_WOFFSET                 0x0
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_DISABLE                 MK_ENUM_CONST(0)
#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_ENABLE                  MK_ENUM_CONST(1)

#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_SHIFT                 MK_SHIFT_CONST(5)
#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_SHIFT)
#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_RANGE                 5:5
#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_MSB                   MK_SHIFT_CONST(5)
#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_LSB                   MK_SHIFT_CONST(5)
#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_WOFFSET                       0x0
#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_DISABLE                       MK_ENUM_CONST(0)
#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_ENABLE                        MK_ENUM_CONST(1)

#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_SHIFT                     MK_SHIFT_CONST(4)
#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_PKT_MODE_EN_SHIFT)
#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_RANGE                     4:4
#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_MSB                       MK_SHIFT_CONST(4)
#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_LSB                       MK_SHIFT_CONST(4)
#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_WOFFSET                   0x0
#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_DISABLE                   MK_ENUM_CONST(0)
#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_ENABLE                    MK_ENUM_CONST(1)

#define I2C_I2C_SL_CNFG_0_ENABLE_SL_SHIFT                       MK_SHIFT_CONST(3)
#define I2C_I2C_SL_CNFG_0_ENABLE_SL_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_ENABLE_SL_SHIFT)
#define I2C_I2C_SL_CNFG_0_ENABLE_SL_RANGE                       3:3
#define I2C_I2C_SL_CNFG_0_ENABLE_SL_MSB                 MK_SHIFT_CONST(3)
#define I2C_I2C_SL_CNFG_0_ENABLE_SL_LSB                 MK_SHIFT_CONST(3)
#define I2C_I2C_SL_CNFG_0_ENABLE_SL_WOFFSET                     0x0
#define I2C_I2C_SL_CNFG_0_ENABLE_SL_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ENABLE_SL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_ENABLE_SL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ENABLE_SL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ENABLE_SL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_ENABLE_SL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_ENABLE_SL_DISABLE                     MK_ENUM_CONST(0)
#define I2C_I2C_SL_CNFG_0_ENABLE_SL_ENABLE                      MK_ENUM_CONST(1)

#define I2C_I2C_SL_CNFG_0_NEWSL_SHIFT                   MK_SHIFT_CONST(2)
#define I2C_I2C_SL_CNFG_0_NEWSL_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_NEWSL_SHIFT)
#define I2C_I2C_SL_CNFG_0_NEWSL_RANGE                   2:2
#define I2C_I2C_SL_CNFG_0_NEWSL_MSB                     MK_SHIFT_CONST(2)
#define I2C_I2C_SL_CNFG_0_NEWSL_LSB                     MK_SHIFT_CONST(2)
#define I2C_I2C_SL_CNFG_0_NEWSL_WOFFSET                 0x0
#define I2C_I2C_SL_CNFG_0_NEWSL_DEFAULT                 MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_NEWSL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_NEWSL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_NEWSL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_NEWSL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_NEWSL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_NEWSL_DISABLE                 MK_ENUM_CONST(0)
#define I2C_I2C_SL_CNFG_0_NEWSL_ENABLE                  MK_ENUM_CONST(1)

#define I2C_I2C_SL_CNFG_0_NACK_SHIFT                    MK_SHIFT_CONST(1)
#define I2C_I2C_SL_CNFG_0_NACK_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_NACK_SHIFT)
#define I2C_I2C_SL_CNFG_0_NACK_RANGE                    1:1
#define I2C_I2C_SL_CNFG_0_NACK_MSB                      MK_SHIFT_CONST(1)
#define I2C_I2C_SL_CNFG_0_NACK_LSB                      MK_SHIFT_CONST(1)
#define I2C_I2C_SL_CNFG_0_NACK_WOFFSET                  0x0
#define I2C_I2C_SL_CNFG_0_NACK_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_NACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_NACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_NACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_NACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_NACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_NACK_DISABLE                  MK_ENUM_CONST(0)
#define I2C_I2C_SL_CNFG_0_NACK_ENABLE                   MK_ENUM_CONST(1)

#define I2C_I2C_SL_CNFG_0_RESP_SHIFT                    MK_SHIFT_CONST(0)
#define I2C_I2C_SL_CNFG_0_RESP_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_RESP_SHIFT)
#define I2C_I2C_SL_CNFG_0_RESP_RANGE                    0:0
#define I2C_I2C_SL_CNFG_0_RESP_MSB                      MK_SHIFT_CONST(0)
#define I2C_I2C_SL_CNFG_0_RESP_LSB                      MK_SHIFT_CONST(0)
#define I2C_I2C_SL_CNFG_0_RESP_WOFFSET                  0x0
#define I2C_I2C_SL_CNFG_0_RESP_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_RESP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_RESP_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_RESP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_RESP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_CNFG_0_RESP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_SL_CNFG_0_RESP_DISABLE                  MK_ENUM_CONST(0)
#define I2C_I2C_SL_CNFG_0_RESP_ENABLE                   MK_ENUM_CONST(1)

// Register I2C_I2C_SL_RCVD_0
#define I2C_I2C_SL_RCVD_0                       MK_ADDR_CONST(0x24)
#define I2C_I2C_SL_RCVD_0_SECURE                        0x0
#define I2C_I2C_SL_RCVD_0_DUAL                  0x0
#define I2C_I2C_SL_RCVD_0_SCR                   0
#define I2C_I2C_SL_RCVD_0_SCRREG                        0
#define I2C_I2C_SL_RCVD_0_WORD_COUNT                    0x1
#define I2C_I2C_SL_RCVD_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_RCVD_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define I2C_I2C_SL_RCVD_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_RCVD_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_RCVD_0_READ_MASK                     MK_MASK_CONST(0xff)
#define I2C_I2C_SL_RCVD_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define I2C_I2C_SL_RCVD_0_SL_DATA_SHIFT                 MK_SHIFT_CONST(0)
#define I2C_I2C_SL_RCVD_0_SL_DATA_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_SL_RCVD_0_SL_DATA_SHIFT)
#define I2C_I2C_SL_RCVD_0_SL_DATA_RANGE                 7:0
#define I2C_I2C_SL_RCVD_0_SL_DATA_MSB                   MK_SHIFT_CONST(7)
#define I2C_I2C_SL_RCVD_0_SL_DATA_LSB                   MK_SHIFT_CONST(0)
#define I2C_I2C_SL_RCVD_0_SL_DATA_WOFFSET                       0x0
#define I2C_I2C_SL_RCVD_0_SL_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_RCVD_0_SL_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define I2C_I2C_SL_RCVD_0_SL_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_RCVD_0_SL_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_RCVD_0_SL_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_RCVD_0_SL_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Register I2C_I2C_SL_STATUS_0
#define I2C_I2C_SL_STATUS_0                     MK_ADDR_CONST(0x28)
#define I2C_I2C_SL_STATUS_0_SECURE                      0x0
#define I2C_I2C_SL_STATUS_0_DUAL                        0x0
#define I2C_I2C_SL_STATUS_0_SCR                         0
#define I2C_I2C_SL_STATUS_0_SCRREG                      0
#define I2C_I2C_SL_STATUS_0_WORD_COUNT                  0x1
#define I2C_I2C_SL_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7fff)
#define I2C_I2C_SL_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7fff)
#define I2C_I2C_SL_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0xfd)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SHIFT                   MK_SHIFT_CONST(8)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_FIELD                   MK_FIELD_CONST(0x7f, I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SHIFT)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_RANGE                   14:8
#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_MSB                     MK_SHIFT_CONST(14)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_LSB                     MK_SHIFT_CONST(8)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_WOFFSET                 0x0
#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SHIFT                   MK_SHIFT_CONST(7)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SHIFT)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_RANGE                   7:7
#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_MSB                     MK_SHIFT_CONST(7)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_LSB                     MK_SHIFT_CONST(7)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_WOFFSET                 0x0
#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define I2C_I2C_SL_STATUS_0_REPROG_SL_SHIFT                     MK_SHIFT_CONST(6)
#define I2C_I2C_SL_STATUS_0_REPROG_SL_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_REPROG_SL_SHIFT)
#define I2C_I2C_SL_STATUS_0_REPROG_SL_RANGE                     6:6
#define I2C_I2C_SL_STATUS_0_REPROG_SL_MSB                       MK_SHIFT_CONST(6)
#define I2C_I2C_SL_STATUS_0_REPROG_SL_LSB                       MK_SHIFT_CONST(6)
#define I2C_I2C_SL_STATUS_0_REPROG_SL_WOFFSET                   0x0
#define I2C_I2C_SL_STATUS_0_REPROG_SL_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_REPROG_SL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_SL_STATUS_0_REPROG_SL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_REPROG_SL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_REPROG_SL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_REPROG_SL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define I2C_I2C_SL_STATUS_0_RST_SL_SHIFT                        MK_SHIFT_CONST(5)
#define I2C_I2C_SL_STATUS_0_RST_SL_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_RST_SL_SHIFT)
#define I2C_I2C_SL_STATUS_0_RST_SL_RANGE                        5:5
#define I2C_I2C_SL_STATUS_0_RST_SL_MSB                  MK_SHIFT_CONST(5)
#define I2C_I2C_SL_STATUS_0_RST_SL_LSB                  MK_SHIFT_CONST(5)
#define I2C_I2C_SL_STATUS_0_RST_SL_WOFFSET                      0x0
#define I2C_I2C_SL_STATUS_0_RST_SL_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_RST_SL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_SL_STATUS_0_RST_SL_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_RST_SL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_RST_SL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_RST_SL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define I2C_I2C_SL_STATUS_0_END_TRANS_SHIFT                     MK_SHIFT_CONST(4)
#define I2C_I2C_SL_STATUS_0_END_TRANS_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_END_TRANS_SHIFT)
#define I2C_I2C_SL_STATUS_0_END_TRANS_RANGE                     4:4
#define I2C_I2C_SL_STATUS_0_END_TRANS_MSB                       MK_SHIFT_CONST(4)
#define I2C_I2C_SL_STATUS_0_END_TRANS_LSB                       MK_SHIFT_CONST(4)
#define I2C_I2C_SL_STATUS_0_END_TRANS_WOFFSET                   0x0
#define I2C_I2C_SL_STATUS_0_END_TRANS_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_END_TRANS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_SL_STATUS_0_END_TRANS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_END_TRANS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_END_TRANS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_END_TRANS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define I2C_I2C_SL_STATUS_0_SL_IRQ_SHIFT                        MK_SHIFT_CONST(3)
#define I2C_I2C_SL_STATUS_0_SL_IRQ_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_SL_IRQ_SHIFT)
#define I2C_I2C_SL_STATUS_0_SL_IRQ_RANGE                        3:3
#define I2C_I2C_SL_STATUS_0_SL_IRQ_MSB                  MK_SHIFT_CONST(3)
#define I2C_I2C_SL_STATUS_0_SL_IRQ_LSB                  MK_SHIFT_CONST(3)
#define I2C_I2C_SL_STATUS_0_SL_IRQ_WOFFSET                      0x0
#define I2C_I2C_SL_STATUS_0_SL_IRQ_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_SL_IRQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_SL_STATUS_0_SL_IRQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_SL_IRQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_SL_IRQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_SL_IRQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_SL_STATUS_0_SL_IRQ_UNSET                        MK_ENUM_CONST(0)
#define I2C_I2C_SL_STATUS_0_SL_IRQ_SET                  MK_ENUM_CONST(1)

#define I2C_I2C_SL_STATUS_0_RCVD_SHIFT                  MK_SHIFT_CONST(2)
#define I2C_I2C_SL_STATUS_0_RCVD_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_RCVD_SHIFT)
#define I2C_I2C_SL_STATUS_0_RCVD_RANGE                  2:2
#define I2C_I2C_SL_STATUS_0_RCVD_MSB                    MK_SHIFT_CONST(2)
#define I2C_I2C_SL_STATUS_0_RCVD_LSB                    MK_SHIFT_CONST(2)
#define I2C_I2C_SL_STATUS_0_RCVD_WOFFSET                        0x0
#define I2C_I2C_SL_STATUS_0_RCVD_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_RCVD_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_I2C_SL_STATUS_0_RCVD_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_RCVD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_RCVD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_RCVD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define I2C_I2C_SL_STATUS_0_RCVD_NO_TRANSACTION_OCCURED                 MK_ENUM_CONST(0)
#define I2C_I2C_SL_STATUS_0_RCVD_TRANSACTION_OCCURED                    MK_ENUM_CONST(1)

#define I2C_I2C_SL_STATUS_0_RNW_SHIFT                   MK_SHIFT_CONST(1)
#define I2C_I2C_SL_STATUS_0_RNW_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_RNW_SHIFT)
#define I2C_I2C_SL_STATUS_0_RNW_RANGE                   1:1
#define I2C_I2C_SL_STATUS_0_RNW_MSB                     MK_SHIFT_CONST(1)
#define I2C_I2C_SL_STATUS_0_RNW_LSB                     MK_SHIFT_CONST(1)
#define I2C_I2C_SL_STATUS_0_RNW_WOFFSET                 0x0
#define I2C_I2C_SL_STATUS_0_RNW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_RNW_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_STATUS_0_RNW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_RNW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_RNW_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_RNW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_SL_STATUS_0_RNW_WRITE                   MK_ENUM_CONST(0)
#define I2C_I2C_SL_STATUS_0_RNW_READ                    MK_ENUM_CONST(1)

#define I2C_I2C_SL_STATUS_0_ZA_SHIFT                    MK_SHIFT_CONST(0)
#define I2C_I2C_SL_STATUS_0_ZA_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_ZA_SHIFT)
#define I2C_I2C_SL_STATUS_0_ZA_RANGE                    0:0
#define I2C_I2C_SL_STATUS_0_ZA_MSB                      MK_SHIFT_CONST(0)
#define I2C_I2C_SL_STATUS_0_ZA_LSB                      MK_SHIFT_CONST(0)
#define I2C_I2C_SL_STATUS_0_ZA_WOFFSET                  0x0
#define I2C_I2C_SL_STATUS_0_ZA_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_ZA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_SL_STATUS_0_ZA_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_ZA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_ZA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_STATUS_0_ZA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_SL_STATUS_0_ZA_NO_SLAVE_RESPONSE                        MK_ENUM_CONST(0)
#define I2C_I2C_SL_STATUS_0_ZA_SLAVE_RESPONSE                   MK_ENUM_CONST(1)

// Register I2C_I2C_SL_ADDR1_0
#define I2C_I2C_SL_ADDR1_0                      MK_ADDR_CONST(0x2c)
#define I2C_I2C_SL_ADDR1_0_SECURE                       0x0
#define I2C_I2C_SL_ADDR1_0_DUAL                         0x0
#define I2C_I2C_SL_ADDR1_0_SCR                  0
#define I2C_I2C_SL_ADDR1_0_SCRREG                       0
#define I2C_I2C_SL_ADDR1_0_WORD_COUNT                   0x1
#define I2C_I2C_SL_ADDR1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR1_0_RESET_MASK                   MK_MASK_CONST(0xffff)
#define I2C_I2C_SL_ADDR1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR1_0_READ_MASK                    MK_MASK_CONST(0xffff)
#define I2C_I2C_SL_ADDR1_0_WRITE_MASK                   MK_MASK_CONST(0xffff)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_SHIFT                       MK_SHIFT_CONST(8)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_FIELD                       MK_FIELD_CONST(0xff, I2C_I2C_SL_ADDR1_0_SL_ADDR1_SHIFT)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_RANGE                       15:8
#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_MSB                 MK_SHIFT_CONST(15)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_LSB                 MK_SHIFT_CONST(8)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_WOFFSET                     0x0
#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SHIFT                       MK_SHIFT_CONST(0)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_FIELD                       MK_FIELD_CONST(0xff, I2C_I2C_SL_ADDR1_0_SL_ADDR0_SHIFT)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_RANGE                       7:0
#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_MSB                 MK_SHIFT_CONST(7)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_LSB                 MK_SHIFT_CONST(0)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_WOFFSET                     0x0
#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

// Register I2C_I2C_SL_ADDR2_0
#define I2C_I2C_SL_ADDR2_0                      MK_ADDR_CONST(0x30)
#define I2C_I2C_SL_ADDR2_0_SECURE                       0x0
#define I2C_I2C_SL_ADDR2_0_DUAL                         0x0
#define I2C_I2C_SL_ADDR2_0_SCR                  0
#define I2C_I2C_SL_ADDR2_0_SCRREG                       0
#define I2C_I2C_SL_ADDR2_0_WORD_COUNT                   0x1
#define I2C_I2C_SL_ADDR2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_RESET_MASK                   MK_MASK_CONST(0x10707)
#define I2C_I2C_SL_ADDR2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_READ_MASK                    MK_MASK_CONST(0x10707)
#define I2C_I2C_SL_ADDR2_0_WRITE_MASK                   MK_MASK_CONST(0x10707)
#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_SHIFT                   MK_SHIFT_CONST(16)
#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_SHIFT)
#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_RANGE                   16:16
#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_MSB                     MK_SHIFT_CONST(16)
#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_LSB                     MK_SHIFT_CONST(16)
#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_WOFFSET                 0x0
#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_SHIFT                    MK_SHIFT_CONST(9)
#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_FIELD                    MK_FIELD_CONST(0x3, I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_SHIFT)
#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_RANGE                    10:9
#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_MSB                      MK_SHIFT_CONST(10)
#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_LSB                      MK_SHIFT_CONST(9)
#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_WOFFSET                  0x0
#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define I2C_I2C_SL_ADDR2_0_SL1_VLD_SHIFT                        MK_SHIFT_CONST(8)
#define I2C_I2C_SL_ADDR2_0_SL1_VLD_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_SL_ADDR2_0_SL1_VLD_SHIFT)
#define I2C_I2C_SL_ADDR2_0_SL1_VLD_RANGE                        8:8
#define I2C_I2C_SL_ADDR2_0_SL1_VLD_MSB                  MK_SHIFT_CONST(8)
#define I2C_I2C_SL_ADDR2_0_SL1_VLD_LSB                  MK_SHIFT_CONST(8)
#define I2C_I2C_SL_ADDR2_0_SL1_VLD_WOFFSET                      0x0
#define I2C_I2C_SL_ADDR2_0_SL1_VLD_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SL1_VLD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_SL_ADDR2_0_SL1_VLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SL1_VLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SL1_VLD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SL1_VLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_SL_ADDR2_0_SL1_VLD_SEVEN_BIT_ADDR_MODE                  MK_ENUM_CONST(0)
#define I2C_I2C_SL_ADDR2_0_SL1_VLD_TEN_BIT_ADDR_MODE                    MK_ENUM_CONST(1)

#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SHIFT                     MK_SHIFT_CONST(1)
#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_FIELD                     MK_FIELD_CONST(0x3, I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SHIFT)
#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_RANGE                     2:1
#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_MSB                       MK_SHIFT_CONST(2)
#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_LSB                       MK_SHIFT_CONST(1)
#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_WOFFSET                   0x0
#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_DEFAULT_MASK                      MK_MASK_CONST(0x3)
#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define I2C_I2C_SL_ADDR2_0_VLD_SHIFT                    MK_SHIFT_CONST(0)
#define I2C_I2C_SL_ADDR2_0_VLD_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_ADDR2_0_VLD_SHIFT)
#define I2C_I2C_SL_ADDR2_0_VLD_RANGE                    0:0
#define I2C_I2C_SL_ADDR2_0_VLD_MSB                      MK_SHIFT_CONST(0)
#define I2C_I2C_SL_ADDR2_0_VLD_LSB                      MK_SHIFT_CONST(0)
#define I2C_I2C_SL_ADDR2_0_VLD_WOFFSET                  0x0
#define I2C_I2C_SL_ADDR2_0_VLD_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_VLD_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_SL_ADDR2_0_VLD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_VLD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_VLD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_ADDR2_0_VLD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_SL_ADDR2_0_VLD_SEVEN_BIT_ADDR_MODE                      MK_ENUM_CONST(0)
#define I2C_I2C_SL_ADDR2_0_VLD_TEN_BIT_ADDR_MODE                        MK_ENUM_CONST(1)

// Register I2C_I2C_TLOW_SEXT_0
#define I2C_I2C_TLOW_SEXT_0                     MK_ADDR_CONST(0x34)
#define I2C_I2C_TLOW_SEXT_0_SECURE                      0x0
#define I2C_I2C_TLOW_SEXT_0_DUAL                        0x0
#define I2C_I2C_TLOW_SEXT_0_SCR                         0
#define I2C_I2C_TLOW_SEXT_0_SCRREG                      0
#define I2C_I2C_TLOW_SEXT_0_WORD_COUNT                  0x1
#define I2C_I2C_TLOW_SEXT_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_RESET_MASK                  MK_MASK_CONST(0xfffffff)
#define I2C_I2C_TLOW_SEXT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_READ_MASK                   MK_MASK_CONST(0xfffffff)
#define I2C_I2C_TLOW_SEXT_0_WRITE_MASK                  MK_MASK_CONST(0xfffffff)
#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_SHIFT                     MK_SHIFT_CONST(27)
#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_SHIFT)
#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_RANGE                     27:27
#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_MSB                       MK_SHIFT_CONST(27)
#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_LSB                       MK_SHIFT_CONST(27)
#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_WOFFSET                   0x0
#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_SHIFT                  MK_SHIFT_CONST(26)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_SHIFT)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_RANGE                  26:26
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_MSB                    MK_SHIFT_CONST(26)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_LSB                    MK_SHIFT_CONST(26)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_WOFFSET                        0x0
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_SHIFT                  MK_SHIFT_CONST(25)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_SHIFT)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_RANGE                  25:25
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_MSB                    MK_SHIFT_CONST(25)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_LSB                    MK_SHIFT_CONST(25)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_WOFFSET                        0x0
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_SHIFT                    MK_SHIFT_CONST(24)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_SHIFT)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_RANGE                    24:24
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_MSB                      MK_SHIFT_CONST(24)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_LSB                      MK_SHIFT_CONST(24)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_WOFFSET                  0x0
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_SHIFT                     MK_SHIFT_CONST(16)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_FIELD                     MK_FIELD_CONST(0xff, I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_SHIFT)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_RANGE                     23:16
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_MSB                       MK_SHIFT_CONST(23)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_LSB                       MK_SHIFT_CONST(16)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_WOFFSET                   0x0
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_SHIFT                     MK_SHIFT_CONST(8)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_FIELD                     MK_FIELD_CONST(0xff, I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_SHIFT)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_RANGE                     15:8
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_MSB                       MK_SHIFT_CONST(15)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_LSB                       MK_SHIFT_CONST(8)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_WOFFSET                   0x0
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_DEFAULT_MASK                      MK_MASK_CONST(0xff)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_SHIFT                       MK_SHIFT_CONST(0)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_FIELD                       MK_FIELD_CONST(0xff, I2C_I2C_TLOW_SEXT_0_TIMEOUT_SHIFT)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_RANGE                       7:0
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_MSB                 MK_SHIFT_CONST(7)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_LSB                 MK_SHIFT_CONST(0)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_WOFFSET                     0x0
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

// Reserved address 0x38

// Register I2C_I2C_SL_DELAY_COUNT_0
#define I2C_I2C_SL_DELAY_COUNT_0                        MK_ADDR_CONST(0x3c)
#define I2C_I2C_SL_DELAY_COUNT_0_SECURE                         0x0
#define I2C_I2C_SL_DELAY_COUNT_0_DUAL                   0x0
#define I2C_I2C_SL_DELAY_COUNT_0_SCR                    0
#define I2C_I2C_SL_DELAY_COUNT_0_SCRREG                         0
#define I2C_I2C_SL_DELAY_COUNT_0_WORD_COUNT                     0x1
#define I2C_I2C_SL_DELAY_COUNT_0_RESET_VAL                      MK_MASK_CONST(0x1e)
#define I2C_I2C_SL_DELAY_COUNT_0_RESET_MASK                     MK_MASK_CONST(0xffff)
#define I2C_I2C_SL_DELAY_COUNT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define I2C_I2C_SL_DELAY_COUNT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_DELAY_COUNT_0_READ_MASK                      MK_MASK_CONST(0xffff)
#define I2C_I2C_SL_DELAY_COUNT_0_WRITE_MASK                     MK_MASK_CONST(0xffff)
#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SHIFT                   MK_SHIFT_CONST(0)
#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_FIELD                   MK_FIELD_CONST(0xffff, I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SHIFT)
#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_RANGE                   15:0
#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_MSB                     MK_SHIFT_CONST(15)
#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_LSB                     MK_SHIFT_CONST(0)
#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_WOFFSET                 0x0
#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_DEFAULT                 MK_MASK_CONST(0x1e)
#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

// Register I2C_I2C_SL_INT_MASK_0
#define I2C_I2C_SL_INT_MASK_0                   MK_ADDR_CONST(0x40)
#define I2C_I2C_SL_INT_MASK_0_SECURE                    0x0
#define I2C_I2C_SL_INT_MASK_0_DUAL                      0x0
#define I2C_I2C_SL_INT_MASK_0_SCR                       0
#define I2C_I2C_SL_INT_MASK_0_SCRREG                    0
#define I2C_I2C_SL_INT_MASK_0_WORD_COUNT                        0x1
#define I2C_I2C_SL_INT_MASK_0_RESET_VAL                         MK_MASK_CONST(0xfd)
#define I2C_I2C_SL_INT_MASK_0_RESET_MASK                        MK_MASK_CONST(0xfd)
#define I2C_I2C_SL_INT_MASK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_READ_MASK                         MK_MASK_CONST(0xfd)
#define I2C_I2C_SL_INT_MASK_0_WRITE_MASK                        MK_MASK_CONST(0xfd)
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_SHIFT                 MK_SHIFT_CONST(7)
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_SHIFT)
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_RANGE                 7:7
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_MSB                   MK_SHIFT_CONST(7)
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_LSB                   MK_SHIFT_CONST(7)
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_WOFFSET                       0x0
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_DEFAULT                       MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_DISABLE                       MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_ENABLE                        MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_SHIFT                   MK_SHIFT_CONST(6)
#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_REPROG_SL_SHIFT)
#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_RANGE                   6:6
#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_MSB                     MK_SHIFT_CONST(6)
#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_LSB                     MK_SHIFT_CONST(6)
#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_WOFFSET                 0x0
#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_DEFAULT                 MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_DISABLE                 MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_ENABLE                  MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_MASK_0_RST_SL_SHIFT                      MK_SHIFT_CONST(5)
#define I2C_I2C_SL_INT_MASK_0_RST_SL_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_RST_SL_SHIFT)
#define I2C_I2C_SL_INT_MASK_0_RST_SL_RANGE                      5:5
#define I2C_I2C_SL_INT_MASK_0_RST_SL_MSB                        MK_SHIFT_CONST(5)
#define I2C_I2C_SL_INT_MASK_0_RST_SL_LSB                        MK_SHIFT_CONST(5)
#define I2C_I2C_SL_INT_MASK_0_RST_SL_WOFFSET                    0x0
#define I2C_I2C_SL_INT_MASK_0_RST_SL_DEFAULT                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_RST_SL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_RST_SL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_RST_SL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_RST_SL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_RST_SL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_RST_SL_DISABLE                    MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_MASK_0_RST_SL_ENABLE                     MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_MASK_0_END_TRANS_SHIFT                   MK_SHIFT_CONST(4)
#define I2C_I2C_SL_INT_MASK_0_END_TRANS_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_END_TRANS_SHIFT)
#define I2C_I2C_SL_INT_MASK_0_END_TRANS_RANGE                   4:4
#define I2C_I2C_SL_INT_MASK_0_END_TRANS_MSB                     MK_SHIFT_CONST(4)
#define I2C_I2C_SL_INT_MASK_0_END_TRANS_LSB                     MK_SHIFT_CONST(4)
#define I2C_I2C_SL_INT_MASK_0_END_TRANS_WOFFSET                 0x0
#define I2C_I2C_SL_INT_MASK_0_END_TRANS_DEFAULT                 MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_END_TRANS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_END_TRANS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_END_TRANS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_END_TRANS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_END_TRANS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_END_TRANS_DISABLE                 MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_MASK_0_END_TRANS_ENABLE                  MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_SHIFT                      MK_SHIFT_CONST(3)
#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_SL_IRQ_SHIFT)
#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_RANGE                      3:3
#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_MSB                        MK_SHIFT_CONST(3)
#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_LSB                        MK_SHIFT_CONST(3)
#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_WOFFSET                    0x0
#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_DEFAULT                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_DISABLE                    MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_ENABLE                     MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_MASK_0_RCVD_SHIFT                        MK_SHIFT_CONST(2)
#define I2C_I2C_SL_INT_MASK_0_RCVD_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_RCVD_SHIFT)
#define I2C_I2C_SL_INT_MASK_0_RCVD_RANGE                        2:2
#define I2C_I2C_SL_INT_MASK_0_RCVD_MSB                  MK_SHIFT_CONST(2)
#define I2C_I2C_SL_INT_MASK_0_RCVD_LSB                  MK_SHIFT_CONST(2)
#define I2C_I2C_SL_INT_MASK_0_RCVD_WOFFSET                      0x0
#define I2C_I2C_SL_INT_MASK_0_RCVD_DEFAULT                      MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_RCVD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_RCVD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_RCVD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_RCVD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_RCVD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_RCVD_DISABLE                      MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_MASK_0_RCVD_ENABLE                       MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_MASK_0_ZA_SHIFT                  MK_SHIFT_CONST(0)
#define I2C_I2C_SL_INT_MASK_0_ZA_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_ZA_SHIFT)
#define I2C_I2C_SL_INT_MASK_0_ZA_RANGE                  0:0
#define I2C_I2C_SL_INT_MASK_0_ZA_MSB                    MK_SHIFT_CONST(0)
#define I2C_I2C_SL_INT_MASK_0_ZA_LSB                    MK_SHIFT_CONST(0)
#define I2C_I2C_SL_INT_MASK_0_ZA_WOFFSET                        0x0
#define I2C_I2C_SL_INT_MASK_0_ZA_DEFAULT                        MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_ZA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_ZA_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_ZA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_ZA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_MASK_0_ZA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_MASK_0_ZA_DISABLE                        MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_MASK_0_ZA_ENABLE                 MK_ENUM_CONST(1)

// Register I2C_I2C_SL_INT_SOURCE_0
#define I2C_I2C_SL_INT_SOURCE_0                 MK_ADDR_CONST(0x44)
#define I2C_I2C_SL_INT_SOURCE_0_SECURE                  0x0
#define I2C_I2C_SL_INT_SOURCE_0_DUAL                    0x0
#define I2C_I2C_SL_INT_SOURCE_0_SCR                     0
#define I2C_I2C_SL_INT_SOURCE_0_SCRREG                  0
#define I2C_I2C_SL_INT_SOURCE_0_WORD_COUNT                      0x1
#define I2C_I2C_SL_INT_SOURCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_RESET_MASK                      MK_MASK_CONST(0xfd)
#define I2C_I2C_SL_INT_SOURCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_READ_MASK                       MK_MASK_CONST(0xfd)
#define I2C_I2C_SL_INT_SOURCE_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_SHIFT                       MK_SHIFT_CONST(7)
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_SHIFT)
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_RANGE                       7:7
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_MSB                 MK_SHIFT_CONST(7)
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_LSB                 MK_SHIFT_CONST(7)
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_WOFFSET                     0x0
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_UNSET                       MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_SET                 MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_SHIFT                 MK_SHIFT_CONST(6)
#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_SHIFT)
#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_RANGE                 6:6
#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_MSB                   MK_SHIFT_CONST(6)
#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_LSB                   MK_SHIFT_CONST(6)
#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_WOFFSET                       0x0
#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_UNSET                 MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_SET                   MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_SHIFT                    MK_SHIFT_CONST(5)
#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_RST_SL_SHIFT)
#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_RANGE                    5:5
#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_MSB                      MK_SHIFT_CONST(5)
#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_LSB                      MK_SHIFT_CONST(5)
#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_WOFFSET                  0x0
#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_UNSET                    MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_SET                      MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_SHIFT                 MK_SHIFT_CONST(4)
#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_END_TRANS_SHIFT)
#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_RANGE                 4:4
#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_MSB                   MK_SHIFT_CONST(4)
#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_LSB                   MK_SHIFT_CONST(4)
#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_WOFFSET                       0x0
#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_UNSET                 MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_SET                   MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_SHIFT                    MK_SHIFT_CONST(3)
#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_SHIFT)
#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_RANGE                    3:3
#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_MSB                      MK_SHIFT_CONST(3)
#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_LSB                      MK_SHIFT_CONST(3)
#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_WOFFSET                  0x0
#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_UNSET                    MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_SET                      MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_SOURCE_0_RCVD_SHIFT                      MK_SHIFT_CONST(2)
#define I2C_I2C_SL_INT_SOURCE_0_RCVD_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_RCVD_SHIFT)
#define I2C_I2C_SL_INT_SOURCE_0_RCVD_RANGE                      2:2
#define I2C_I2C_SL_INT_SOURCE_0_RCVD_MSB                        MK_SHIFT_CONST(2)
#define I2C_I2C_SL_INT_SOURCE_0_RCVD_LSB                        MK_SHIFT_CONST(2)
#define I2C_I2C_SL_INT_SOURCE_0_RCVD_WOFFSET                    0x0
#define I2C_I2C_SL_INT_SOURCE_0_RCVD_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_RCVD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_RCVD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_RCVD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_RCVD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_RCVD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_RCVD_UNSET                      MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SOURCE_0_RCVD_SET                        MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_SOURCE_0_ZA_SHIFT                        MK_SHIFT_CONST(0)
#define I2C_I2C_SL_INT_SOURCE_0_ZA_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_ZA_SHIFT)
#define I2C_I2C_SL_INT_SOURCE_0_ZA_RANGE                        0:0
#define I2C_I2C_SL_INT_SOURCE_0_ZA_MSB                  MK_SHIFT_CONST(0)
#define I2C_I2C_SL_INT_SOURCE_0_ZA_LSB                  MK_SHIFT_CONST(0)
#define I2C_I2C_SL_INT_SOURCE_0_ZA_WOFFSET                      0x0
#define I2C_I2C_SL_INT_SOURCE_0_ZA_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_ZA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_ZA_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_ZA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_ZA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SOURCE_0_ZA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SOURCE_0_ZA_UNSET                        MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SOURCE_0_ZA_SET                  MK_ENUM_CONST(1)

// Register I2C_I2C_SL_INT_SET_0
#define I2C_I2C_SL_INT_SET_0                    MK_ADDR_CONST(0x48)
#define I2C_I2C_SL_INT_SET_0_SECURE                     0x0
#define I2C_I2C_SL_INT_SET_0_DUAL                       0x0
#define I2C_I2C_SL_INT_SET_0_SCR                        0
#define I2C_I2C_SL_INT_SET_0_SCRREG                     0
#define I2C_I2C_SL_INT_SET_0_WORD_COUNT                         0x1
#define I2C_I2C_SL_INT_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_RESET_MASK                         MK_MASK_CONST(0xfd)
#define I2C_I2C_SL_INT_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_READ_MASK                  MK_MASK_CONST(0xfd)
#define I2C_I2C_SL_INT_SET_0_WRITE_MASK                         MK_MASK_CONST(0xfd)
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_SHIFT                  MK_SHIFT_CONST(7)
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_SHIFT)
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_RANGE                  7:7
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_MSB                    MK_SHIFT_CONST(7)
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_LSB                    MK_SHIFT_CONST(7)
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_WOFFSET                        0x0
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_UNSET                  MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_SET                    MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_SET_0_REPROG_SL_SHIFT                    MK_SHIFT_CONST(6)
#define I2C_I2C_SL_INT_SET_0_REPROG_SL_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_REPROG_SL_SHIFT)
#define I2C_I2C_SL_INT_SET_0_REPROG_SL_RANGE                    6:6
#define I2C_I2C_SL_INT_SET_0_REPROG_SL_MSB                      MK_SHIFT_CONST(6)
#define I2C_I2C_SL_INT_SET_0_REPROG_SL_LSB                      MK_SHIFT_CONST(6)
#define I2C_I2C_SL_INT_SET_0_REPROG_SL_WOFFSET                  0x0
#define I2C_I2C_SL_INT_SET_0_REPROG_SL_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_REPROG_SL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_REPROG_SL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_REPROG_SL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_REPROG_SL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_REPROG_SL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_REPROG_SL_UNSET                    MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SET_0_REPROG_SL_SET                      MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_SET_0_RST_SL_SHIFT                       MK_SHIFT_CONST(5)
#define I2C_I2C_SL_INT_SET_0_RST_SL_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_RST_SL_SHIFT)
#define I2C_I2C_SL_INT_SET_0_RST_SL_RANGE                       5:5
#define I2C_I2C_SL_INT_SET_0_RST_SL_MSB                 MK_SHIFT_CONST(5)
#define I2C_I2C_SL_INT_SET_0_RST_SL_LSB                 MK_SHIFT_CONST(5)
#define I2C_I2C_SL_INT_SET_0_RST_SL_WOFFSET                     0x0
#define I2C_I2C_SL_INT_SET_0_RST_SL_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_RST_SL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_RST_SL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_RST_SL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_RST_SL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_RST_SL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_RST_SL_UNSET                       MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SET_0_RST_SL_SET                 MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_SET_0_END_TRANS_SHIFT                    MK_SHIFT_CONST(4)
#define I2C_I2C_SL_INT_SET_0_END_TRANS_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_END_TRANS_SHIFT)
#define I2C_I2C_SL_INT_SET_0_END_TRANS_RANGE                    4:4
#define I2C_I2C_SL_INT_SET_0_END_TRANS_MSB                      MK_SHIFT_CONST(4)
#define I2C_I2C_SL_INT_SET_0_END_TRANS_LSB                      MK_SHIFT_CONST(4)
#define I2C_I2C_SL_INT_SET_0_END_TRANS_WOFFSET                  0x0
#define I2C_I2C_SL_INT_SET_0_END_TRANS_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_END_TRANS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_END_TRANS_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_END_TRANS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_END_TRANS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_END_TRANS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_END_TRANS_UNSET                    MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SET_0_END_TRANS_SET                      MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_SET_0_SL_IRQ_SHIFT                       MK_SHIFT_CONST(3)
#define I2C_I2C_SL_INT_SET_0_SL_IRQ_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_SL_IRQ_SHIFT)
#define I2C_I2C_SL_INT_SET_0_SL_IRQ_RANGE                       3:3
#define I2C_I2C_SL_INT_SET_0_SL_IRQ_MSB                 MK_SHIFT_CONST(3)
#define I2C_I2C_SL_INT_SET_0_SL_IRQ_LSB                 MK_SHIFT_CONST(3)
#define I2C_I2C_SL_INT_SET_0_SL_IRQ_WOFFSET                     0x0
#define I2C_I2C_SL_INT_SET_0_SL_IRQ_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_SL_IRQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_SL_IRQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_SL_IRQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_SL_IRQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_SL_IRQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_SL_IRQ_UNSET                       MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SET_0_SL_IRQ_SET                 MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_SET_0_RCVD_SHIFT                 MK_SHIFT_CONST(2)
#define I2C_I2C_SL_INT_SET_0_RCVD_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_RCVD_SHIFT)
#define I2C_I2C_SL_INT_SET_0_RCVD_RANGE                 2:2
#define I2C_I2C_SL_INT_SET_0_RCVD_MSB                   MK_SHIFT_CONST(2)
#define I2C_I2C_SL_INT_SET_0_RCVD_LSB                   MK_SHIFT_CONST(2)
#define I2C_I2C_SL_INT_SET_0_RCVD_WOFFSET                       0x0
#define I2C_I2C_SL_INT_SET_0_RCVD_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_RCVD_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_RCVD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_RCVD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_RCVD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_RCVD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_RCVD_UNSET                 MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SET_0_RCVD_SET                   MK_ENUM_CONST(1)

#define I2C_I2C_SL_INT_SET_0_ZA_SHIFT                   MK_SHIFT_CONST(0)
#define I2C_I2C_SL_INT_SET_0_ZA_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_ZA_SHIFT)
#define I2C_I2C_SL_INT_SET_0_ZA_RANGE                   0:0
#define I2C_I2C_SL_INT_SET_0_ZA_MSB                     MK_SHIFT_CONST(0)
#define I2C_I2C_SL_INT_SET_0_ZA_LSB                     MK_SHIFT_CONST(0)
#define I2C_I2C_SL_INT_SET_0_ZA_WOFFSET                 0x0
#define I2C_I2C_SL_INT_SET_0_ZA_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_ZA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_ZA_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_ZA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_ZA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_SL_INT_SET_0_ZA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_SL_INT_SET_0_ZA_UNSET                   MK_ENUM_CONST(0)
#define I2C_I2C_SL_INT_SET_0_ZA_SET                     MK_ENUM_CONST(1)

// Reserved address 0x4c

// Packet I2C_IO_PACKET_HEADER_0
#define I2C_IO_PACKET_HEADER_0_SIZE 32

#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_SHIFT                        MK_SHIFT_CONST(30)
#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_FIELD                        MK_FIELD_CONST(0x3, I2C_IO_PACKET_HEADER_0_RESERVED0_3_SHIFT)
#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(30)
#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_ROW                  0

#define I2C_IO_PACKET_HEADER_0_HDRSZ_SHIFT                      MK_SHIFT_CONST(28)
#define I2C_IO_PACKET_HEADER_0_HDRSZ_FIELD                      MK_FIELD_CONST(0x3, I2C_IO_PACKET_HEADER_0_HDRSZ_SHIFT)
#define I2C_IO_PACKET_HEADER_0_HDRSZ_RANGE                      MK_SHIFT_CONST(29):MK_SHIFT_CONST(28)
#define I2C_IO_PACKET_HEADER_0_HDRSZ_ROW                        0
#define I2C_IO_PACKET_HEADER_0_HDRSZ_ONE                        MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_HDRSZ_TWO                        MK_ENUM_CONST(1)
#define I2C_IO_PACKET_HEADER_0_HDRSZ_THREE                      MK_ENUM_CONST(2)
#define I2C_IO_PACKET_HEADER_0_HDRSZ_FOUR                       MK_ENUM_CONST(3)

#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_SHIFT                        MK_SHIFT_CONST(26)
#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_FIELD                        MK_FIELD_CONST(0x3, I2C_IO_PACKET_HEADER_0_RESERVED0_2_SHIFT)
#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_RANGE                        MK_SHIFT_CONST(27):MK_SHIFT_CONST(26)
#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_ROW                  0

#define I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_SHIFT                      MK_SHIFT_CONST(25)
#define I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_FIELD                      MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_SHIFT)
#define I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_RANGE                      MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_ROW                        0
#define I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_EOT                        MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_EACH_PACKET                        MK_ENUM_CONST(1)

#define I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_SHIFT                    MK_SHIFT_CONST(24)
#define I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_SHIFT)
#define I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_RANGE                    MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_ROW                      0
#define I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define I2C_IO_PACKET_HEADER_0_PKTID_SHIFT                      MK_SHIFT_CONST(16)
#define I2C_IO_PACKET_HEADER_0_PKTID_FIELD                      MK_FIELD_CONST(0xff, I2C_IO_PACKET_HEADER_0_PKTID_SHIFT)
#define I2C_IO_PACKET_HEADER_0_PKTID_RANGE                      MK_SHIFT_CONST(23):MK_SHIFT_CONST(16)
#define I2C_IO_PACKET_HEADER_0_PKTID_ROW                        0

#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_SHIFT                      MK_SHIFT_CONST(12)
#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_FIELD                      MK_FIELD_CONST(0xf, I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_SHIFT)
#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_RANGE                      MK_SHIFT_CONST(15):MK_SHIFT_CONST(12)
#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_ROW                        0
#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C1                       MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C2                       MK_ENUM_CONST(1)
#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C3                       MK_ENUM_CONST(2)
#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_DVC_I2C                    MK_ENUM_CONST(3)

#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_SHIFT                        MK_SHIFT_CONST(8)
#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_FIELD                        MK_FIELD_CONST(0xf, I2C_IO_PACKET_HEADER_0_RESERVED0_1_SHIFT)
#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_RANGE                        MK_SHIFT_CONST(11):MK_SHIFT_CONST(8)
#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_ROW                  0

#define I2C_IO_PACKET_HEADER_0_PROTOCOL_SHIFT                   MK_SHIFT_CONST(4)
#define I2C_IO_PACKET_HEADER_0_PROTOCOL_FIELD                   MK_FIELD_CONST(0xf, I2C_IO_PACKET_HEADER_0_PROTOCOL_SHIFT)
#define I2C_IO_PACKET_HEADER_0_PROTOCOL_RANGE                   MK_SHIFT_CONST(7):MK_SHIFT_CONST(4)
#define I2C_IO_PACKET_HEADER_0_PROTOCOL_ROW                     0
#define I2C_IO_PACKET_HEADER_0_PROTOCOL_RESERVED                        MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_PROTOCOL_I2C                     MK_ENUM_CONST(1)

#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_SHIFT                        MK_SHIFT_CONST(3)
#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_FIELD                        MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_RESERVED0_0_SHIFT)
#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_RANGE                        MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_ROW                  0

#define I2C_IO_PACKET_HEADER_0_PKTTYPE_SHIFT                    MK_SHIFT_CONST(0)
#define I2C_IO_PACKET_HEADER_0_PKTTYPE_FIELD                    MK_FIELD_CONST(0x7, I2C_IO_PACKET_HEADER_0_PKTTYPE_SHIFT)
#define I2C_IO_PACKET_HEADER_0_PKTTYPE_RANGE                    MK_SHIFT_CONST(2):MK_SHIFT_CONST(0)
#define I2C_IO_PACKET_HEADER_0_PKTTYPE_ROW                      0

#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_SHIFT                        MK_SHIFT_CONST(16)
#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_FIELD                        MK_FIELD_CONST(0xffff, I2C_IO_PACKET_HEADER_0_RESERVED1_0_SHIFT)
#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(16)
#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_ROW                  1

#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_SHIFT                        MK_SHIFT_CONST(0)
#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_FIELD                        MK_FIELD_CONST(0xffff, I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_SHIFT)
#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_RANGE                        MK_SHIFT_CONST(15):MK_SHIFT_CONST(0)
#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_ROW                  1

#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_SHIFT                        MK_SHIFT_CONST(23)
#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_FIELD                        MK_FIELD_CONST(0x1ff, I2C_IO_PACKET_HEADER_0_RESERVED2_0_SHIFT)
#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(23)
#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_ROW                  2

#define I2C_IO_PACKET_HEADER_0_HS_MODE_SHIFT                    MK_SHIFT_CONST(22)
#define I2C_IO_PACKET_HEADER_0_HS_MODE_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_HS_MODE_SHIFT)
#define I2C_IO_PACKET_HEADER_0_HS_MODE_RANGE                    MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define I2C_IO_PACKET_HEADER_0_HS_MODE_ROW                      2
#define I2C_IO_PACKET_HEADER_0_HS_MODE_DISABLE                  MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_HS_MODE_ENABLE                   MK_ENUM_CONST(1)

#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_SHIFT                    MK_SHIFT_CONST(21)
#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_SHIFT)
#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_RANGE                    MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_ROW                      2
#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_DISABLE                  MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_ENABLE                   MK_ENUM_CONST(1)

#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_SHIFT                    MK_SHIFT_CONST(20)
#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_SHIFT)
#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_RANGE                    MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_ROW                      2
#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_DISABLE                  MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_ENABLE                   MK_ENUM_CONST(1)

#define I2C_IO_PACKET_HEADER_0_READ_SHIFT                       MK_SHIFT_CONST(19)
#define I2C_IO_PACKET_HEADER_0_READ_FIELD                       MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_READ_SHIFT)
#define I2C_IO_PACKET_HEADER_0_READ_RANGE                       MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define I2C_IO_PACKET_HEADER_0_READ_ROW                 2
#define I2C_IO_PACKET_HEADER_0_READ_WRITE                       MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_READ_READ                        MK_ENUM_CONST(1)

#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_SHIFT                  MK_SHIFT_CONST(18)
#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_FIELD                  MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_ADDR_MODE_SHIFT)
#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_RANGE                  MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_ROW                    2
#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_SEVEN_BIT                      MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_TEN_BIT                        MK_ENUM_CONST(1)

#define I2C_IO_PACKET_HEADER_0_IE_SHIFT                 MK_SHIFT_CONST(17)
#define I2C_IO_PACKET_HEADER_0_IE_FIELD                 MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_IE_SHIFT)
#define I2C_IO_PACKET_HEADER_0_IE_RANGE                 MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define I2C_IO_PACKET_HEADER_0_IE_ROW                   2
#define I2C_IO_PACKET_HEADER_0_IE_DISABLE                       MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_IE_ENABLE                        MK_ENUM_CONST(1)

#define I2C_IO_PACKET_HEADER_0_REPEAT_START_SHIFT                       MK_SHIFT_CONST(16)
#define I2C_IO_PACKET_HEADER_0_REPEAT_START_FIELD                       MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_REPEAT_START_SHIFT)
#define I2C_IO_PACKET_HEADER_0_REPEAT_START_RANGE                       MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
#define I2C_IO_PACKET_HEADER_0_REPEAT_START_ROW                 2
#define I2C_IO_PACKET_HEADER_0_REPEAT_START_STOP                        MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_REPEAT_START_REPEAT_START                        MK_ENUM_CONST(1)

#define I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_SHIFT                      MK_SHIFT_CONST(15)
#define I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_FIELD                      MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_SHIFT)
#define I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_RANGE                      MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_ROW                        2
#define I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_DISABLE                    MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_ENABLE                     MK_ENUM_CONST(1)

#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_SHIFT                     MK_SHIFT_CONST(12)
#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_FIELD                     MK_FIELD_CONST(0x7, I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_SHIFT)
#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_RANGE                     MK_SHIFT_CONST(14):MK_SHIFT_CONST(12)
#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_ROW                       2

#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_SHIFT                        MK_SHIFT_CONST(10)
#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_FIELD                        MK_FIELD_CONST(0x3, I2C_IO_PACKET_HEADER_0_RESERVED2_2_SHIFT)
#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_RANGE                        MK_SHIFT_CONST(11):MK_SHIFT_CONST(10)
#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_ROW                  2

#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_SHIFT                 MK_SHIFT_CONST(0)
#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_FIELD                 MK_FIELD_CONST(0x3ff, I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_SHIFT)
#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_RANGE                 MK_SHIFT_CONST(9):MK_SHIFT_CONST(0)
#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_ROW                   2

// Packet I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SIZE 32

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_3_SHIFT                 MK_SHIFT_CONST(30)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_3_FIELD                 MK_FIELD_CONST(0x3, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_3_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_3_RANGE                 MK_SHIFT_CONST(31):MK_SHIFT_CONST(30)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_3_ROW                   0

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_SHIFT                       MK_SHIFT_CONST(28)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_FIELD                       MK_FIELD_CONST(0x3, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_RANGE                       MK_SHIFT_CONST(29):MK_SHIFT_CONST(28)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_ROW                 0
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_ONE                 MK_ENUM_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_TWO                 MK_ENUM_CONST(1)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_THREE                       MK_ENUM_CONST(2)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_FOUR                        MK_ENUM_CONST(3)

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_2_SHIFT                 MK_SHIFT_CONST(24)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_2_FIELD                 MK_FIELD_CONST(0xf, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_2_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_2_RANGE                 MK_SHIFT_CONST(27):MK_SHIFT_CONST(24)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_2_ROW                   0

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTID_SHIFT                       MK_SHIFT_CONST(16)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTID_FIELD                       MK_FIELD_CONST(0xff, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTID_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTID_RANGE                       MK_SHIFT_CONST(23):MK_SHIFT_CONST(16)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTID_ROW                 0

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_SHIFT                       MK_SHIFT_CONST(12)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_FIELD                       MK_FIELD_CONST(0xf, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_RANGE                       MK_SHIFT_CONST(15):MK_SHIFT_CONST(12)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_ROW                 0
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_I2C1                        MK_ENUM_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_I2C2                        MK_ENUM_CONST(1)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_I2C3                        MK_ENUM_CONST(2)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_DVC_I2C                     MK_ENUM_CONST(3)

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_1_SHIFT                 MK_SHIFT_CONST(8)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_1_FIELD                 MK_FIELD_CONST(0xf, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_1_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_1_RANGE                 MK_SHIFT_CONST(11):MK_SHIFT_CONST(8)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_1_ROW                   0

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_SHIFT                    MK_SHIFT_CONST(4)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_FIELD                    MK_FIELD_CONST(0xf, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_RANGE                    MK_SHIFT_CONST(7):MK_SHIFT_CONST(4)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_ROW                      0
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_RESERVED                 MK_ENUM_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_I2C                      MK_ENUM_CONST(1)

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_0_SHIFT                 MK_SHIFT_CONST(3)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_0_FIELD                 MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_0_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_0_RANGE                 MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_0_ROW                   0

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTTYPE_SHIFT                     MK_SHIFT_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTTYPE_FIELD                     MK_FIELD_CONST(0x7, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTTYPE_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTTYPE_RANGE                     MK_SHIFT_CONST(2):MK_SHIFT_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTTYPE_ROW                       0

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED1_0_SHIFT                 MK_SHIFT_CONST(16)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED1_0_FIELD                 MK_FIELD_CONST(0xffff, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED1_0_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED1_0_RANGE                 MK_SHIFT_CONST(31):MK_SHIFT_CONST(16)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED1_0_ROW                   1

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PAYLOADSIZE_SHIFT                 MK_SHIFT_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PAYLOADSIZE_FIELD                 MK_FIELD_CONST(0xffff, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PAYLOADSIZE_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PAYLOADSIZE_RANGE                 MK_SHIFT_CONST(15):MK_SHIFT_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PAYLOADSIZE_ROW                   1

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_0_SHIFT                 MK_SHIFT_CONST(27)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_0_FIELD                 MK_FIELD_CONST(0x1f, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_0_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_0_RANGE                 MK_SHIFT_CONST(31):MK_SHIFT_CONST(27)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_0_ROW                   2

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_SHIFT                       MK_SHIFT_CONST(26)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_FIELD                       MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_RANGE                       MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_ROW                 2
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_DISABLE                     MK_ENUM_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_ENABLE                      MK_ENUM_CONST(1)

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_SHIFT                       MK_SHIFT_CONST(25)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_FIELD                       MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_RANGE                       MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_ROW                 2
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_DISABLE                     MK_ENUM_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_ENABLE                      MK_ENUM_CONST(1)

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_SHIFT                     MK_SHIFT_CONST(24)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_FIELD                     MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_RANGE                     MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_ROW                       2
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_1_SHIFT                 MK_SHIFT_CONST(23)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_1_FIELD                 MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_1_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_1_RANGE                 MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_1_ROW                   2

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_SHIFT                     MK_SHIFT_CONST(22)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_FIELD                     MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_RANGE                     MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_ROW                       2
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_DISABLE                   MK_ENUM_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_ENABLE                    MK_ENUM_CONST(1)

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_SHIFT                 MK_SHIFT_CONST(20)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_FIELD                 MK_FIELD_CONST(0x3, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_RANGE                 MK_SHIFT_CONST(21):MK_SHIFT_CONST(20)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_ROW                   2
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_DISABLE                       MK_ENUM_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_ENABLE                        MK_ENUM_CONST(1)

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_SHIFT                  MK_SHIFT_CONST(19)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_FIELD                  MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_RANGE                  MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_ROW                    2
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_WRITE                  MK_ENUM_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_READ                   MK_ENUM_CONST(1)

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_SHIFT                   MK_SHIFT_CONST(18)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_FIELD                   MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_RANGE                   MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_ROW                     2
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_SEVEN_BIT                       MK_ENUM_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_TEN_BIT                 MK_ENUM_CONST(1)

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_IE_SHIFT                  MK_SHIFT_CONST(17)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_IE_FIELD                  MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_IE_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_IE_RANGE                  MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_IE_ROW                    2

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_3_SHIFT                 MK_SHIFT_CONST(11)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_3_FIELD                 MK_FIELD_CONST(0x3f, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_3_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_3_RANGE                 MK_SHIFT_CONST(16):MK_SHIFT_CONST(11)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_3_ROW                   2

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_SHIFT                 MK_SHIFT_CONST(10)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_FIELD                 MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_RANGE                 MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_ROW                   2
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_DISABLE                       MK_ENUM_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_ENABLE                        MK_ENUM_CONST(1)

#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_SHIFT                  MK_SHIFT_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_FIELD                  MK_FIELD_CONST(0x3ff, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_SHIFT)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_RANGE                  MK_SHIFT_CONST(9):MK_SHIFT_CONST(0)
#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_ROW                    2

// Packet I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_SIZE 32

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_3_SHIFT                  MK_SHIFT_CONST(23)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_3_FIELD                  MK_FIELD_CONST(0x1ff, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_3_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_3_RANGE                  MK_SHIFT_CONST(31):MK_SHIFT_CONST(23)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_3_ROW                    0

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HS_MODE_SHIFT                      MK_SHIFT_CONST(22)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HS_MODE_FIELD                      MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HS_MODE_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HS_MODE_RANGE                      MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HS_MODE_ROW                        0

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_2_SHIFT                  MK_SHIFT_CONST(19)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_2_FIELD                  MK_FIELD_CONST(0x7, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_2_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_2_RANGE                  MK_SHIFT_CONST(21):MK_SHIFT_CONST(19)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_2_ROW                    0

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ADDR_MODE_SHIFT                    MK_SHIFT_CONST(18)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ADDR_MODE_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ADDR_MODE_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ADDR_MODE_RANGE                    MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ADDR_MODE_ROW                      0

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_1_SHIFT                  MK_SHIFT_CONST(10)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_1_FIELD                  MK_FIELD_CONST(0xff, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_1_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_1_RANGE                  MK_SHIFT_CONST(17):MK_SHIFT_CONST(10)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_1_ROW                    0

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_SLAVE_ADDR_SHIFT                   MK_SHIFT_CONST(0)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_SLAVE_ADDR_FIELD                   MK_FIELD_CONST(0x3ff, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_SLAVE_ADDR_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_SLAVE_ADDR_RANGE                   MK_SHIFT_CONST(9):MK_SHIFT_CONST(0)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_SLAVE_ADDR_ROW                     0

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_0_SHIFT                  MK_SHIFT_CONST(29)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_0_FIELD                  MK_FIELD_CONST(0x7, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_0_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_0_RANGE                  MK_SHIFT_CONST(31):MK_SHIFT_CONST(29)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_0_ROW                    1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ACK_WITHHELD_SHIFT                 MK_SHIFT_CONST(28)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ACK_WITHHELD_FIELD                 MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ACK_WITHHELD_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ACK_WITHHELD_RANGE                 MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ACK_WITHHELD_ROW                   1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_XFER_ERR_REASON_SHIFT                      MK_SHIFT_CONST(27)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_XFER_ERR_REASON_FIELD                      MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_XFER_ERR_REASON_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_XFER_ERR_REASON_RANGE                      MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_XFER_ERR_REASON_ROW                        1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_PKT_XFER_ERR_SHIFT                 MK_SHIFT_CONST(26)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_PKT_XFER_ERR_FIELD                 MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_PKT_XFER_ERR_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_PKT_XFER_ERR_RANGE                 MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_PKT_XFER_ERR_ROW                   1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TFIFO_OVF_SHIFT                    MK_SHIFT_CONST(25)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TFIFO_OVF_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TFIFO_OVF_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TFIFO_OVF_RANGE                    MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TFIFO_OVF_ROW                      1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RFIFO_UNF_SHIFT                    MK_SHIFT_CONST(24)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RFIFO_UNF_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RFIFO_UNF_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RFIFO_UNF_RANGE                    MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RFIFO_UNF_ROW                      1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TRANSFER_PKT_ID_SHIFT                      MK_SHIFT_CONST(16)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TRANSFER_PKT_ID_FIELD                      MK_FIELD_CONST(0xff, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TRANSFER_PKT_ID_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TRANSFER_PKT_ID_RANGE                      MK_SHIFT_CONST(23):MK_SHIFT_CONST(16)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TRANSFER_PKT_ID_ROW                        1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_1_SHIFT                  MK_SHIFT_CONST(15)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_1_FIELD                  MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_1_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_1_RANGE                  MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_1_ROW                    1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_ADDR_SHIFT                 MK_SHIFT_CONST(8)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_ADDR_FIELD                 MK_FIELD_CONST(0x7f, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_ADDR_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_ADDR_RANGE                 MK_SHIFT_CONST(14):MK_SHIFT_CONST(8)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_ADDR_ROW                   1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_2_SHIFT                  MK_SHIFT_CONST(7)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_2_FIELD                  MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_2_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_2_RANGE                  MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_2_ROW                    1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_IRQ_SHIFT                  MK_SHIFT_CONST(6)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_IRQ_FIELD                  MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_IRQ_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_IRQ_RANGE                  MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_IRQ_ROW                    1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_REPROG_SL_SHIFT                    MK_SHIFT_CONST(5)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_REPROG_SL_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_REPROG_SL_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_REPROG_SL_RANGE                    MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_REPROG_SL_ROW                      1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RST_SL_SHIFT                       MK_SHIFT_CONST(4)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RST_SL_FIELD                       MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RST_SL_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RST_SL_RANGE                       MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RST_SL_ROW                 1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_3_SHIFT                  MK_SHIFT_CONST(2)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_3_FIELD                  MK_FIELD_CONST(0x3, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_3_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_3_RANGE                  MK_SHIFT_CONST(3):MK_SHIFT_CONST(2)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_3_ROW                    1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RW_SHIFT                   MK_SHIFT_CONST(1)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RW_FIELD                   MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RW_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RW_RANGE                   MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RW_ROW                     1

#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ZA_SHIFT                   MK_SHIFT_CONST(0)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ZA_FIELD                   MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ZA_SHIFT)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ZA_RANGE                   MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ZA_ROW                     1

// Register I2C_I2C_TX_PACKET_FIFO_0
#define I2C_I2C_TX_PACKET_FIFO_0                        MK_ADDR_CONST(0x50)
#define I2C_I2C_TX_PACKET_FIFO_0_SECURE                         0x0
#define I2C_I2C_TX_PACKET_FIFO_0_DUAL                   0x0
#define I2C_I2C_TX_PACKET_FIFO_0_SCR                    0
#define I2C_I2C_TX_PACKET_FIFO_0_SCRREG                         0
#define I2C_I2C_TX_PACKET_FIFO_0_WORD_COUNT                     0x1
#define I2C_I2C_TX_PACKET_FIFO_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define I2C_I2C_TX_PACKET_FIFO_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
#define I2C_I2C_TX_PACKET_FIFO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define I2C_I2C_TX_PACKET_FIFO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_TX_PACKET_FIFO_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
#define I2C_I2C_TX_PACKET_FIFO_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SHIFT                        MK_SHIFT_CONST(0)
#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_FIELD                        MK_FIELD_CONST(0xffffffff, I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SHIFT)
#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_RANGE                        31:0
#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_MSB                  MK_SHIFT_CONST(31)
#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_LSB                  MK_SHIFT_CONST(0)
#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_WOFFSET                      0x0
#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

// Register I2C_I2C_RX_FIFO_0
#define I2C_I2C_RX_FIFO_0                       MK_ADDR_CONST(0x54)
#define I2C_I2C_RX_FIFO_0_SECURE                        0x0
#define I2C_I2C_RX_FIFO_0_DUAL                  0x0
#define I2C_I2C_RX_FIFO_0_SCR                   0
#define I2C_I2C_RX_FIFO_0_SCRREG                        0
#define I2C_I2C_RX_FIFO_0_WORD_COUNT                    0x1
#define I2C_I2C_RX_FIFO_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define I2C_I2C_RX_FIFO_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
#define I2C_I2C_RX_FIFO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define I2C_I2C_RX_FIFO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_RX_FIFO_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
#define I2C_I2C_RX_FIFO_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_RX_FIFO_0_RD_DATA_SHIFT                 MK_SHIFT_CONST(0)
#define I2C_I2C_RX_FIFO_0_RD_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, I2C_I2C_RX_FIFO_0_RD_DATA_SHIFT)
#define I2C_I2C_RX_FIFO_0_RD_DATA_RANGE                 31:0
#define I2C_I2C_RX_FIFO_0_RD_DATA_MSB                   MK_SHIFT_CONST(31)
#define I2C_I2C_RX_FIFO_0_RD_DATA_LSB                   MK_SHIFT_CONST(0)
#define I2C_I2C_RX_FIFO_0_RD_DATA_WOFFSET                       0x0
#define I2C_I2C_RX_FIFO_0_RD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_RX_FIFO_0_RD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define I2C_I2C_RX_FIFO_0_RD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_RX_FIFO_0_RD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_RX_FIFO_0_RD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_RX_FIFO_0_RD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

// Register I2C_PACKET_TRANSFER_STATUS_0
#define I2C_PACKET_TRANSFER_STATUS_0                    MK_ADDR_CONST(0x58)
#define I2C_PACKET_TRANSFER_STATUS_0_SECURE                     0x0
#define I2C_PACKET_TRANSFER_STATUS_0_DUAL                       0x0
#define I2C_PACKET_TRANSFER_STATUS_0_SCR                        0
#define I2C_PACKET_TRANSFER_STATUS_0_SCRREG                     0
#define I2C_PACKET_TRANSFER_STATUS_0_WORD_COUNT                         0x1
#define I2C_PACKET_TRANSFER_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x1ffffff)
#define I2C_PACKET_TRANSFER_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_READ_MASK                  MK_MASK_CONST(0x1ffffff)
#define I2C_PACKET_TRANSFER_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SHIFT                    MK_SHIFT_CONST(24)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_FIELD                    MK_FIELD_CONST(0x1, I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SHIFT)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_RANGE                    24:24
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_MSB                      MK_SHIFT_CONST(24)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_LSB                      MK_SHIFT_CONST(24)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_WOFFSET                  0x0
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_UNSET                    MK_ENUM_CONST(0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SET                      MK_ENUM_CONST(1)

#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SHIFT                      MK_SHIFT_CONST(16)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_FIELD                      MK_FIELD_CONST(0xff, I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SHIFT)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_RANGE                      23:16
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_MSB                        MK_SHIFT_CONST(23)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_LSB                        MK_SHIFT_CONST(16)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_WOFFSET                    0x0
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SHIFT                     MK_SHIFT_CONST(4)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_FIELD                     MK_FIELD_CONST(0xfff, I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SHIFT)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_RANGE                     15:4
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_MSB                       MK_SHIFT_CONST(15)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_LSB                       MK_SHIFT_CONST(4)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_WOFFSET                   0x0
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_DEFAULT_MASK                      MK_MASK_CONST(0xfff)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SHIFT                       MK_SHIFT_CONST(3)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_FIELD                       MK_FIELD_CONST(0x1, I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SHIFT)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_RANGE                       3:3
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_MSB                 MK_SHIFT_CONST(3)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_LSB                 MK_SHIFT_CONST(3)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_WOFFSET                     0x0
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_UNSET                       MK_ENUM_CONST(0)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SET                 MK_ENUM_CONST(1)

#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SHIFT                       MK_SHIFT_CONST(2)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_FIELD                       MK_FIELD_CONST(0x1, I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SHIFT)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_RANGE                       2:2
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_MSB                 MK_SHIFT_CONST(2)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_LSB                 MK_SHIFT_CONST(2)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_WOFFSET                     0x0
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_UNSET                       MK_ENUM_CONST(0)
#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SET                 MK_ENUM_CONST(1)

#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SHIFT                     MK_SHIFT_CONST(1)
#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_FIELD                     MK_FIELD_CONST(0x1, I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SHIFT)
#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_RANGE                     1:1
#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_MSB                       MK_SHIFT_CONST(1)
#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_LSB                       MK_SHIFT_CONST(1)
#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_WOFFSET                   0x0
#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_UNSET                     MK_ENUM_CONST(0)
#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SET                       MK_ENUM_CONST(1)

#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SHIFT                      MK_SHIFT_CONST(0)
#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_FIELD                      MK_FIELD_CONST(0x1, I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SHIFT)
#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_RANGE                      0:0
#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_MSB                        MK_SHIFT_CONST(0)
#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_LSB                        MK_SHIFT_CONST(0)
#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_WOFFSET                    0x0
#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_UNSET                      MK_ENUM_CONST(0)
#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SET                        MK_ENUM_CONST(1)

// Register I2C_INTERRUPT_MASK_REGISTER_0
#define I2C_INTERRUPT_MASK_REGISTER_0                   MK_ADDR_CONST(0x64)
#define I2C_INTERRUPT_MASK_REGISTER_0_SECURE                    0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_DUAL                      0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_SCR                       0
#define I2C_INTERRUPT_MASK_REGISTER_0_SCRREG                    0
#define I2C_INTERRUPT_MASK_REGISTER_0_WORD_COUNT                        0x1
#define I2C_INTERRUPT_MASK_REGISTER_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RESET_MASK                        MK_MASK_CONST(0x1ff30fff)
#define I2C_INTERRUPT_MASK_REGISTER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_READ_MASK                         MK_MASK_CONST(0x1ff30fff)
#define I2C_INTERRUPT_MASK_REGISTER_0_WRITE_MASK                        MK_MASK_CONST(0x1ff30fff)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_SHIFT                     MK_SHIFT_CONST(28)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_RANGE                     28:28
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_MSB                       MK_SHIFT_CONST(28)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_LSB                       MK_SHIFT_CONST(28)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_WOFFSET                   0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_DISABLE                   MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_ENABLE                    MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_SHIFT                    MK_SHIFT_CONST(27)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_RANGE                    27:27
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_MSB                      MK_SHIFT_CONST(27)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_LSB                      MK_SHIFT_CONST(27)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_WOFFSET                  0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_DISABLE                  MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_ENABLE                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_SHIFT                    MK_SHIFT_CONST(26)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_RANGE                    26:26
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_MSB                      MK_SHIFT_CONST(26)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_LSB                      MK_SHIFT_CONST(26)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_WOFFSET                  0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_DISABLE                  MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_ENABLE                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_SHIFT                     MK_SHIFT_CONST(25)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_RANGE                     25:25
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_MSB                       MK_SHIFT_CONST(25)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_LSB                       MK_SHIFT_CONST(25)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_WOFFSET                   0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_DISABLE                   MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_ENABLE                    MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_SHIFT                    MK_SHIFT_CONST(24)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_RANGE                    24:24
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_MSB                      MK_SHIFT_CONST(24)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_LSB                      MK_SHIFT_CONST(24)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_WOFFSET                  0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_DISABLE                  MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_ENABLE                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_SHIFT                 MK_SHIFT_CONST(23)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_RANGE                 23:23
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_MSB                   MK_SHIFT_CONST(23)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_LSB                   MK_SHIFT_CONST(23)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_WOFFSET                       0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_DISABLE                       MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_ENABLE                        MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_SHIFT                     MK_SHIFT_CONST(22)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_RANGE                     22:22
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_MSB                       MK_SHIFT_CONST(22)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_LSB                       MK_SHIFT_CONST(22)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_WOFFSET                   0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_DISABLE                   MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_ENABLE                    MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_SHIFT                    MK_SHIFT_CONST(21)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_RANGE                    21:21
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_MSB                      MK_SHIFT_CONST(21)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_LSB                      MK_SHIFT_CONST(21)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_WOFFSET                  0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_DISABLE                  MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_ENABLE                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_SHIFT                    MK_SHIFT_CONST(20)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_RANGE                    20:20
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_MSB                      MK_SHIFT_CONST(20)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_LSB                      MK_SHIFT_CONST(20)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_WOFFSET                  0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_DISABLE                  MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_ENABLE                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_SHIFT                   MK_SHIFT_CONST(17)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_FIELD                   MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_RANGE                   17:17
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_MSB                     MK_SHIFT_CONST(17)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_LSB                     MK_SHIFT_CONST(17)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_WOFFSET                 0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_DISABLE                 MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_ENABLE                  MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_SHIFT                   MK_SHIFT_CONST(16)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_FIELD                   MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_RANGE                   16:16
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_MSB                     MK_SHIFT_CONST(16)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_LSB                     MK_SHIFT_CONST(16)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_WOFFSET                 0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_DISABLE                 MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_ENABLE                  MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_SHIFT                       MK_SHIFT_CONST(11)
#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_FIELD                       MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_RANGE                       11:11
#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_MSB                 MK_SHIFT_CONST(11)
#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_LSB                 MK_SHIFT_CONST(11)
#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_WOFFSET                     0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_DISABLE                     MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_ENABLE                      MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_SHIFT                        MK_SHIFT_CONST(10)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_FIELD                        MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_RANGE                        10:10
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_MSB                  MK_SHIFT_CONST(10)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_LSB                  MK_SHIFT_CONST(10)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_WOFFSET                      0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_DISABLE                      MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_ENABLE                       MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_SHIFT                        MK_SHIFT_CONST(9)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_FIELD                        MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_RANGE                        9:9
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_MSB                  MK_SHIFT_CONST(9)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_LSB                  MK_SHIFT_CONST(9)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_WOFFSET                      0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_DISABLE                      MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_ENABLE                       MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_SHIFT                      MK_SHIFT_CONST(8)
#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_FIELD                      MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_RANGE                      8:8
#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_MSB                        MK_SHIFT_CONST(8)
#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_LSB                        MK_SHIFT_CONST(8)
#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_WOFFSET                    0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_DISABLE                    MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_ENABLE                     MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_SHIFT                 MK_SHIFT_CONST(7)
#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_RANGE                 7:7
#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_MSB                   MK_SHIFT_CONST(7)
#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_LSB                   MK_SHIFT_CONST(7)
#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_WOFFSET                       0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_DISABLE                       MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_ENABLE                        MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SHIFT                    MK_SHIFT_CONST(6)
#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_RANGE                    6:6
#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_MSB                      MK_SHIFT_CONST(6)
#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_LSB                      MK_SHIFT_CONST(6)
#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_WOFFSET                  0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DISABLE                  MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_ENABLE                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SHIFT                    MK_SHIFT_CONST(5)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_RANGE                    5:5
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_MSB                      MK_SHIFT_CONST(5)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_LSB                      MK_SHIFT_CONST(5)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_WOFFSET                  0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DISABLE                  MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_ENABLE                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SHIFT                    MK_SHIFT_CONST(4)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_RANGE                    4:4
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_MSB                      MK_SHIFT_CONST(4)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_LSB                      MK_SHIFT_CONST(4)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_WOFFSET                  0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DISABLE                  MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_ENABLE                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SHIFT                        MK_SHIFT_CONST(3)
#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_FIELD                        MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_RANGE                        3:3
#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_MSB                  MK_SHIFT_CONST(3)
#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_LSB                  MK_SHIFT_CONST(3)
#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_WOFFSET                      0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DISABLE                      MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_ENABLE                       MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SHIFT                     MK_SHIFT_CONST(2)
#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_RANGE                     2:2
#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_MSB                       MK_SHIFT_CONST(2)
#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_LSB                       MK_SHIFT_CONST(2)
#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_WOFFSET                   0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DISABLE                   MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_ENABLE                    MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SHIFT                       MK_SHIFT_CONST(1)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_FIELD                       MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_RANGE                       1:1
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_MSB                 MK_SHIFT_CONST(1)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_LSB                 MK_SHIFT_CONST(1)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_WOFFSET                     0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DISABLE                     MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_ENABLE                      MK_ENUM_CONST(1)

#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SHIFT                       MK_SHIFT_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_FIELD                       MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SHIFT)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_RANGE                       0:0
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_MSB                 MK_SHIFT_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_LSB                 MK_SHIFT_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_WOFFSET                     0x0
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DISABLE                     MK_ENUM_CONST(0)
#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_ENABLE                      MK_ENUM_CONST(1)

// Register I2C_INTERRUPT_STATUS_REGISTER_0
#define I2C_INTERRUPT_STATUS_REGISTER_0                 MK_ADDR_CONST(0x68)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SECURE                  0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_DUAL                    0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_SCR                     0
#define I2C_INTERRUPT_STATUS_REGISTER_0_SCRREG                  0
#define I2C_INTERRUPT_STATUS_REGISTER_0_WORD_COUNT                      0x1
#define I2C_INTERRUPT_STATUS_REGISTER_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RESET_MASK                      MK_MASK_CONST(0x1ff30fff)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_READ_MASK                       MK_MASK_CONST(0x1ff30fff)
#define I2C_INTERRUPT_STATUS_REGISTER_0_WRITE_MASK                      MK_MASK_CONST(0x1ff00ffc)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_SHIFT                  MK_SHIFT_CONST(28)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_FIELD                  MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_RANGE                  28:28
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_MSB                    MK_SHIFT_CONST(28)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_LSB                    MK_SHIFT_CONST(28)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_WOFFSET                        0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_UNSET                  MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_SET                    MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_SHIFT                 MK_SHIFT_CONST(27)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_RANGE                 27:27
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_MSB                   MK_SHIFT_CONST(27)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_LSB                   MK_SHIFT_CONST(27)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_WOFFSET                       0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_UNSET                 MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_SET                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_SHIFT                 MK_SHIFT_CONST(26)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_RANGE                 26:26
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_MSB                   MK_SHIFT_CONST(26)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_LSB                   MK_SHIFT_CONST(26)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_WOFFSET                       0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_UNSET                 MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_SET                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_SHIFT                  MK_SHIFT_CONST(25)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_FIELD                  MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_RANGE                  25:25
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_MSB                    MK_SHIFT_CONST(25)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_LSB                    MK_SHIFT_CONST(25)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_WOFFSET                        0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_UNSET                  MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_SET                    MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_SHIFT                 MK_SHIFT_CONST(24)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_RANGE                 24:24
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_MSB                   MK_SHIFT_CONST(24)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_LSB                   MK_SHIFT_CONST(24)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_WOFFSET                       0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_UNSET                 MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_SET                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_SHIFT                      MK_SHIFT_CONST(23)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_FIELD                      MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_RANGE                      23:23
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_MSB                        MK_SHIFT_CONST(23)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_LSB                        MK_SHIFT_CONST(23)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_WOFFSET                    0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_UNSET                      MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_SET                        MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SHIFT                  MK_SHIFT_CONST(22)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_FIELD                  MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_RANGE                  22:22
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_MSB                    MK_SHIFT_CONST(22)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_LSB                    MK_SHIFT_CONST(22)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_WOFFSET                        0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_UNSET                  MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SET                    MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_SHIFT                     MK_SHIFT_CONST(21)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_RANGE                     21:21
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_MSB                       MK_SHIFT_CONST(21)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_LSB                       MK_SHIFT_CONST(21)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_WOFFSET                   0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_UNSET                     MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_SET                       MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_SHIFT                     MK_SHIFT_CONST(20)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_RANGE                     20:20
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_MSB                       MK_SHIFT_CONST(20)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_LSB                       MK_SHIFT_CONST(20)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_WOFFSET                   0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_UNSET                     MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_SET                       MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_SHIFT                        MK_SHIFT_CONST(17)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_FIELD                        MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_RANGE                        17:17
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_MSB                  MK_SHIFT_CONST(17)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_LSB                  MK_SHIFT_CONST(17)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_WOFFSET                      0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_UNSET                        MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_SET                  MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_SHIFT                        MK_SHIFT_CONST(16)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_FIELD                        MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_RANGE                        16:16
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_MSB                  MK_SHIFT_CONST(16)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_LSB                  MK_SHIFT_CONST(16)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_WOFFSET                      0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_UNSET                        MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_SET                  MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_SHIFT                    MK_SHIFT_CONST(11)
#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_RANGE                    11:11
#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_MSB                      MK_SHIFT_CONST(11)
#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_LSB                      MK_SHIFT_CONST(11)
#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_WOFFSET                  0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_UNSET                    MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_SET                      MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_SHIFT                 MK_SHIFT_CONST(10)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_RANGE                 10:10
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_MSB                   MK_SHIFT_CONST(10)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_LSB                   MK_SHIFT_CONST(10)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_WOFFSET                       0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_UNSET                 MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_SET                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_SHIFT                 MK_SHIFT_CONST(9)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_RANGE                 9:9
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_MSB                   MK_SHIFT_CONST(9)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_LSB                   MK_SHIFT_CONST(9)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_WOFFSET                       0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_UNSET                 MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_SET                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_SHIFT                   MK_SHIFT_CONST(8)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_FIELD                   MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_RANGE                   8:8
#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_MSB                     MK_SHIFT_CONST(8)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_LSB                     MK_SHIFT_CONST(8)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_WOFFSET                 0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_UNSET                   MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_SET                     MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT                      MK_SHIFT_CONST(7)
#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_FIELD                      MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_RANGE                      7:7
#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_MSB                        MK_SHIFT_CONST(7)
#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_LSB                        MK_SHIFT_CONST(7)
#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_WOFFSET                    0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_UNSET                      MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SET                        MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT                 MK_SHIFT_CONST(6)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_RANGE                 6:6
#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_MSB                   MK_SHIFT_CONST(6)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_LSB                   MK_SHIFT_CONST(6)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_WOFFSET                       0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_UNSET                 MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SET                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SHIFT                 MK_SHIFT_CONST(5)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_RANGE                 5:5
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_MSB                   MK_SHIFT_CONST(5)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_LSB                   MK_SHIFT_CONST(5)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_WOFFSET                       0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_UNSET                 MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SET                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SHIFT                 MK_SHIFT_CONST(4)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_RANGE                 4:4
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_MSB                   MK_SHIFT_CONST(4)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_LSB                   MK_SHIFT_CONST(4)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_WOFFSET                       0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_UNSET                 MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SET                   MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SHIFT                     MK_SHIFT_CONST(3)
#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_RANGE                     3:3
#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_MSB                       MK_SHIFT_CONST(3)
#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_LSB                       MK_SHIFT_CONST(3)
#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_WOFFSET                   0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_UNSET                     MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SET                       MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SHIFT                  MK_SHIFT_CONST(2)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_FIELD                  MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_RANGE                  2:2
#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_MSB                    MK_SHIFT_CONST(2)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_LSB                    MK_SHIFT_CONST(2)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_WOFFSET                        0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_UNSET                  MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SET                    MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SHIFT                    MK_SHIFT_CONST(1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_RANGE                    1:1
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_MSB                      MK_SHIFT_CONST(1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_LSB                      MK_SHIFT_CONST(1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_WOFFSET                  0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_UNSET                    MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SET                      MK_ENUM_CONST(1)

#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SHIFT                    MK_SHIFT_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SHIFT)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_RANGE                    0:0
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_MSB                      MK_SHIFT_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_LSB                      MK_SHIFT_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_WOFFSET                  0x0
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_UNSET                    MK_ENUM_CONST(0)
#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SET                      MK_ENUM_CONST(1)

// Register I2C_I2C_CLK_DIVISOR_REGISTER_0
#define I2C_I2C_CLK_DIVISOR_REGISTER_0                  MK_ADDR_CONST(0x6c)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SECURE                   0x0
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_DUAL                     0x0
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SCR                      0
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SCRREG                   0
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_WORD_COUNT                       0x1
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_RESET_VAL                        MK_MASK_CONST(0x190001)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT                      MK_SHIFT_CONST(16)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_FIELD                      MK_FIELD_CONST(0xffff, I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_RANGE                      31:16
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_MSB                        MK_SHIFT_CONST(31)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_LSB                        MK_SHIFT_CONST(16)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_WOFFSET                    0x0
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_DEFAULT                    MK_MASK_CONST(0x19)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE__PROD_C_SM                 MK_ENUM_CONST(79)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE__PROD_C_FM                 MK_ENUM_CONST(88)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE__PROD_C_FMPLUS                     MK_ENUM_CONST(36)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE__PROD_C_HS                 MK_ENUM_CONST(88)

#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SHIFT                     MK_SHIFT_CONST(0)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_FIELD                     MK_FIELD_CONST(0xffff, I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SHIFT)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_RANGE                     15:0
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_MSB                       MK_SHIFT_CONST(15)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_LSB                       MK_SHIFT_CONST(0)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_WOFFSET                   0x0
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_DEFAULT                   MK_MASK_CONST(0x1)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE__PROD_C_HS                        MK_ENUM_CONST(2)

#define REG_OFFSET_WIDTH        16
#define SLV_HIF_SM_WIDTH        5
#define SLV_HIF_TXFIFO_SM_WIDTH 3

// Register I2C_I2C_INTERRUPT_SOURCE_REGISTER_0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0                     MK_ADDR_CONST(0x70)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SECURE                      0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_DUAL                        0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SCR                         0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SCRREG                      0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_WORD_COUNT                  0x1
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RESET_MASK                  MK_MASK_CONST(0x1ff30fff)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_READ_MASK                   MK_MASK_CONST(0x1ff30fff)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_SHIFT                      MK_SHIFT_CONST(28)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_RANGE                      28:28
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_MSB                        MK_SHIFT_CONST(28)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_LSB                        MK_SHIFT_CONST(28)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_WOFFSET                    0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_UNSET                      MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_SET                        MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_SHIFT                     MK_SHIFT_CONST(27)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_RANGE                     27:27
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_MSB                       MK_SHIFT_CONST(27)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_LSB                       MK_SHIFT_CONST(27)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_WOFFSET                   0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_UNSET                     MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_SET                       MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_SHIFT                     MK_SHIFT_CONST(26)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_RANGE                     26:26
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_MSB                       MK_SHIFT_CONST(26)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_LSB                       MK_SHIFT_CONST(26)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_WOFFSET                   0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_UNSET                     MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_SET                       MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_SHIFT                      MK_SHIFT_CONST(25)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_RANGE                      25:25
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_MSB                        MK_SHIFT_CONST(25)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_LSB                        MK_SHIFT_CONST(25)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_WOFFSET                    0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_UNSET                      MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_SET                        MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_SHIFT                     MK_SHIFT_CONST(24)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_RANGE                     24:24
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_MSB                       MK_SHIFT_CONST(24)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_LSB                       MK_SHIFT_CONST(24)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_WOFFSET                   0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_UNSET                     MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_SET                       MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_SHIFT                  MK_SHIFT_CONST(23)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_RANGE                  23:23
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_MSB                    MK_SHIFT_CONST(23)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_LSB                    MK_SHIFT_CONST(23)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_WOFFSET                        0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_UNSET                  MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_SET                    MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SHIFT                      MK_SHIFT_CONST(22)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_RANGE                      22:22
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_MSB                        MK_SHIFT_CONST(22)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_LSB                        MK_SHIFT_CONST(22)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_WOFFSET                    0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_UNSET                      MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SET                        MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_SHIFT                 MK_SHIFT_CONST(21)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_RANGE                 21:21
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_MSB                   MK_SHIFT_CONST(21)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_LSB                   MK_SHIFT_CONST(21)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_WOFFSET                       0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_UNSET                 MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_SET                   MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_SHIFT                 MK_SHIFT_CONST(20)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_RANGE                 20:20
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_MSB                   MK_SHIFT_CONST(20)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_LSB                   MK_SHIFT_CONST(20)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_WOFFSET                       0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_UNSET                 MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_SET                   MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_SHIFT                    MK_SHIFT_CONST(17)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_RANGE                    17:17
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_MSB                      MK_SHIFT_CONST(17)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_LSB                      MK_SHIFT_CONST(17)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_WOFFSET                  0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_UNSET                    MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_SET                      MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_SHIFT                    MK_SHIFT_CONST(16)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_RANGE                    16:16
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_MSB                      MK_SHIFT_CONST(16)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_LSB                      MK_SHIFT_CONST(16)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_WOFFSET                  0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_UNSET                    MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_SET                      MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_SHIFT                        MK_SHIFT_CONST(11)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_RANGE                        11:11
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_MSB                  MK_SHIFT_CONST(11)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_LSB                  MK_SHIFT_CONST(11)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_WOFFSET                      0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_UNSET                        MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_SET                  MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_SHIFT                     MK_SHIFT_CONST(10)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_RANGE                     10:10
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_MSB                       MK_SHIFT_CONST(10)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_LSB                       MK_SHIFT_CONST(10)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_WOFFSET                   0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_UNSET                     MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_SET                       MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_SHIFT                     MK_SHIFT_CONST(9)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_RANGE                     9:9
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_MSB                       MK_SHIFT_CONST(9)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_LSB                       MK_SHIFT_CONST(9)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_WOFFSET                   0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_UNSET                     MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_SET                       MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_SHIFT                       MK_SHIFT_CONST(8)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_RANGE                       8:8
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_MSB                 MK_SHIFT_CONST(8)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_LSB                 MK_SHIFT_CONST(8)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_WOFFSET                     0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_UNSET                       MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_SET                 MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT                  MK_SHIFT_CONST(7)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_RANGE                  7:7
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_MSB                    MK_SHIFT_CONST(7)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_LSB                    MK_SHIFT_CONST(7)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_WOFFSET                        0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_UNSET                  MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_SET                    MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT                     MK_SHIFT_CONST(6)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_RANGE                     6:6
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_MSB                       MK_SHIFT_CONST(6)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_LSB                       MK_SHIFT_CONST(6)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_WOFFSET                   0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_UNSET                     MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SET                       MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_SHIFT                     MK_SHIFT_CONST(5)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_RANGE                     5:5
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_MSB                       MK_SHIFT_CONST(5)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_LSB                       MK_SHIFT_CONST(5)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_WOFFSET                   0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_UNSET                     MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_SET                       MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_SHIFT                     MK_SHIFT_CONST(4)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_RANGE                     4:4
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_MSB                       MK_SHIFT_CONST(4)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_LSB                       MK_SHIFT_CONST(4)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_WOFFSET                   0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_UNSET                     MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_SET                       MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_SHIFT                 MK_SHIFT_CONST(3)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_RANGE                 3:3
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_MSB                   MK_SHIFT_CONST(3)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_LSB                   MK_SHIFT_CONST(3)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_WOFFSET                       0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_UNSET                 MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_SET                   MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_SHIFT                      MK_SHIFT_CONST(2)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_RANGE                      2:2
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_MSB                        MK_SHIFT_CONST(2)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_LSB                        MK_SHIFT_CONST(2)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_WOFFSET                    0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_UNSET                      MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_SET                        MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_SHIFT                        MK_SHIFT_CONST(1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_RANGE                        1:1
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_MSB                  MK_SHIFT_CONST(1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_LSB                  MK_SHIFT_CONST(1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_WOFFSET                      0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_UNSET                        MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_SET                  MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_SHIFT                        MK_SHIFT_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_SHIFT)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_RANGE                        0:0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_MSB                  MK_SHIFT_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_LSB                  MK_SHIFT_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_WOFFSET                      0x0
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_UNSET                        MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_SET                  MK_ENUM_CONST(1)

// Register I2C_I2C_INTERRUPT_SET_REGISTER_0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0                        MK_ADDR_CONST(0x74)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SECURE                         0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_DUAL                   0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SCR                    0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SCRREG                         0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_WORD_COUNT                     0x1
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RESET_MASK                     MK_MASK_CONST(0x1ff00ffc)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_READ_MASK                      MK_MASK_CONST(0x1ff00ffc)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_WRITE_MASK                     MK_MASK_CONST(0x1ff00ffc)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_SHIFT                 MK_SHIFT_CONST(28)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_RANGE                 28:28
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_MSB                   MK_SHIFT_CONST(28)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_LSB                   MK_SHIFT_CONST(28)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_WOFFSET                       0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_UNSET                 MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_SET                   MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_SHIFT                        MK_SHIFT_CONST(27)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_RANGE                        27:27
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_MSB                  MK_SHIFT_CONST(27)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_LSB                  MK_SHIFT_CONST(27)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_WOFFSET                      0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_UNSET                        MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_SET                  MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_SHIFT                        MK_SHIFT_CONST(26)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_RANGE                        26:26
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_MSB                  MK_SHIFT_CONST(26)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_LSB                  MK_SHIFT_CONST(26)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_WOFFSET                      0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_UNSET                        MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_SET                  MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_SHIFT                 MK_SHIFT_CONST(25)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_RANGE                 25:25
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_MSB                   MK_SHIFT_CONST(25)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_LSB                   MK_SHIFT_CONST(25)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_WOFFSET                       0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_UNSET                 MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_SET                   MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_SHIFT                        MK_SHIFT_CONST(24)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_RANGE                        24:24
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_MSB                  MK_SHIFT_CONST(24)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_LSB                  MK_SHIFT_CONST(24)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_WOFFSET                      0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_UNSET                        MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_SET                  MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_SHIFT                     MK_SHIFT_CONST(23)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_RANGE                     23:23
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_MSB                       MK_SHIFT_CONST(23)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_LSB                       MK_SHIFT_CONST(23)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_WOFFSET                   0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_UNSET                     MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_SET                       MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SHIFT                 MK_SHIFT_CONST(22)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_RANGE                 22:22
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_MSB                   MK_SHIFT_CONST(22)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_LSB                   MK_SHIFT_CONST(22)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_WOFFSET                       0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_UNSET                 MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SET                   MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_SHIFT                    MK_SHIFT_CONST(21)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_RANGE                    21:21
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_MSB                      MK_SHIFT_CONST(21)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_LSB                      MK_SHIFT_CONST(21)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_WOFFSET                  0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_UNSET                    MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_SET                      MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_SHIFT                    MK_SHIFT_CONST(20)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_RANGE                    20:20
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_MSB                      MK_SHIFT_CONST(20)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_LSB                      MK_SHIFT_CONST(20)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_WOFFSET                  0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_UNSET                    MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_SET                      MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_SHIFT                   MK_SHIFT_CONST(11)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_RANGE                   11:11
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_MSB                     MK_SHIFT_CONST(11)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_LSB                     MK_SHIFT_CONST(11)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_WOFFSET                 0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_UNSET                   MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_SET                     MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_SHIFT                        MK_SHIFT_CONST(10)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_RANGE                        10:10
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_MSB                  MK_SHIFT_CONST(10)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_LSB                  MK_SHIFT_CONST(10)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_WOFFSET                      0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_UNSET                        MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_SET                  MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_SHIFT                        MK_SHIFT_CONST(9)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_RANGE                        9:9
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_MSB                  MK_SHIFT_CONST(9)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_LSB                  MK_SHIFT_CONST(9)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_WOFFSET                      0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_UNSET                        MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_SET                  MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_SHIFT                  MK_SHIFT_CONST(8)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_RANGE                  8:8
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_MSB                    MK_SHIFT_CONST(8)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_LSB                    MK_SHIFT_CONST(8)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_WOFFSET                        0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_UNSET                  MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_SET                    MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT                     MK_SHIFT_CONST(7)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_RANGE                     7:7
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_MSB                       MK_SHIFT_CONST(7)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_LSB                       MK_SHIFT_CONST(7)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_WOFFSET                   0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_UNSET                     MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_SET                       MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT                        MK_SHIFT_CONST(6)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_RANGE                        6:6
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_MSB                  MK_SHIFT_CONST(6)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_LSB                  MK_SHIFT_CONST(6)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_WOFFSET                      0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_UNSET                        MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SET                  MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_SHIFT                        MK_SHIFT_CONST(5)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_RANGE                        5:5
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_MSB                  MK_SHIFT_CONST(5)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_LSB                  MK_SHIFT_CONST(5)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_WOFFSET                      0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_UNSET                        MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_SET                  MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_SHIFT                        MK_SHIFT_CONST(4)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_RANGE                        4:4
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_MSB                  MK_SHIFT_CONST(4)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_LSB                  MK_SHIFT_CONST(4)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_WOFFSET                      0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_UNSET                        MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_SET                  MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_SHIFT                    MK_SHIFT_CONST(3)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_RANGE                    3:3
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_MSB                      MK_SHIFT_CONST(3)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_LSB                      MK_SHIFT_CONST(3)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_WOFFSET                  0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_UNSET                    MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_SET                      MK_ENUM_CONST(1)

#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_SHIFT                 MK_SHIFT_CONST(2)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_SHIFT)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_RANGE                 2:2
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_MSB                   MK_SHIFT_CONST(2)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_LSB                   MK_SHIFT_CONST(2)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_WOFFSET                       0x0
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_UNSET                 MK_ENUM_CONST(0)
#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_SET                   MK_ENUM_CONST(1)

// Register I2C_I2C_SLV_TX_PACKET_FIFO_0
#define I2C_I2C_SLV_TX_PACKET_FIFO_0                    MK_ADDR_CONST(0x78)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_SECURE                     0x0
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_DUAL                       0x0
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_SCR                        0
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_SCRREG                     0
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_WORD_COUNT                         0x1
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_SHIFT                    MK_SHIFT_CONST(0)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_FIELD                    MK_FIELD_CONST(0xffffffff, I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_SHIFT)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_RANGE                    31:0
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_MSB                      MK_SHIFT_CONST(31)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_LSB                      MK_SHIFT_CONST(0)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_WOFFSET                  0x0
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

// Register I2C_I2C_SLV_RX_FIFO_0
#define I2C_I2C_SLV_RX_FIFO_0                   MK_ADDR_CONST(0x7c)
#define I2C_I2C_SLV_RX_FIFO_0_SECURE                    0x0
#define I2C_I2C_SLV_RX_FIFO_0_DUAL                      0x0
#define I2C_I2C_SLV_RX_FIFO_0_SCR                       0
#define I2C_I2C_SLV_RX_FIFO_0_SCRREG                    0
#define I2C_I2C_SLV_RX_FIFO_0_WORD_COUNT                        0x1
#define I2C_I2C_SLV_RX_FIFO_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RX_FIFO_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
#define I2C_I2C_SLV_RX_FIFO_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RX_FIFO_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RX_FIFO_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
#define I2C_I2C_SLV_RX_FIFO_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_SHIFT                     MK_SHIFT_CONST(0)
#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_FIELD                     MK_FIELD_CONST(0xffffffff, I2C_I2C_SLV_RX_FIFO_0_RD_DATA_SHIFT)
#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_RANGE                     31:0
#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_MSB                       MK_SHIFT_CONST(31)
#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_LSB                       MK_SHIFT_CONST(0)
#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_WOFFSET                   0x0
#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

// Register I2C_I2C_SLV_PACKET_STATUS_0
#define I2C_I2C_SLV_PACKET_STATUS_0                     MK_ADDR_CONST(0x80)
#define I2C_I2C_SLV_PACKET_STATUS_0_SECURE                      0x0
#define I2C_I2C_SLV_PACKET_STATUS_0_DUAL                        0x0
#define I2C_I2C_SLV_PACKET_STATUS_0_SCR                         0
#define I2C_I2C_SLV_PACKET_STATUS_0_SCRREG                      0
#define I2C_I2C_SLV_PACKET_STATUS_0_WORD_COUNT                  0x1
#define I2C_I2C_SLV_PACKET_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x3ffffff)
#define I2C_I2C_SLV_PACKET_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_READ_MASK                   MK_MASK_CONST(0x3ffffff)
#define I2C_I2C_SLV_PACKET_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_SHIFT                  MK_SHIFT_CONST(25)
#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_SHIFT)
#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_RANGE                  25:25
#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_MSB                    MK_SHIFT_CONST(25)
#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_LSB                    MK_SHIFT_CONST(25)
#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_WOFFSET                        0x0
#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_SHIFT                     MK_SHIFT_CONST(24)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_SHIFT)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_RANGE                     24:24
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_MSB                       MK_SHIFT_CONST(24)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_LSB                       MK_SHIFT_CONST(24)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_WOFFSET                   0x0
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_SHIFT                       MK_SHIFT_CONST(16)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_FIELD                       MK_FIELD_CONST(0xff, I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_SHIFT)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_RANGE                       23:16
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_MSB                 MK_SHIFT_CONST(23)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_LSB                 MK_SHIFT_CONST(16)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_WOFFSET                     0x0
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_SHIFT                      MK_SHIFT_CONST(0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_FIELD                      MK_FIELD_CONST(0xffff, I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_SHIFT)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_RANGE                      15:0
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_MSB                        MK_SHIFT_CONST(15)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_LSB                        MK_SHIFT_CONST(0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_WOFFSET                    0x0
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

// Register I2C_I2C_BUS_CLEAR_CONFIG_0
#define I2C_I2C_BUS_CLEAR_CONFIG_0                      MK_ADDR_CONST(0x84)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_SECURE                       0x0
#define I2C_I2C_BUS_CLEAR_CONFIG_0_DUAL                         0x0
#define I2C_I2C_BUS_CLEAR_CONFIG_0_SCR                  0
#define I2C_I2C_BUS_CLEAR_CONFIG_0_SCRREG                       0
#define I2C_I2C_BUS_CLEAR_CONFIG_0_WORD_COUNT                   0x1
#define I2C_I2C_BUS_CLEAR_CONFIG_0_RESET_VAL                    MK_MASK_CONST(0x90004)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_RESET_MASK                   MK_MASK_CONST(0xff0007)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_READ_MASK                    MK_MASK_CONST(0xff0007)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_WRITE_MASK                   MK_MASK_CONST(0xff0007)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_SHIFT                      MK_SHIFT_CONST(16)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_FIELD                      MK_FIELD_CONST(0xff, I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_SHIFT)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_RANGE                      23:16
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_MSB                        MK_SHIFT_CONST(23)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_LSB                        MK_SHIFT_CONST(16)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_WOFFSET                    0x0
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_DEFAULT                    MK_MASK_CONST(0x9)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_SHIFT                   MK_SHIFT_CONST(2)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_SHIFT)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_RANGE                   2:2
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_MSB                     MK_SHIFT_CONST(2)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_LSB                     MK_SHIFT_CONST(2)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_WOFFSET                 0x0
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_DEFAULT                 MK_MASK_CONST(0x1)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_NO_STOP                 MK_ENUM_CONST(0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_STOP                    MK_ENUM_CONST(1)

#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_SHIFT                   MK_SHIFT_CONST(1)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_SHIFT)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_RANGE                   1:1
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_MSB                     MK_SHIFT_CONST(1)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_LSB                     MK_SHIFT_CONST(1)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_WOFFSET                 0x0
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_THRESHOLD                       MK_ENUM_CONST(0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_IMMEDIATE                       MK_ENUM_CONST(1)

#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_SHIFT)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_RANGE                      0:0
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_MSB                        MK_SHIFT_CONST(0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_LSB                        MK_SHIFT_CONST(0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_WOFFSET                    0x0
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

// Register I2C_I2C_BUS_CLEAR_STATUS_0
#define I2C_I2C_BUS_CLEAR_STATUS_0                      MK_ADDR_CONST(0x88)
#define I2C_I2C_BUS_CLEAR_STATUS_0_SECURE                       0x0
#define I2C_I2C_BUS_CLEAR_STATUS_0_DUAL                         0x0
#define I2C_I2C_BUS_CLEAR_STATUS_0_SCR                  0
#define I2C_I2C_BUS_CLEAR_STATUS_0_SCRREG                       0
#define I2C_I2C_BUS_CLEAR_STATUS_0_WORD_COUNT                   0x1
#define I2C_I2C_BUS_CLEAR_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define I2C_I2C_BUS_CLEAR_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_STATUS_0_READ_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_BUS_CLEAR_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_SHIFT                      MK_SHIFT_CONST(0)
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_SHIFT)
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_RANGE                      0:0
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_MSB                        MK_SHIFT_CONST(0)
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_LSB                        MK_SHIFT_CONST(0)
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_WOFFSET                    0x0
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_NOT_CLEARED                        MK_ENUM_CONST(0)
#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_CLEARED                    MK_ENUM_CONST(1)

// Register I2C_I2C_CONFIG_LOAD_0
#define I2C_I2C_CONFIG_LOAD_0                   MK_ADDR_CONST(0x8c)
#define I2C_I2C_CONFIG_LOAD_0_SECURE                    0x0
#define I2C_I2C_CONFIG_LOAD_0_DUAL                      0x0
#define I2C_I2C_CONFIG_LOAD_0_SCR                       0
#define I2C_I2C_CONFIG_LOAD_0_SCRREG                    0
#define I2C_I2C_CONFIG_LOAD_0_WORD_COUNT                        0x1
#define I2C_I2C_CONFIG_LOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define I2C_I2C_CONFIG_LOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_READ_MASK                         MK_MASK_CONST(0x7)
#define I2C_I2C_CONFIG_LOAD_0_WRITE_MASK                        MK_MASK_CONST(0x7)
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_SHIFT                 MK_SHIFT_CONST(2)
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_SHIFT)
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_RANGE                 2:2
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_MSB                   MK_SHIFT_CONST(2)
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_LSB                   MK_SHIFT_CONST(2)
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_WOFFSET                       0x0
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_DISABLE                       MK_ENUM_CONST(0)
#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_ENABLE                        MK_ENUM_CONST(1)

#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_SHIFT                     MK_SHIFT_CONST(1)
#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_SHIFT)
#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_RANGE                     1:1
#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_MSB                       MK_SHIFT_CONST(1)
#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_LSB                       MK_SHIFT_CONST(1)
#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_WOFFSET                   0x0
#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_DISABLE                   MK_ENUM_CONST(0)
#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_ENABLE                    MK_ENUM_CONST(1)

#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_SHIFT                    MK_SHIFT_CONST(0)
#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_SHIFT)
#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_RANGE                    0:0
#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_MSB                      MK_SHIFT_CONST(0)
#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_LSB                      MK_SHIFT_CONST(0)
#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_WOFFSET                  0x0
#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_DISABLE                  MK_ENUM_CONST(0)
#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_ENABLE                   MK_ENUM_CONST(1)

// Register I2C_I2C_CLKEN_OVERRIDE_0
#define I2C_I2C_CLKEN_OVERRIDE_0                        MK_ADDR_CONST(0x90)
#define I2C_I2C_CLKEN_OVERRIDE_0_SECURE                         0x0
#define I2C_I2C_CLKEN_OVERRIDE_0_DUAL                   0x0
#define I2C_I2C_CLKEN_OVERRIDE_0_SCR                    0
#define I2C_I2C_CLKEN_OVERRIDE_0_SCRREG                         0
#define I2C_I2C_CLKEN_OVERRIDE_0_WORD_COUNT                     0x1
#define I2C_I2C_CLKEN_OVERRIDE_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_RESET_MASK                     MK_MASK_CONST(0x1d)
#define I2C_I2C_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_READ_MASK                      MK_MASK_CONST(0x1d)
#define I2C_I2C_CLKEN_OVERRIDE_0_WRITE_MASK                     MK_MASK_CONST(0x1d)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_SHIFT                   MK_SHIFT_CONST(0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_SHIFT)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_RANGE                   0:0
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_MSB                     MK_SHIFT_CONST(0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_LSB                     MK_SHIFT_CONST(0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_WOFFSET                 0x0
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_INIT_ENUM                       CLK_GATED
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_CLK_GATED                       MK_ENUM_CONST(0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_CLK_ALWAYS_ON                   MK_ENUM_CONST(1)

#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_SHIFT                   MK_SHIFT_CONST(2)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_SHIFT)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_RANGE                   2:2
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_MSB                     MK_SHIFT_CONST(2)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_LSB                     MK_SHIFT_CONST(2)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_WOFFSET                 0x0
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_INIT_ENUM                       CLK_GATED
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_CLK_GATED                       MK_ENUM_CONST(0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_CLK_ALWAYS_ON                   MK_ENUM_CONST(1)

#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_SHIFT                    MK_SHIFT_CONST(3)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_SHIFT)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_RANGE                    3:3
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_MSB                      MK_SHIFT_CONST(3)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_LSB                      MK_SHIFT_CONST(3)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_WOFFSET                  0x0
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_INIT_ENUM                        CLK_GATED
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_CLK_GATED                        MK_ENUM_CONST(0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_CLK_ALWAYS_ON                    MK_ENUM_CONST(1)

#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_SHIFT                  MK_SHIFT_CONST(4)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_SHIFT)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_RANGE                  4:4
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_MSB                    MK_SHIFT_CONST(4)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_LSB                    MK_SHIFT_CONST(4)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_WOFFSET                        0x0
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_INIT_ENUM                      CLK_GATED
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_CLK_GATED                      MK_ENUM_CONST(0)
#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_CLK_ALWAYS_ON                  MK_ENUM_CONST(1)

// Register I2C_I2C_INTERFACE_TIMING_0_0
#define I2C_I2C_INTERFACE_TIMING_0_0                    MK_ADDR_CONST(0x94)
#define I2C_I2C_INTERFACE_TIMING_0_0_SECURE                     0x0
#define I2C_I2C_INTERFACE_TIMING_0_0_DUAL                       0x0
#define I2C_I2C_INTERFACE_TIMING_0_0_SCR                        0
#define I2C_I2C_INTERFACE_TIMING_0_0_SCRREG                     0
#define I2C_I2C_INTERFACE_TIMING_0_0_WORD_COUNT                         0x1
#define I2C_I2C_INTERFACE_TIMING_0_0_RESET_VAL                  MK_MASK_CONST(0x204)
#define I2C_I2C_INTERFACE_TIMING_0_0_RESET_MASK                         MK_MASK_CONST(0xffff)
#define I2C_I2C_INTERFACE_TIMING_0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_0_0_READ_MASK                  MK_MASK_CONST(0xffff)
#define I2C_I2C_INTERFACE_TIMING_0_0_WRITE_MASK                         MK_MASK_CONST(0xffff)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_SHIFT                        MK_SHIFT_CONST(8)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_FIELD                        MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_0_0_THIGH_SHIFT)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_RANGE                        15:8
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_MSB                  MK_SHIFT_CONST(15)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_LSB                  MK_SHIFT_CONST(8)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_WOFFSET                      0x0
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_DEFAULT                      MK_MASK_CONST(0x2)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH__PROD_C_SM                   MK_ENUM_CONST(7)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH__PROD_C_FM                   MK_ENUM_CONST(1)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH__PROD_C_FMPLUS                       MK_ENUM_CONST(1)
#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH__PROD_C_HS                   MK_ENUM_CONST(1)

#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_SHIFT                 MK_SHIFT_CONST(0)
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_0_0_TLOW_SHIFT)
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_RANGE                 7:0
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_MSB                   MK_SHIFT_CONST(7)
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_LSB                   MK_SHIFT_CONST(0)
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_WOFFSET                       0x0
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_DEFAULT                       MK_MASK_CONST(0x4)
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW__PROD_C_SM                    MK_ENUM_CONST(8)
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW__PROD_C_FM                    MK_ENUM_CONST(1)
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW__PROD_C_FMPLUS                        MK_ENUM_CONST(1)
#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW__PROD_C_HS                    MK_ENUM_CONST(1)

// Register I2C_I2C_INTERFACE_TIMING_1_0
#define I2C_I2C_INTERFACE_TIMING_1_0                    MK_ADDR_CONST(0x98)
#define I2C_I2C_INTERFACE_TIMING_1_0_SECURE                     0x0
#define I2C_I2C_INTERFACE_TIMING_1_0_DUAL                       0x0
#define I2C_I2C_INTERFACE_TIMING_1_0_SCR                        0
#define I2C_I2C_INTERFACE_TIMING_1_0_SCRREG                     0
#define I2C_I2C_INTERFACE_TIMING_1_0_WORD_COUNT                         0x1
#define I2C_I2C_INTERFACE_TIMING_1_0_RESET_VAL                  MK_MASK_CONST(0x4070404)
#define I2C_I2C_INTERFACE_TIMING_1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define I2C_I2C_INTERFACE_TIMING_1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define I2C_I2C_INTERFACE_TIMING_1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_SHIFT                 MK_SHIFT_CONST(24)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_1_0_TBUF_SHIFT)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_RANGE                 31:24
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_MSB                   MK_SHIFT_CONST(31)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_LSB                   MK_SHIFT_CONST(24)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_WOFFSET                       0x0
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_DEFAULT                       MK_MASK_CONST(0x4)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF__PROD_C_SM                    MK_ENUM_CONST(8)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF__PROD_C_FM                    MK_ENUM_CONST(2)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF__PROD_C_FMPLUS                        MK_ENUM_CONST(2)
#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF__PROD_C_HS                    MK_ENUM_CONST(2)

#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_SHIFT                      MK_SHIFT_CONST(16)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_FIELD                      MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_SHIFT)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_RANGE                      23:16
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_MSB                        MK_SHIFT_CONST(23)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_LSB                        MK_SHIFT_CONST(16)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_WOFFSET                    0x0
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_DEFAULT                    MK_MASK_CONST(0x7)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO__PROD_C_SM                 MK_ENUM_CONST(8)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO__PROD_C_FM                 MK_ENUM_CONST(2)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO__PROD_C_FMPLUS                     MK_ENUM_CONST(2)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO__PROD_C_HS                 MK_ENUM_CONST(2)

#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_SHIFT                      MK_SHIFT_CONST(8)
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_FIELD                      MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_SHIFT)
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_RANGE                      15:8
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_MSB                        MK_SHIFT_CONST(15)
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_LSB                        MK_SHIFT_CONST(8)
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_WOFFSET                    0x0
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_DEFAULT                    MK_MASK_CONST(0x4)
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA__PROD_C_SM                 MK_ENUM_CONST(8)
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA__PROD_C_FM                 MK_ENUM_CONST(2)
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA__PROD_C_FMPLUS                     MK_ENUM_CONST(2)
#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA__PROD_C_HS                 MK_ENUM_CONST(2)

#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_SHIFT                      MK_SHIFT_CONST(0)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_FIELD                      MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_SHIFT)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_RANGE                      7:0
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_MSB                        MK_SHIFT_CONST(7)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_LSB                        MK_SHIFT_CONST(0)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_WOFFSET                    0x0
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_DEFAULT                    MK_MASK_CONST(0x4)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA__PROD_C_SM                 MK_ENUM_CONST(8)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA__PROD_C_FM                 MK_ENUM_CONST(2)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA__PROD_C_FMPLUS                     MK_ENUM_CONST(2)
#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA__PROD_C_HS                 MK_ENUM_CONST(2)

// Register I2C_I2C_HS_INTERFACE_TIMING_0_0
#define I2C_I2C_HS_INTERFACE_TIMING_0_0                 MK_ADDR_CONST(0x9c)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_SECURE                  0x0
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_DUAL                    0x0
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_SCR                     0
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_SCRREG                  0
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_WORD_COUNT                      0x1
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_RESET_VAL                       MK_MASK_CONST(0x308)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_SHIFT                  MK_SHIFT_CONST(8)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_FIELD                  MK_FIELD_CONST(0xff, I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_SHIFT)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_RANGE                  15:8
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_MSB                    MK_SHIFT_CONST(15)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_LSB                    MK_SHIFT_CONST(8)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_WOFFSET                        0x0
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_DEFAULT                        MK_MASK_CONST(0x3)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH__PROD                  MK_ENUM_CONST(3)

#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_SHIFT                   MK_SHIFT_CONST(0)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_FIELD                   MK_FIELD_CONST(0xff, I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_SHIFT)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_RANGE                   7:0
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_MSB                     MK_SHIFT_CONST(7)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_LSB                     MK_SHIFT_CONST(0)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_WOFFSET                 0x0
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_DEFAULT                 MK_MASK_CONST(0x8)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW__PROD                   MK_ENUM_CONST(8)

// Register I2C_I2C_HS_INTERFACE_TIMING_1_0
#define I2C_I2C_HS_INTERFACE_TIMING_1_0                 MK_ADDR_CONST(0xa0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_SECURE                  0x0
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_DUAL                    0x0
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_SCR                     0
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_SCRREG                  0
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_WORD_COUNT                      0x1
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_RESET_VAL                       MK_MASK_CONST(0xb0b0b)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_READ_MASK                       MK_MASK_CONST(0xffffff)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_SHIFT                        MK_SHIFT_CONST(16)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_FIELD                        MK_FIELD_CONST(0xff, I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_SHIFT)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_RANGE                        23:16
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_MSB                  MK_SHIFT_CONST(23)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_LSB                  MK_SHIFT_CONST(16)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_WOFFSET                      0x0
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_DEFAULT                      MK_MASK_CONST(0xb)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO__PROD_C_HS                   MK_ENUM_CONST(9)

#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_SHIFT                        MK_SHIFT_CONST(8)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_FIELD                        MK_FIELD_CONST(0xff, I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_SHIFT)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_RANGE                        15:8
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_MSB                  MK_SHIFT_CONST(15)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_LSB                  MK_SHIFT_CONST(8)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_WOFFSET                      0x0
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_DEFAULT                      MK_MASK_CONST(0xb)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA__PROD_C_HS                   MK_ENUM_CONST(9)

#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_SHIFT                        MK_SHIFT_CONST(0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_FIELD                        MK_FIELD_CONST(0xff, I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_SHIFT)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_RANGE                        7:0
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_MSB                  MK_SHIFT_CONST(7)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_LSB                  MK_SHIFT_CONST(0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_WOFFSET                      0x0
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_DEFAULT                      MK_MASK_CONST(0xb)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA__PROD_C_HS                   MK_ENUM_CONST(9)

// Register I2C_I2C_MASTER_RESET_CNTRL_0
#define I2C_I2C_MASTER_RESET_CNTRL_0                    MK_ADDR_CONST(0xa8)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SECURE                     0x0
#define I2C_I2C_MASTER_RESET_CNTRL_0_DUAL                       0x0
#define I2C_I2C_MASTER_RESET_CNTRL_0_SCR                        0
#define I2C_I2C_MASTER_RESET_CNTRL_0_SCRREG                     0
#define I2C_I2C_MASTER_RESET_CNTRL_0_WORD_COUNT                         0x1
#define I2C_I2C_MASTER_RESET_CNTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define I2C_I2C_MASTER_RESET_CNTRL_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_MASTER_RESET_CNTRL_0_READ_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_MASTER_RESET_CNTRL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_SHIFT                   MK_SHIFT_CONST(0)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_SHIFT)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_RANGE                   0:0
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_MSB                     MK_SHIFT_CONST(0)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_LSB                     MK_SHIFT_CONST(0)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_WOFFSET                 0x0
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_CLEARED                 MK_ENUM_CONST(0)
#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_ASSERTED                        MK_ENUM_CONST(1)

// Register I2C_I2C_SLV_RESET_CNTRL_0
#define I2C_I2C_SLV_RESET_CNTRL_0                       MK_ADDR_CONST(0xac)
#define I2C_I2C_SLV_RESET_CNTRL_0_SECURE                        0x0
#define I2C_I2C_SLV_RESET_CNTRL_0_DUAL                  0x0
#define I2C_I2C_SLV_RESET_CNTRL_0_SCR                   0
#define I2C_I2C_SLV_RESET_CNTRL_0_SCRREG                        0
#define I2C_I2C_SLV_RESET_CNTRL_0_WORD_COUNT                    0x1
#define I2C_I2C_SLV_RESET_CNTRL_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RESET_CNTRL_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_SLV_RESET_CNTRL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RESET_CNTRL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RESET_CNTRL_0_READ_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_SLV_RESET_CNTRL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_SHIFT                      MK_SHIFT_CONST(0)
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_SHIFT)
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_RANGE                      0:0
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_MSB                        MK_SHIFT_CONST(0)
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_LSB                        MK_SHIFT_CONST(0)
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_WOFFSET                    0x0
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_CLEARED                    MK_ENUM_CONST(0)
#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_ASSERTED                   MK_ENUM_CONST(1)

// Register I2C_MST_PACKET_TRANSFER_CNT_STATUS_0
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0                    MK_ADDR_CONST(0xb0)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_SECURE                     0x0
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_DUAL                       0x0
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_SCR                        0
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_SCRREG                     0
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_WORD_COUNT                         0x1
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_RESET_MASK                         MK_MASK_CONST(0xffff)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_READ_MASK                  MK_MASK_CONST(0xffff)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_SHIFT                     MK_SHIFT_CONST(0)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_FIELD                     MK_FIELD_CONST(0xffff, I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_SHIFT)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_RANGE                     15:0
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_MSB                       MK_SHIFT_CONST(15)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_LSB                       MK_SHIFT_CONST(0)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_WOFFSET                   0x0
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

// Register I2C_MST_FIFO_CONTROL_0
#define I2C_MST_FIFO_CONTROL_0                  MK_ADDR_CONST(0xb4)
#define I2C_MST_FIFO_CONTROL_0_SECURE                   0x0
#define I2C_MST_FIFO_CONTROL_0_DUAL                     0x0
#define I2C_MST_FIFO_CONTROL_0_SCR                      0
#define I2C_MST_FIFO_CONTROL_0_SCRREG                   0
#define I2C_MST_FIFO_CONTROL_0_WORD_COUNT                       0x1
#define I2C_MST_FIFO_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x7f07f3)
#define I2C_MST_FIFO_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x7f07f3)
#define I2C_MST_FIFO_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x7f07f3)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT                       MK_SHIFT_CONST(16)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_FIELD                       MK_FIELD_CONST(0x7f, I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_RANGE                       22:16
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_MSB                 MK_SHIFT_CONST(22)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_LSB                 MK_SHIFT_CONST(16)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_WOFFSET                     0x0
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT                       MK_SHIFT_CONST(4)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_FIELD                       MK_FIELD_CONST(0x7f, I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_RANGE                       10:4
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_MSB                 MK_SHIFT_CONST(10)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_LSB                 MK_SHIFT_CONST(4)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_WOFFSET                     0x0
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT                      MK_SHIFT_CONST(1)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_FIELD                      MK_FIELD_CONST(0x1, I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_RANGE                      1:1
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_MSB                        MK_SHIFT_CONST(1)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_LSB                        MK_SHIFT_CONST(1)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_WOFFSET                    0x0
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_UNSET                      MK_ENUM_CONST(0)
#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_SET                        MK_ENUM_CONST(1)

#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT                      MK_SHIFT_CONST(0)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_FIELD                      MK_FIELD_CONST(0x1, I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_RANGE                      0:0
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_MSB                        MK_SHIFT_CONST(0)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_LSB                        MK_SHIFT_CONST(0)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_WOFFSET                    0x0
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_UNSET                      MK_ENUM_CONST(0)
#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_SET                        MK_ENUM_CONST(1)

// Register I2C_MST_FIFO_STATUS_0
#define I2C_MST_FIFO_STATUS_0                   MK_ADDR_CONST(0xb8)
#define I2C_MST_FIFO_STATUS_0_SECURE                    0x0
#define I2C_MST_FIFO_STATUS_0_DUAL                      0x0
#define I2C_MST_FIFO_STATUS_0_SCR                       0
#define I2C_MST_FIFO_STATUS_0_SCRREG                    0
#define I2C_MST_FIFO_STATUS_0_WORD_COUNT                        0x1
#define I2C_MST_FIFO_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x800000)
#define I2C_MST_FIFO_STATUS_0_RESET_MASK                        MK_MASK_CONST(0xff00ff)
#define I2C_MST_FIFO_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_STATUS_0_READ_MASK                         MK_MASK_CONST(0xff00ff)
#define I2C_MST_FIFO_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT                   MK_SHIFT_CONST(16)
#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_FIELD                   MK_FIELD_CONST(0xff, I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT)
#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_RANGE                   23:16
#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_MSB                     MK_SHIFT_CONST(23)
#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_LSB                     MK_SHIFT_CONST(16)
#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_WOFFSET                 0x0
#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT                 MK_MASK_CONST(0x80)
#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT                    MK_SHIFT_CONST(0)
#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_FIELD                    MK_FIELD_CONST(0xff, I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT)
#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_RANGE                    7:0
#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_MSB                      MK_SHIFT_CONST(7)
#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_LSB                      MK_SHIFT_CONST(0)
#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_WOFFSET                  0x0
#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

// Register I2C_SLV_PAYLOAD_0
#define I2C_SLV_PAYLOAD_0                       MK_ADDR_CONST(0xbc)
#define I2C_SLV_PAYLOAD_0_SECURE                        0x0
#define I2C_SLV_PAYLOAD_0_DUAL                  0x0
#define I2C_SLV_PAYLOAD_0_SCR                   0
#define I2C_SLV_PAYLOAD_0_SCRREG                        0
#define I2C_SLV_PAYLOAD_0_WORD_COUNT                    0x1
#define I2C_SLV_PAYLOAD_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define I2C_SLV_PAYLOAD_0_RESET_MASK                    MK_MASK_CONST(0xffff)
#define I2C_SLV_PAYLOAD_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define I2C_SLV_PAYLOAD_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_SLV_PAYLOAD_0_READ_MASK                     MK_MASK_CONST(0xffff)
#define I2C_SLV_PAYLOAD_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_SHIFT                     MK_SHIFT_CONST(0)
#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_FIELD                     MK_FIELD_CONST(0xffff, I2C_SLV_PAYLOAD_0_BUFFER_SIZE_SHIFT)
#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_RANGE                     15:0
#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_MSB                       MK_SHIFT_CONST(15)
#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_LSB                       MK_SHIFT_CONST(0)
#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_WOFFSET                   0x0
#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

// Register I2C_SLV_FIFO_CONTROL_0
#define I2C_SLV_FIFO_CONTROL_0                  MK_ADDR_CONST(0xc0)
#define I2C_SLV_FIFO_CONTROL_0_SECURE                   0x0
#define I2C_SLV_FIFO_CONTROL_0_DUAL                     0x0
#define I2C_SLV_FIFO_CONTROL_0_SCR                      0
#define I2C_SLV_FIFO_CONTROL_0_SCRREG                   0
#define I2C_SLV_FIFO_CONTROL_0_WORD_COUNT                       0x1
#define I2C_SLV_FIFO_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x7f07f3)
#define I2C_SLV_FIFO_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x7f07f3)
#define I2C_SLV_FIFO_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x7f07f3)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT                       MK_SHIFT_CONST(16)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_FIELD                       MK_FIELD_CONST(0x7f, I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_RANGE                       22:16
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_MSB                 MK_SHIFT_CONST(22)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_LSB                 MK_SHIFT_CONST(16)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_WOFFSET                     0x0
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT                       MK_SHIFT_CONST(4)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_FIELD                       MK_FIELD_CONST(0x7f, I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_RANGE                       10:4
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_MSB                 MK_SHIFT_CONST(10)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_LSB                 MK_SHIFT_CONST(4)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_WOFFSET                     0x0
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT                      MK_SHIFT_CONST(1)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_FIELD                      MK_FIELD_CONST(0x1, I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_RANGE                      1:1
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_MSB                        MK_SHIFT_CONST(1)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_LSB                        MK_SHIFT_CONST(1)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_WOFFSET                    0x0
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_UNSET                      MK_ENUM_CONST(0)
#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_SET                        MK_ENUM_CONST(1)

#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT                      MK_SHIFT_CONST(0)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_FIELD                      MK_FIELD_CONST(0x1, I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_RANGE                      0:0
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_MSB                        MK_SHIFT_CONST(0)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_LSB                        MK_SHIFT_CONST(0)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_WOFFSET                    0x0
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_UNSET                      MK_ENUM_CONST(0)
#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_SET                        MK_ENUM_CONST(1)

// Register I2C_SLV_FIFO_STATUS_0
#define I2C_SLV_FIFO_STATUS_0                   MK_ADDR_CONST(0xc4)
#define I2C_SLV_FIFO_STATUS_0_SECURE                    0x0
#define I2C_SLV_FIFO_STATUS_0_DUAL                      0x0
#define I2C_SLV_FIFO_STATUS_0_SCR                       0
#define I2C_SLV_FIFO_STATUS_0_SCRREG                    0
#define I2C_SLV_FIFO_STATUS_0_WORD_COUNT                        0x1
#define I2C_SLV_FIFO_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x800000)
#define I2C_SLV_FIFO_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x1ff00ff)
#define I2C_SLV_FIFO_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_READ_MASK                         MK_MASK_CONST(0x1ff00ff)
#define I2C_SLV_FIFO_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_SHIFT                 MK_SHIFT_CONST(24)
#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_FIELD                 MK_FIELD_CONST(0x1, I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_SHIFT)
#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_RANGE                 24:24
#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_MSB                   MK_SHIFT_CONST(24)
#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_LSB                   MK_SHIFT_CONST(24)
#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_WOFFSET                       0x0
#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT                   MK_SHIFT_CONST(16)
#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_FIELD                   MK_FIELD_CONST(0xff, I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT)
#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_RANGE                   23:16
#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_MSB                     MK_SHIFT_CONST(23)
#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_LSB                     MK_SHIFT_CONST(16)
#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_WOFFSET                 0x0
#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT                 MK_MASK_CONST(0x80)
#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT                    MK_SHIFT_CONST(0)
#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_FIELD                    MK_FIELD_CONST(0xff, I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT)
#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_RANGE                    7:0
#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_MSB                      MK_SHIFT_CONST(7)
#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_LSB                      MK_SHIFT_CONST(0)
#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_WOFFSET                  0x0
#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT_MASK                     MK_MASK_CONST(0xff)
#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

// Register I2C_I2C_MST_NM_INT_STATUS_0
#define I2C_I2C_MST_NM_INT_STATUS_0                     MK_ADDR_CONST(0xc8)
#define I2C_I2C_MST_NM_INT_STATUS_0_SECURE                      0x0
#define I2C_I2C_MST_NM_INT_STATUS_0_DUAL                        0x0
#define I2C_I2C_MST_NM_INT_STATUS_0_SCR                         0
#define I2C_I2C_MST_NM_INT_STATUS_0_SCRREG                      0
#define I2C_I2C_MST_NM_INT_STATUS_0_WORD_COUNT                  0x1
#define I2C_I2C_MST_NM_INT_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define I2C_I2C_MST_NM_INT_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_MST_NM_INT_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define I2C_I2C_MST_NM_INT_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_MST_NM_INT_STATUS_0_READ_MASK                   MK_MASK_CONST(0x1)
#define I2C_I2C_MST_NM_INT_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_SHIFT                      MK_SHIFT_CONST(0)
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_SHIFT)
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_RANGE                      0:0
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_MSB                        MK_SHIFT_CONST(0)
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_LSB                        MK_SHIFT_CONST(0)
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_WOFFSET                    0x0
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_UNSET                      MK_ENUM_CONST(0)
#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_SET                        MK_ENUM_CONST(1)

// Register I2C_I2C_MST_NM_INT_MASK_0
#define I2C_I2C_MST_NM_INT_MASK_0                       MK_ADDR_CONST(0xcc)
#define I2C_I2C_MST_NM_INT_MASK_0_SECURE                        0x0
#define I2C_I2C_MST_NM_INT_MASK_0_DUAL                  0x0
#define I2C_I2C_MST_NM_INT_MASK_0_SCR                   0
#define I2C_I2C_MST_NM_INT_MASK_0_SCRREG                        0
#define I2C_I2C_MST_NM_INT_MASK_0_WORD_COUNT                    0x1
#define I2C_I2C_MST_NM_INT_MASK_0_RESET_VAL                     MK_MASK_CONST(0x1)
#define I2C_I2C_MST_NM_INT_MASK_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_MST_NM_INT_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define I2C_I2C_MST_NM_INT_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_MST_NM_INT_MASK_0_READ_MASK                     MK_MASK_CONST(0x1)
#define I2C_I2C_MST_NM_INT_MASK_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_SHIFT                 MK_SHIFT_CONST(0)
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_SHIFT)
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_RANGE                 0:0
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_MSB                   MK_SHIFT_CONST(0)
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_LSB                   MK_SHIFT_CONST(0)
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_WOFFSET                       0x0
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_DEFAULT                       MK_MASK_CONST(0x1)
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_DISABLE                       MK_ENUM_CONST(0)
#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_ENABLE                        MK_ENUM_CONST(1)

// Register I2C_BUS_STATUS_0
#define I2C_BUS_STATUS_0                        MK_ADDR_CONST(0xd0)
#define I2C_BUS_STATUS_0_SECURE                         0x0
#define I2C_BUS_STATUS_0_DUAL                   0x0
#define I2C_BUS_STATUS_0_SCR                    0
#define I2C_BUS_STATUS_0_SCRREG                         0
#define I2C_BUS_STATUS_0_WORD_COUNT                     0x1
#define I2C_BUS_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
#define I2C_BUS_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_SCL_SHIFT                      MK_SHIFT_CONST(2)
#define I2C_BUS_STATUS_0_SCL_FIELD                      MK_FIELD_CONST(0x1, I2C_BUS_STATUS_0_SCL_SHIFT)
#define I2C_BUS_STATUS_0_SCL_RANGE                      2:2
#define I2C_BUS_STATUS_0_SCL_MSB                        MK_SHIFT_CONST(2)
#define I2C_BUS_STATUS_0_SCL_LSB                        MK_SHIFT_CONST(2)
#define I2C_BUS_STATUS_0_SCL_WOFFSET                    0x0
#define I2C_BUS_STATUS_0_SCL_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_SCL_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_SCL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_SCL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_SCL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_SCL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define I2C_BUS_STATUS_0_SDA_SHIFT                      MK_SHIFT_CONST(1)
#define I2C_BUS_STATUS_0_SDA_FIELD                      MK_FIELD_CONST(0x1, I2C_BUS_STATUS_0_SDA_SHIFT)
#define I2C_BUS_STATUS_0_SDA_RANGE                      1:1
#define I2C_BUS_STATUS_0_SDA_MSB                        MK_SHIFT_CONST(1)
#define I2C_BUS_STATUS_0_SDA_LSB                        MK_SHIFT_CONST(1)
#define I2C_BUS_STATUS_0_SDA_WOFFSET                    0x0
#define I2C_BUS_STATUS_0_SDA_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_SDA_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_SDA_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_SDA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_SDA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_SDA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define I2C_BUS_STATUS_0_BUS_BUSY_SHIFT                 MK_SHIFT_CONST(0)
#define I2C_BUS_STATUS_0_BUS_BUSY_FIELD                 MK_FIELD_CONST(0x1, I2C_BUS_STATUS_0_BUS_BUSY_SHIFT)
#define I2C_BUS_STATUS_0_BUS_BUSY_RANGE                 0:0
#define I2C_BUS_STATUS_0_BUS_BUSY_MSB                   MK_SHIFT_CONST(0)
#define I2C_BUS_STATUS_0_BUS_BUSY_LSB                   MK_SHIFT_CONST(0)
#define I2C_BUS_STATUS_0_BUS_BUSY_WOFFSET                       0x0
#define I2C_BUS_STATUS_0_BUS_BUSY_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_BUS_BUSY_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_BUS_BUSY_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_BUS_BUSY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_BUS_BUSY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define I2C_BUS_STATUS_0_BUS_BUSY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define I2C_BUS_STATUS_0_BUS_BUSY_FREE                  MK_ENUM_CONST(0)
#define I2C_BUS_STATUS_0_BUS_BUSY_BUSY                  MK_ENUM_CONST(1)

// Register I2C_I2C_INTERFACE_TIMING_2_0
#define I2C_I2C_INTERFACE_TIMING_2_0                    MK_ADDR_CONST(0xd4)
#define I2C_I2C_INTERFACE_TIMING_2_0_SECURE                     0x0
#define I2C_I2C_INTERFACE_TIMING_2_0_DUAL                       0x0
#define I2C_I2C_INTERFACE_TIMING_2_0_SCR                        0
#define I2C_I2C_INTERFACE_TIMING_2_0_SCRREG                     0
#define I2C_I2C_INTERFACE_TIMING_2_0_WORD_COUNT                         0x1
#define I2C_I2C_INTERFACE_TIMING_2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define I2C_I2C_INTERFACE_TIMING_2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define I2C_I2C_INTERFACE_TIMING_2_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_SHIFT                      MK_SHIFT_CONST(0)
#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_FIELD                      MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_SHIFT)
#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_RANGE                      7:0
#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_MSB                        MK_SHIFT_CONST(7)
#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_LSB                        MK_SHIFT_CONST(0)
#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_WOFFSET                    0x0
#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_DEFAULT                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_DEFAULT_MASK                       MK_MASK_CONST(0xff)
#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT__PROD                      MK_ENUM_CONST(0)

// Register I2C_I2C_HS_INTERFACE_TIMING_2_0
#define I2C_I2C_HS_INTERFACE_TIMING_2_0                 MK_ADDR_CONST(0xd8)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_SECURE                  0x0
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_DUAL                    0x0
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_SCR                     0
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_SCRREG                  0
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_WORD_COUNT                      0x1
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_READ_MASK                       MK_MASK_CONST(0xff)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_SHIFT                        MK_SHIFT_CONST(0)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_FIELD                        MK_FIELD_CONST(0xff, I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_SHIFT)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_RANGE                        7:0
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_MSB                  MK_SHIFT_CONST(7)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_LSB                  MK_SHIFT_CONST(0)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_WOFFSET                      0x0
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT__PROD                        MK_ENUM_CONST(0)

// Register I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0                      MK_ADDR_CONST(0xdc)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_SECURE                       0x0
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_DUAL                         0x0
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_SCR                  0
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_SCRREG                       0
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_WORD_COUNT                   0x1
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_RESET_MASK                   MK_MASK_CONST(0xffff)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_READ_MASK                    MK_MASK_CONST(0xffff)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_WRITE_MASK                   MK_MASK_CONST(0xffff)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SHIFT                   MK_SHIFT_CONST(0)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_FIELD                   MK_FIELD_CONST(0xffff, I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SHIFT)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_RANGE                   15:0
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_MSB                     MK_SHIFT_CONST(15)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_LSB                     MK_SHIFT_CONST(0)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_WOFFSET                 0x0
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_DEFAULT                 MK_MASK_CONST(0x1)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT__PROD                   MK_ENUM_CONST(1)

// Register I2C_I2C_SLV_DATA_CAPTURE_TIMING_0
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0                       MK_ADDR_CONST(0xe0)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_SECURE                        0x0
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_DUAL                  0x0
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_SCR                   0
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_SCRREG                        0
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_WORD_COUNT                    0x1
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_RESET_VAL                     MK_MASK_CONST(0x2)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_RESET_MASK                    MK_MASK_CONST(0xffff)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_READ_MASK                     MK_MASK_CONST(0xffff)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SHIFT                    MK_SHIFT_CONST(0)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_FIELD                    MK_FIELD_CONST(0xffff, I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SHIFT)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_RANGE                    15:0
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_MSB                      MK_SHIFT_CONST(15)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_LSB                      MK_SHIFT_CONST(0)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_WOFFSET                  0x0
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_DEFAULT                  MK_MASK_CONST(0x2)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT__PROD                    MK_ENUM_CONST(2)

// Register I2C_I2C_SPARE_0
#define I2C_I2C_SPARE_0                 MK_ADDR_CONST(0xe4)
#define I2C_I2C_SPARE_0_SECURE                  0x0
#define I2C_I2C_SPARE_0_DUAL                    0x0
#define I2C_I2C_SPARE_0_SCR                     0
#define I2C_I2C_SPARE_0_SCRREG                  0
#define I2C_I2C_SPARE_0_WORD_COUNT                      0x1
#define I2C_I2C_SPARE_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define I2C_I2C_SPARE_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define I2C_I2C_SPARE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define I2C_I2C_SPARE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define I2C_I2C_SPARE_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define I2C_I2C_SPARE_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define I2C_I2C_SPARE_0_ECO_SHIFT                       MK_SHIFT_CONST(0)
#define I2C_I2C_SPARE_0_ECO_FIELD                       MK_FIELD_CONST(0xffffffff, I2C_I2C_SPARE_0_ECO_SHIFT)
#define I2C_I2C_SPARE_0_ECO_RANGE                       31:0
#define I2C_I2C_SPARE_0_ECO_MSB                 MK_SHIFT_CONST(31)
#define I2C_I2C_SPARE_0_ECO_LSB                 MK_SHIFT_CONST(0)
#define I2C_I2C_SPARE_0_ECO_WOFFSET                     0x0
#define I2C_I2C_SPARE_0_ECO_DEFAULT                     MK_MASK_CONST(0x0)
#define I2C_I2C_SPARE_0_ECO_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define I2C_I2C_SPARE_0_ECO_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define I2C_I2C_SPARE_0_ECO_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define I2C_I2C_SPARE_0_ECO_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define I2C_I2C_SPARE_0_ECO_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

//
// REGISTER LIST
//
#define LIST_ARI2C_REGS(_op_) \
_op_(I2C_I2C_CNFG_0) \
_op_(I2C_I2C_CMD_ADDR0_0) \
_op_(I2C_I2C_CMD_ADDR1_0) \
_op_(I2C_I2C_CMD_DATA1_0) \
_op_(I2C_I2C_CMD_DATA2_0) \
_op_(I2C_I2C_STATUS_0) \
_op_(I2C_I2C_SL_CNFG_0) \
_op_(I2C_I2C_SL_RCVD_0) \
_op_(I2C_I2C_SL_STATUS_0) \
_op_(I2C_I2C_SL_ADDR1_0) \
_op_(I2C_I2C_SL_ADDR2_0) \
_op_(I2C_I2C_TLOW_SEXT_0) \
_op_(I2C_I2C_SL_DELAY_COUNT_0) \
_op_(I2C_I2C_SL_INT_MASK_0) \
_op_(I2C_I2C_SL_INT_SOURCE_0) \
_op_(I2C_I2C_SL_INT_SET_0) \
_op_(I2C_I2C_TX_PACKET_FIFO_0) \
_op_(I2C_I2C_RX_FIFO_0) \
_op_(I2C_PACKET_TRANSFER_STATUS_0) \
_op_(I2C_INTERRUPT_MASK_REGISTER_0) \
_op_(I2C_INTERRUPT_STATUS_REGISTER_0) \
_op_(I2C_I2C_CLK_DIVISOR_REGISTER_0) \
_op_(I2C_I2C_INTERRUPT_SOURCE_REGISTER_0) \
_op_(I2C_I2C_INTERRUPT_SET_REGISTER_0) \
_op_(I2C_I2C_SLV_TX_PACKET_FIFO_0) \
_op_(I2C_I2C_SLV_RX_FIFO_0) \
_op_(I2C_I2C_SLV_PACKET_STATUS_0) \
_op_(I2C_I2C_BUS_CLEAR_CONFIG_0) \
_op_(I2C_I2C_BUS_CLEAR_STATUS_0) \
_op_(I2C_I2C_CONFIG_LOAD_0) \
_op_(I2C_I2C_CLKEN_OVERRIDE_0) \
_op_(I2C_I2C_INTERFACE_TIMING_0_0) \
_op_(I2C_I2C_INTERFACE_TIMING_1_0) \
_op_(I2C_I2C_HS_INTERFACE_TIMING_0_0) \
_op_(I2C_I2C_HS_INTERFACE_TIMING_1_0) \
_op_(I2C_I2C_MASTER_RESET_CNTRL_0) \
_op_(I2C_I2C_SLV_RESET_CNTRL_0) \
_op_(I2C_MST_PACKET_TRANSFER_CNT_STATUS_0) \
_op_(I2C_MST_FIFO_CONTROL_0) \
_op_(I2C_MST_FIFO_STATUS_0) \
_op_(I2C_SLV_PAYLOAD_0) \
_op_(I2C_SLV_FIFO_CONTROL_0) \
_op_(I2C_SLV_FIFO_STATUS_0) \
_op_(I2C_I2C_MST_NM_INT_STATUS_0) \
_op_(I2C_I2C_MST_NM_INT_MASK_0) \
_op_(I2C_BUS_STATUS_0) \
_op_(I2C_I2C_INTERFACE_TIMING_2_0) \
_op_(I2C_I2C_HS_INTERFACE_TIMING_2_0) \
_op_(I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0) \
_op_(I2C_I2C_SLV_DATA_CAPTURE_TIMING_0) \
_op_(I2C_I2C_SPARE_0)

//
// ADDRESS SPACES
//

#define BASE_ADDRESS_I2C        0x00000000

//
// ARI2C REGISTER BANKS
//

#define I2C0_FIRST_REG 0x0000 // I2C_I2C_CNFG_0
#define I2C0_LAST_REG 0x0010 // I2C_I2C_CMD_DATA2_0
#define I2C1_FIRST_REG 0x001c // I2C_I2C_STATUS_0
#define I2C1_LAST_REG 0x0034 // I2C_I2C_TLOW_SEXT_0
#define I2C2_FIRST_REG 0x003c // I2C_I2C_SL_DELAY_COUNT_0
#define I2C2_LAST_REG 0x0048 // I2C_I2C_SL_INT_SET_0
#define I2C3_FIRST_REG 0x0050 // I2C_I2C_TX_PACKET_FIFO_0
#define I2C3_LAST_REG 0x00e4 // I2C_I2C_SPARE_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARI2C_H_INC
