//
// Copyright (c) 2021 NVIDIA Corporation.
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
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// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// POSSIBILITY OF SUCH DAMAGE.
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//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARAPS_VIC_H_INC
#define ARAPS_VIC_H_INC
#define NV_MOBILE_ARAPS_VIC_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARAPS_VIC_H_SCRREG_NOMENCLATURE INFERRED


// Register APS_VIC_VICIRQSTATUS_0
#define APS_VIC_VICIRQSTATUS_0                  MK_ADDR_CONST(0x0)
#define APS_VIC_VICIRQSTATUS_0_SECURE                   0x0
#define APS_VIC_VICIRQSTATUS_0_DUAL                     0x0
#define APS_VIC_VICIRQSTATUS_0_SCR                      0
#define APS_VIC_VICIRQSTATUS_0_SCRREG                   0
#define APS_VIC_VICIRQSTATUS_0_WORD_COUNT                       0x1
#define APS_VIC_VICIRQSTATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICIRQSTATUS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICIRQSTATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICIRQSTATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICIRQSTATUS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICIRQSTATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_SHIFT)
#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_RANGE                       31:0
#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_WOFFSET                     0x0
#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICFIQSTATUS_0
#define APS_VIC_VICFIQSTATUS_0                  MK_ADDR_CONST(0x4)
#define APS_VIC_VICFIQSTATUS_0_SECURE                   0x0
#define APS_VIC_VICFIQSTATUS_0_DUAL                     0x0
#define APS_VIC_VICFIQSTATUS_0_SCR                      0
#define APS_VIC_VICFIQSTATUS_0_SCRREG                   0
#define APS_VIC_VICFIQSTATUS_0_WORD_COUNT                       0x1
#define APS_VIC_VICFIQSTATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICFIQSTATUS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICFIQSTATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICFIQSTATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICFIQSTATUS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICFIQSTATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_SHIFT)
#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_RANGE                       31:0
#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_WOFFSET                     0x0
#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICRAWINTR_0
#define APS_VIC_VICRAWINTR_0                    MK_ADDR_CONST(0x8)
#define APS_VIC_VICRAWINTR_0_SECURE                     0x0
#define APS_VIC_VICRAWINTR_0_DUAL                       0x0
#define APS_VIC_VICRAWINTR_0_SCR                        0
#define APS_VIC_VICRAWINTR_0_SCRREG                     0
#define APS_VIC_VICRAWINTR_0_WORD_COUNT                         0x1
#define APS_VIC_VICRAWINTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICRAWINTR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICRAWINTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define APS_VIC_VICRAWINTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_VIC_VICRAWINTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICRAWINTR_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICRAWINTR_0_VICRAWINTR_SHIFT                   MK_SHIFT_CONST(0)
#define APS_VIC_VICRAWINTR_0_VICRAWINTR_FIELD                   MK_FIELD_CONST(0xffffffff, APS_VIC_VICRAWINTR_0_VICRAWINTR_SHIFT)
#define APS_VIC_VICRAWINTR_0_VICRAWINTR_RANGE                   31:0
#define APS_VIC_VICRAWINTR_0_VICRAWINTR_MSB                     MK_SHIFT_CONST(31)
#define APS_VIC_VICRAWINTR_0_VICRAWINTR_LSB                     MK_SHIFT_CONST(0)
#define APS_VIC_VICRAWINTR_0_VICRAWINTR_WOFFSET                 0x0
#define APS_VIC_VICRAWINTR_0_VICRAWINTR_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_VIC_VICRAWINTR_0_VICRAWINTR_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_VIC_VICRAWINTR_0_VICRAWINTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_VIC_VICRAWINTR_0_VICRAWINTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_VIC_VICRAWINTR_0_VICRAWINTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_VIC_VICRAWINTR_0_VICRAWINTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_VIC_VICINTSELECT_0
#define APS_VIC_VICINTSELECT_0                  MK_ADDR_CONST(0xc)
#define APS_VIC_VICINTSELECT_0_SECURE                   0x0
#define APS_VIC_VICINTSELECT_0_DUAL                     0x0
#define APS_VIC_VICINTSELECT_0_SCR                      0
#define APS_VIC_VICINTSELECT_0_SCRREG                   0
#define APS_VIC_VICINTSELECT_0_WORD_COUNT                       0x1
#define APS_VIC_VICINTSELECT_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSELECT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICINTSELECT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSELECT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSELECT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICINTSELECT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICINTSELECT_0_VICINTSELECT_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICINTSELECT_0_VICINTSELECT_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICINTSELECT_0_VICINTSELECT_SHIFT)
#define APS_VIC_VICINTSELECT_0_VICINTSELECT_RANGE                       31:0
#define APS_VIC_VICINTSELECT_0_VICINTSELECT_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICINTSELECT_0_VICINTSELECT_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICINTSELECT_0_VICINTSELECT_WOFFSET                     0x0
#define APS_VIC_VICINTSELECT_0_VICINTSELECT_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSELECT_0_VICINTSELECT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICINTSELECT_0_VICINTSELECT_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSELECT_0_VICINTSELECT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSELECT_0_VICINTSELECT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSELECT_0_VICINTSELECT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICINTENABLE_0
#define APS_VIC_VICINTENABLE_0                  MK_ADDR_CONST(0x10)
#define APS_VIC_VICINTENABLE_0_SECURE                   0x0
#define APS_VIC_VICINTENABLE_0_DUAL                     0x0
#define APS_VIC_VICINTENABLE_0_SCR                      0
#define APS_VIC_VICINTENABLE_0_SCRREG                   0
#define APS_VIC_VICINTENABLE_0_WORD_COUNT                       0x1
#define APS_VIC_VICINTENABLE_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENABLE_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICINTENABLE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENABLE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENABLE_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICINTENABLE_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICINTENABLE_0_VICINTENABLE_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICINTENABLE_0_VICINTENABLE_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICINTENABLE_0_VICINTENABLE_SHIFT)
#define APS_VIC_VICINTENABLE_0_VICINTENABLE_RANGE                       31:0
#define APS_VIC_VICINTENABLE_0_VICINTENABLE_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICINTENABLE_0_VICINTENABLE_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICINTENABLE_0_VICINTENABLE_WOFFSET                     0x0
#define APS_VIC_VICINTENABLE_0_VICINTENABLE_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENABLE_0_VICINTENABLE_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICINTENABLE_0_VICINTENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENABLE_0_VICINTENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENABLE_0_VICINTENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENABLE_0_VICINTENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICINTENCLEAR_0
#define APS_VIC_VICINTENCLEAR_0                 MK_ADDR_CONST(0x14)
#define APS_VIC_VICINTENCLEAR_0_SECURE                  0x0
#define APS_VIC_VICINTENCLEAR_0_DUAL                    0x0
#define APS_VIC_VICINTENCLEAR_0_SCR                     0
#define APS_VIC_VICINTENCLEAR_0_SCRREG                  0
#define APS_VIC_VICINTENCLEAR_0_WORD_COUNT                      0x1
#define APS_VIC_VICINTENCLEAR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENCLEAR_0_RESET_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENCLEAR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENCLEAR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENCLEAR_0_READ_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENCLEAR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_SHIFT)
#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_RANGE                     31:0
#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_WOFFSET                   0x0
#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICSOFTINT_0
#define APS_VIC_VICSOFTINT_0                    MK_ADDR_CONST(0x18)
#define APS_VIC_VICSOFTINT_0_SECURE                     0x0
#define APS_VIC_VICSOFTINT_0_DUAL                       0x0
#define APS_VIC_VICSOFTINT_0_SCR                        0
#define APS_VIC_VICSOFTINT_0_SCRREG                     0
#define APS_VIC_VICSOFTINT_0_WORD_COUNT                         0x1
#define APS_VIC_VICSOFTINT_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICSOFTINT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICSOFTINT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICSOFTINT_0_VICSOFTINT_SHIFT                   MK_SHIFT_CONST(0)
#define APS_VIC_VICSOFTINT_0_VICSOFTINT_FIELD                   MK_FIELD_CONST(0xffffffff, APS_VIC_VICSOFTINT_0_VICSOFTINT_SHIFT)
#define APS_VIC_VICSOFTINT_0_VICSOFTINT_RANGE                   31:0
#define APS_VIC_VICSOFTINT_0_VICSOFTINT_MSB                     MK_SHIFT_CONST(31)
#define APS_VIC_VICSOFTINT_0_VICSOFTINT_LSB                     MK_SHIFT_CONST(0)
#define APS_VIC_VICSOFTINT_0_VICSOFTINT_WOFFSET                 0x0
#define APS_VIC_VICSOFTINT_0_VICSOFTINT_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINT_0_VICSOFTINT_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICSOFTINT_0_VICSOFTINT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINT_0_VICSOFTINT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINT_0_VICSOFTINT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINT_0_VICSOFTINT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register APS_VIC_VICSOFTINTCLEAR_0
#define APS_VIC_VICSOFTINTCLEAR_0                       MK_ADDR_CONST(0x1c)
#define APS_VIC_VICSOFTINTCLEAR_0_SECURE                        0x0
#define APS_VIC_VICSOFTINTCLEAR_0_DUAL                  0x0
#define APS_VIC_VICSOFTINTCLEAR_0_SCR                   0
#define APS_VIC_VICSOFTINTCLEAR_0_SCRREG                        0
#define APS_VIC_VICSOFTINTCLEAR_0_WORD_COUNT                    0x1
#define APS_VIC_VICSOFTINTCLEAR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINTCLEAR_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINTCLEAR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINTCLEAR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINTCLEAR_0_READ_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINTCLEAR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_FIELD                 MK_FIELD_CONST(0xffffffff, APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_SHIFT)
#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_RANGE                 31:0
#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_MSB                   MK_SHIFT_CONST(31)
#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_LSB                   MK_SHIFT_CONST(0)
#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_WOFFSET                       0x0
#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register APS_VIC_VICPROTECTION_0
#define APS_VIC_VICPROTECTION_0                 MK_ADDR_CONST(0x20)
#define APS_VIC_VICPROTECTION_0_SECURE                  0x0
#define APS_VIC_VICPROTECTION_0_DUAL                    0x0
#define APS_VIC_VICPROTECTION_0_SCR                     0
#define APS_VIC_VICPROTECTION_0_SCRREG                  0
#define APS_VIC_VICPROTECTION_0_WORD_COUNT                      0x1
#define APS_VIC_VICPROTECTION_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICPROTECTION_0_RESET_MASK                      MK_MASK_CONST(0x1)
#define APS_VIC_VICPROTECTION_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICPROTECTION_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICPROTECTION_0_READ_MASK                       MK_MASK_CONST(0x1)
#define APS_VIC_VICPROTECTION_0_WRITE_MASK                      MK_MASK_CONST(0x1)
#define APS_VIC_VICPROTECTION_0_VICPROTECTION_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICPROTECTION_0_VICPROTECTION_FIELD                     MK_FIELD_CONST(0x1, APS_VIC_VICPROTECTION_0_VICPROTECTION_SHIFT)
#define APS_VIC_VICPROTECTION_0_VICPROTECTION_RANGE                     0:0
#define APS_VIC_VICPROTECTION_0_VICPROTECTION_MSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICPROTECTION_0_VICPROTECTION_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICPROTECTION_0_VICPROTECTION_WOFFSET                   0x0
#define APS_VIC_VICPROTECTION_0_VICPROTECTION_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPROTECTION_0_VICPROTECTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_VIC_VICPROTECTION_0_VICPROTECTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICPROTECTION_0_VICPROTECTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPROTECTION_0_VICPROTECTION_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICPROTECTION_0_VICPROTECTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define APS_VIC_VICPROTECTION_0_VICPROTECTION__PROD                     MK_ENUM_CONST(1)


// Register APS_VIC_VICSWPRIORITY_0
#define APS_VIC_VICSWPRIORITY_0                 MK_ADDR_CONST(0x24)
#define APS_VIC_VICSWPRIORITY_0_SECURE                  0x0
#define APS_VIC_VICSWPRIORITY_0_DUAL                    0x0
#define APS_VIC_VICSWPRIORITY_0_SCR                     0
#define APS_VIC_VICSWPRIORITY_0_SCRREG                  0
#define APS_VIC_VICSWPRIORITY_0_WORD_COUNT                      0x1
#define APS_VIC_VICSWPRIORITY_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define APS_VIC_VICSWPRIORITY_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define APS_VIC_VICSWPRIORITY_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICSWPRIORITY_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICSWPRIORITY_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define APS_VIC_VICSWPRIORITY_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_FIELD                     MK_FIELD_CONST(0xffff, APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_SHIFT)
#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_RANGE                     15:0
#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_MSB                       MK_SHIFT_CONST(15)
#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_WOFFSET                   0x0
#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_DEFAULT                   MK_MASK_CONST(0xffff)
#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICPRIORITYDAISY_0
#define APS_VIC_VICPRIORITYDAISY_0                      MK_ADDR_CONST(0x28)
#define APS_VIC_VICPRIORITYDAISY_0_SECURE                       0x0
#define APS_VIC_VICPRIORITYDAISY_0_DUAL                         0x0
#define APS_VIC_VICPRIORITYDAISY_0_SCR                  0
#define APS_VIC_VICPRIORITYDAISY_0_SCRREG                       0
#define APS_VIC_VICPRIORITYDAISY_0_WORD_COUNT                   0x1
#define APS_VIC_VICPRIORITYDAISY_0_RESET_VAL                    MK_MASK_CONST(0xf)
#define APS_VIC_VICPRIORITYDAISY_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICPRIORITYDAISY_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICPRIORITYDAISY_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICPRIORITYDAISY_0_READ_MASK                    MK_MASK_CONST(0xf)
#define APS_VIC_VICPRIORITYDAISY_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_SHIFT)
#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_RANGE                       3:0
#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_MSB                 MK_SHIFT_CONST(3)
#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_WOFFSET                     0x0
#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_DEFAULT                     MK_MASK_CONST(0xf)
#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x2c

// Reserved address 0x30

// Reserved address 0x34

// Reserved address 0x38

// Reserved address 0x3c

// Reserved address 0x40

// Reserved address 0x44

// Reserved address 0x48

// Reserved address 0x4c

// Reserved address 0x50

// Reserved address 0x54

// Reserved address 0x58

// Reserved address 0x5c

// Reserved address 0x60

// Reserved address 0x64

// Reserved address 0x68

// Reserved address 0x6c

// Reserved address 0x70

// Reserved address 0x74

// Reserved address 0x78

// Reserved address 0x7c

// Reserved address 0x80

// Reserved address 0x84

// Reserved address 0x88

// Reserved address 0x8c

// Reserved address 0x90

// Reserved address 0x94

// Reserved address 0x98

// Reserved address 0x9c

// Reserved address 0xa0

// Reserved address 0xa4

// Reserved address 0xa8

// Reserved address 0xac

// Reserved address 0xb0

// Reserved address 0xb4

// Reserved address 0xb8

// Reserved address 0xbc

// Reserved address 0xc0

// Reserved address 0xc4

// Reserved address 0xc8

// Reserved address 0xcc

// Reserved address 0xd0

// Reserved address 0xd4

// Reserved address 0xd8

// Reserved address 0xdc

// Reserved address 0xe0

// Reserved address 0xe4

// Reserved address 0xe8

// Reserved address 0xec

// Reserved address 0xf0

// Reserved address 0xf4

// Reserved address 0xf8

// Reserved address 0xfc

// Register APS_VIC_VICVECTADDR0_0
#define APS_VIC_VICVECTADDR0_0                  MK_ADDR_CONST(0x100)
#define APS_VIC_VICVECTADDR0_0_SECURE                   0x0
#define APS_VIC_VICVECTADDR0_0_DUAL                     0x0
#define APS_VIC_VICVECTADDR0_0_SCR                      0
#define APS_VIC_VICVECTADDR0_0_SCRREG                   0
#define APS_VIC_VICVECTADDR0_0_WORD_COUNT                       0x1
#define APS_VIC_VICVECTADDR0_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR0_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR0_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR0_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR0_0_VICVECTADDR0_SHIFT)
#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_RANGE                       31:0
#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_WOFFSET                     0x0
#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR1_0
#define APS_VIC_VICVECTADDR1_0                  MK_ADDR_CONST(0x104)
#define APS_VIC_VICVECTADDR1_0_SECURE                   0x0
#define APS_VIC_VICVECTADDR1_0_DUAL                     0x0
#define APS_VIC_VICVECTADDR1_0_SCR                      0
#define APS_VIC_VICVECTADDR1_0_SCRREG                   0
#define APS_VIC_VICVECTADDR1_0_WORD_COUNT                       0x1
#define APS_VIC_VICVECTADDR1_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR1_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR1_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR1_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR1_0_VICVECTADDR1_SHIFT)
#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_RANGE                       31:0
#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_WOFFSET                     0x0
#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR2_0
#define APS_VIC_VICVECTADDR2_0                  MK_ADDR_CONST(0x108)
#define APS_VIC_VICVECTADDR2_0_SECURE                   0x0
#define APS_VIC_VICVECTADDR2_0_DUAL                     0x0
#define APS_VIC_VICVECTADDR2_0_SCR                      0
#define APS_VIC_VICVECTADDR2_0_SCRREG                   0
#define APS_VIC_VICVECTADDR2_0_WORD_COUNT                       0x1
#define APS_VIC_VICVECTADDR2_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR2_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR2_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR2_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR2_0_VICVECTADDR2_SHIFT)
#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_RANGE                       31:0
#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_WOFFSET                     0x0
#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR3_0
#define APS_VIC_VICVECTADDR3_0                  MK_ADDR_CONST(0x10c)
#define APS_VIC_VICVECTADDR3_0_SECURE                   0x0
#define APS_VIC_VICVECTADDR3_0_DUAL                     0x0
#define APS_VIC_VICVECTADDR3_0_SCR                      0
#define APS_VIC_VICVECTADDR3_0_SCRREG                   0
#define APS_VIC_VICVECTADDR3_0_WORD_COUNT                       0x1
#define APS_VIC_VICVECTADDR3_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR3_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR3_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR3_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR3_0_VICVECTADDR3_SHIFT)
#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_RANGE                       31:0
#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_WOFFSET                     0x0
#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR4_0
#define APS_VIC_VICVECTADDR4_0                  MK_ADDR_CONST(0x110)
#define APS_VIC_VICVECTADDR4_0_SECURE                   0x0
#define APS_VIC_VICVECTADDR4_0_DUAL                     0x0
#define APS_VIC_VICVECTADDR4_0_SCR                      0
#define APS_VIC_VICVECTADDR4_0_SCRREG                   0
#define APS_VIC_VICVECTADDR4_0_WORD_COUNT                       0x1
#define APS_VIC_VICVECTADDR4_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR4_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR4_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR4_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR4_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR4_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR4_0_VICVECTADDR4_SHIFT)
#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_RANGE                       31:0
#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_WOFFSET                     0x0
#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR5_0
#define APS_VIC_VICVECTADDR5_0                  MK_ADDR_CONST(0x114)
#define APS_VIC_VICVECTADDR5_0_SECURE                   0x0
#define APS_VIC_VICVECTADDR5_0_DUAL                     0x0
#define APS_VIC_VICVECTADDR5_0_SCR                      0
#define APS_VIC_VICVECTADDR5_0_SCRREG                   0
#define APS_VIC_VICVECTADDR5_0_WORD_COUNT                       0x1
#define APS_VIC_VICVECTADDR5_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR5_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR5_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR5_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR5_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR5_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR5_0_VICVECTADDR5_SHIFT)
#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_RANGE                       31:0
#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_WOFFSET                     0x0
#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR6_0
#define APS_VIC_VICVECTADDR6_0                  MK_ADDR_CONST(0x118)
#define APS_VIC_VICVECTADDR6_0_SECURE                   0x0
#define APS_VIC_VICVECTADDR6_0_DUAL                     0x0
#define APS_VIC_VICVECTADDR6_0_SCR                      0
#define APS_VIC_VICVECTADDR6_0_SCRREG                   0
#define APS_VIC_VICVECTADDR6_0_WORD_COUNT                       0x1
#define APS_VIC_VICVECTADDR6_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR6_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR6_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR6_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR6_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR6_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR6_0_VICVECTADDR6_SHIFT)
#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_RANGE                       31:0
#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_WOFFSET                     0x0
#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR7_0
#define APS_VIC_VICVECTADDR7_0                  MK_ADDR_CONST(0x11c)
#define APS_VIC_VICVECTADDR7_0_SECURE                   0x0
#define APS_VIC_VICVECTADDR7_0_DUAL                     0x0
#define APS_VIC_VICVECTADDR7_0_SCR                      0
#define APS_VIC_VICVECTADDR7_0_SCRREG                   0
#define APS_VIC_VICVECTADDR7_0_WORD_COUNT                       0x1
#define APS_VIC_VICVECTADDR7_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR7_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR7_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR7_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR7_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR7_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR7_0_VICVECTADDR7_SHIFT)
#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_RANGE                       31:0
#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_WOFFSET                     0x0
#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR8_0
#define APS_VIC_VICVECTADDR8_0                  MK_ADDR_CONST(0x120)
#define APS_VIC_VICVECTADDR8_0_SECURE                   0x0
#define APS_VIC_VICVECTADDR8_0_DUAL                     0x0
#define APS_VIC_VICVECTADDR8_0_SCR                      0
#define APS_VIC_VICVECTADDR8_0_SCRREG                   0
#define APS_VIC_VICVECTADDR8_0_WORD_COUNT                       0x1
#define APS_VIC_VICVECTADDR8_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR8_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR8_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR8_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR8_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR8_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR8_0_VICVECTADDR8_SHIFT)
#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_RANGE                       31:0
#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_WOFFSET                     0x0
#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR9_0
#define APS_VIC_VICVECTADDR9_0                  MK_ADDR_CONST(0x124)
#define APS_VIC_VICVECTADDR9_0_SECURE                   0x0
#define APS_VIC_VICVECTADDR9_0_DUAL                     0x0
#define APS_VIC_VICVECTADDR9_0_SCR                      0
#define APS_VIC_VICVECTADDR9_0_SCRREG                   0
#define APS_VIC_VICVECTADDR9_0_WORD_COUNT                       0x1
#define APS_VIC_VICVECTADDR9_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR9_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR9_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR9_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR9_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR9_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR9_0_VICVECTADDR9_SHIFT)
#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_RANGE                       31:0
#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_MSB                 MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_WOFFSET                     0x0
#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR10_0
#define APS_VIC_VICVECTADDR10_0                 MK_ADDR_CONST(0x128)
#define APS_VIC_VICVECTADDR10_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR10_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR10_0_SCR                     0
#define APS_VIC_VICVECTADDR10_0_SCRREG                  0
#define APS_VIC_VICVECTADDR10_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR10_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR10_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR10_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR10_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR10_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR10_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR10_0_VICVECTADDR10_SHIFT)
#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_RANGE                     31:0
#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR11_0
#define APS_VIC_VICVECTADDR11_0                 MK_ADDR_CONST(0x12c)
#define APS_VIC_VICVECTADDR11_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR11_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR11_0_SCR                     0
#define APS_VIC_VICVECTADDR11_0_SCRREG                  0
#define APS_VIC_VICVECTADDR11_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR11_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR11_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR11_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR11_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR11_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR11_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR11_0_VICVECTADDR11_SHIFT)
#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_RANGE                     31:0
#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR12_0
#define APS_VIC_VICVECTADDR12_0                 MK_ADDR_CONST(0x130)
#define APS_VIC_VICVECTADDR12_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR12_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR12_0_SCR                     0
#define APS_VIC_VICVECTADDR12_0_SCRREG                  0
#define APS_VIC_VICVECTADDR12_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR12_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR12_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR12_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR12_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR12_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR12_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR12_0_VICVECTADDR12_SHIFT)
#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_RANGE                     31:0
#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR13_0
#define APS_VIC_VICVECTADDR13_0                 MK_ADDR_CONST(0x134)
#define APS_VIC_VICVECTADDR13_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR13_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR13_0_SCR                     0
#define APS_VIC_VICVECTADDR13_0_SCRREG                  0
#define APS_VIC_VICVECTADDR13_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR13_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR13_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR13_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR13_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR13_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR13_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR13_0_VICVECTADDR13_SHIFT)
#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_RANGE                     31:0
#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR14_0
#define APS_VIC_VICVECTADDR14_0                 MK_ADDR_CONST(0x138)
#define APS_VIC_VICVECTADDR14_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR14_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR14_0_SCR                     0
#define APS_VIC_VICVECTADDR14_0_SCRREG                  0
#define APS_VIC_VICVECTADDR14_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR14_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR14_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR14_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR14_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR14_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR14_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR14_0_VICVECTADDR14_SHIFT)
#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_RANGE                     31:0
#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR15_0
#define APS_VIC_VICVECTADDR15_0                 MK_ADDR_CONST(0x13c)
#define APS_VIC_VICVECTADDR15_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR15_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR15_0_SCR                     0
#define APS_VIC_VICVECTADDR15_0_SCRREG                  0
#define APS_VIC_VICVECTADDR15_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR15_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR15_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR15_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR15_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR15_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR15_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR15_0_VICVECTADDR15_SHIFT)
#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_RANGE                     31:0
#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR16_0
#define APS_VIC_VICVECTADDR16_0                 MK_ADDR_CONST(0x140)
#define APS_VIC_VICVECTADDR16_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR16_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR16_0_SCR                     0
#define APS_VIC_VICVECTADDR16_0_SCRREG                  0
#define APS_VIC_VICVECTADDR16_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR16_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR16_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR16_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR16_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR16_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR16_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR16_0_VICVECTADDR16_SHIFT)
#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_RANGE                     31:0
#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR17_0
#define APS_VIC_VICVECTADDR17_0                 MK_ADDR_CONST(0x144)
#define APS_VIC_VICVECTADDR17_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR17_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR17_0_SCR                     0
#define APS_VIC_VICVECTADDR17_0_SCRREG                  0
#define APS_VIC_VICVECTADDR17_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR17_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR17_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR17_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR17_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR17_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR17_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR17_0_VICVECTADDR17_SHIFT)
#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_RANGE                     31:0
#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR18_0
#define APS_VIC_VICVECTADDR18_0                 MK_ADDR_CONST(0x148)
#define APS_VIC_VICVECTADDR18_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR18_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR18_0_SCR                     0
#define APS_VIC_VICVECTADDR18_0_SCRREG                  0
#define APS_VIC_VICVECTADDR18_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR18_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR18_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR18_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR18_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR18_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR18_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR18_0_VICVECTADDR18_SHIFT)
#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_RANGE                     31:0
#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR19_0
#define APS_VIC_VICVECTADDR19_0                 MK_ADDR_CONST(0x14c)
#define APS_VIC_VICVECTADDR19_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR19_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR19_0_SCR                     0
#define APS_VIC_VICVECTADDR19_0_SCRREG                  0
#define APS_VIC_VICVECTADDR19_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR19_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR19_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR19_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR19_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR19_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR19_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR19_0_VICVECTADDR19_SHIFT)
#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_RANGE                     31:0
#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR20_0
#define APS_VIC_VICVECTADDR20_0                 MK_ADDR_CONST(0x150)
#define APS_VIC_VICVECTADDR20_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR20_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR20_0_SCR                     0
#define APS_VIC_VICVECTADDR20_0_SCRREG                  0
#define APS_VIC_VICVECTADDR20_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR20_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR20_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR20_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR20_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR20_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR20_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR20_0_VICVECTADDR20_SHIFT)
#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_RANGE                     31:0
#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR21_0
#define APS_VIC_VICVECTADDR21_0                 MK_ADDR_CONST(0x154)
#define APS_VIC_VICVECTADDR21_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR21_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR21_0_SCR                     0
#define APS_VIC_VICVECTADDR21_0_SCRREG                  0
#define APS_VIC_VICVECTADDR21_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR21_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR21_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR21_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR21_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR21_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR21_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR21_0_VICVECTADDR21_SHIFT)
#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_RANGE                     31:0
#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR22_0
#define APS_VIC_VICVECTADDR22_0                 MK_ADDR_CONST(0x158)
#define APS_VIC_VICVECTADDR22_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR22_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR22_0_SCR                     0
#define APS_VIC_VICVECTADDR22_0_SCRREG                  0
#define APS_VIC_VICVECTADDR22_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR22_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR22_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR22_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR22_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR22_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR22_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR22_0_VICVECTADDR22_SHIFT)
#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_RANGE                     31:0
#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR23_0
#define APS_VIC_VICVECTADDR23_0                 MK_ADDR_CONST(0x15c)
#define APS_VIC_VICVECTADDR23_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR23_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR23_0_SCR                     0
#define APS_VIC_VICVECTADDR23_0_SCRREG                  0
#define APS_VIC_VICVECTADDR23_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR23_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR23_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR23_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR23_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR23_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR23_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR23_0_VICVECTADDR23_SHIFT)
#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_RANGE                     31:0
#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR24_0
#define APS_VIC_VICVECTADDR24_0                 MK_ADDR_CONST(0x160)
#define APS_VIC_VICVECTADDR24_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR24_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR24_0_SCR                     0
#define APS_VIC_VICVECTADDR24_0_SCRREG                  0
#define APS_VIC_VICVECTADDR24_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR24_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR24_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR24_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR24_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR24_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR24_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR24_0_VICVECTADDR24_SHIFT)
#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_RANGE                     31:0
#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR25_0
#define APS_VIC_VICVECTADDR25_0                 MK_ADDR_CONST(0x164)
#define APS_VIC_VICVECTADDR25_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR25_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR25_0_SCR                     0
#define APS_VIC_VICVECTADDR25_0_SCRREG                  0
#define APS_VIC_VICVECTADDR25_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR25_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR25_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR25_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR25_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR25_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR25_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR25_0_VICVECTADDR25_SHIFT)
#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_RANGE                     31:0
#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR26_0
#define APS_VIC_VICVECTADDR26_0                 MK_ADDR_CONST(0x168)
#define APS_VIC_VICVECTADDR26_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR26_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR26_0_SCR                     0
#define APS_VIC_VICVECTADDR26_0_SCRREG                  0
#define APS_VIC_VICVECTADDR26_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR26_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR26_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR26_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR26_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR26_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR26_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR26_0_VICVECTADDR26_SHIFT)
#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_RANGE                     31:0
#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR27_0
#define APS_VIC_VICVECTADDR27_0                 MK_ADDR_CONST(0x16c)
#define APS_VIC_VICVECTADDR27_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR27_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR27_0_SCR                     0
#define APS_VIC_VICVECTADDR27_0_SCRREG                  0
#define APS_VIC_VICVECTADDR27_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR27_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR27_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR27_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR27_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR27_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR27_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR27_0_VICVECTADDR27_SHIFT)
#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_RANGE                     31:0
#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR28_0
#define APS_VIC_VICVECTADDR28_0                 MK_ADDR_CONST(0x170)
#define APS_VIC_VICVECTADDR28_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR28_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR28_0_SCR                     0
#define APS_VIC_VICVECTADDR28_0_SCRREG                  0
#define APS_VIC_VICVECTADDR28_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR28_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR28_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR28_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR28_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR28_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR28_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR28_0_VICVECTADDR28_SHIFT)
#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_RANGE                     31:0
#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR29_0
#define APS_VIC_VICVECTADDR29_0                 MK_ADDR_CONST(0x174)
#define APS_VIC_VICVECTADDR29_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR29_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR29_0_SCR                     0
#define APS_VIC_VICVECTADDR29_0_SCRREG                  0
#define APS_VIC_VICVECTADDR29_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR29_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR29_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR29_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR29_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR29_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR29_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR29_0_VICVECTADDR29_SHIFT)
#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_RANGE                     31:0
#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR30_0
#define APS_VIC_VICVECTADDR30_0                 MK_ADDR_CONST(0x178)
#define APS_VIC_VICVECTADDR30_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR30_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR30_0_SCR                     0
#define APS_VIC_VICVECTADDR30_0_SCRREG                  0
#define APS_VIC_VICVECTADDR30_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR30_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR30_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR30_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR30_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR30_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR30_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR30_0_VICVECTADDR30_SHIFT)
#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_RANGE                     31:0
#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTADDR31_0
#define APS_VIC_VICVECTADDR31_0                 MK_ADDR_CONST(0x17c)
#define APS_VIC_VICVECTADDR31_0_SECURE                  0x0
#define APS_VIC_VICVECTADDR31_0_DUAL                    0x0
#define APS_VIC_VICVECTADDR31_0_SCR                     0
#define APS_VIC_VICVECTADDR31_0_SCRREG                  0
#define APS_VIC_VICVECTADDR31_0_WORD_COUNT                      0x1
#define APS_VIC_VICVECTADDR31_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR31_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR31_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR31_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR31_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR31_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR31_0_VICVECTADDR31_SHIFT)
#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_RANGE                     31:0
#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_MSB                       MK_SHIFT_CONST(31)
#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_WOFFSET                   0x0
#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x180

// Reserved address 0x184

// Reserved address 0x188

// Reserved address 0x18c

// Reserved address 0x190

// Reserved address 0x194

// Reserved address 0x198

// Reserved address 0x19c

// Reserved address 0x1a0

// Reserved address 0x1a4

// Reserved address 0x1a8

// Reserved address 0x1ac

// Reserved address 0x1b0

// Reserved address 0x1b4

// Reserved address 0x1b8

// Reserved address 0x1bc

// Reserved address 0x1c0

// Reserved address 0x1c4

// Reserved address 0x1c8

// Reserved address 0x1cc

// Reserved address 0x1d0

// Reserved address 0x1d4

// Reserved address 0x1d8

// Reserved address 0x1dc

// Reserved address 0x1e0

// Reserved address 0x1e4

// Reserved address 0x1e8

// Reserved address 0x1ec

// Reserved address 0x1f0

// Reserved address 0x1f4

// Reserved address 0x1f8

// Reserved address 0x1fc

// Register APS_VIC_VICVECTPRIORITY0_0
#define APS_VIC_VICVECTPRIORITY0_0                      MK_ADDR_CONST(0x200)
#define APS_VIC_VICVECTPRIORITY0_0_SECURE                       0x0
#define APS_VIC_VICVECTPRIORITY0_0_DUAL                         0x0
#define APS_VIC_VICVECTPRIORITY0_0_SCR                  0
#define APS_VIC_VICVECTPRIORITY0_0_SCRREG                       0
#define APS_VIC_VICVECTPRIORITY0_0_WORD_COUNT                   0x1
#define APS_VIC_VICVECTPRIORITY0_0_RESET_VAL                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY0_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY0_0_READ_MASK                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY0_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_SHIFT)
#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_RANGE                       3:0
#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_MSB                 MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_WOFFSET                     0x0
#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_DEFAULT                     MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY1_0
#define APS_VIC_VICVECTPRIORITY1_0                      MK_ADDR_CONST(0x204)
#define APS_VIC_VICVECTPRIORITY1_0_SECURE                       0x0
#define APS_VIC_VICVECTPRIORITY1_0_DUAL                         0x0
#define APS_VIC_VICVECTPRIORITY1_0_SCR                  0
#define APS_VIC_VICVECTPRIORITY1_0_SCRREG                       0
#define APS_VIC_VICVECTPRIORITY1_0_WORD_COUNT                   0x1
#define APS_VIC_VICVECTPRIORITY1_0_RESET_VAL                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY1_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY1_0_READ_MASK                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY1_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_SHIFT)
#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_RANGE                       3:0
#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_MSB                 MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_WOFFSET                     0x0
#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_DEFAULT                     MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY2_0
#define APS_VIC_VICVECTPRIORITY2_0                      MK_ADDR_CONST(0x208)
#define APS_VIC_VICVECTPRIORITY2_0_SECURE                       0x0
#define APS_VIC_VICVECTPRIORITY2_0_DUAL                         0x0
#define APS_VIC_VICVECTPRIORITY2_0_SCR                  0
#define APS_VIC_VICVECTPRIORITY2_0_SCRREG                       0
#define APS_VIC_VICVECTPRIORITY2_0_WORD_COUNT                   0x1
#define APS_VIC_VICVECTPRIORITY2_0_RESET_VAL                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY2_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY2_0_READ_MASK                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY2_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_SHIFT)
#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_RANGE                       3:0
#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_MSB                 MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_WOFFSET                     0x0
#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_DEFAULT                     MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY3_0
#define APS_VIC_VICVECTPRIORITY3_0                      MK_ADDR_CONST(0x20c)
#define APS_VIC_VICVECTPRIORITY3_0_SECURE                       0x0
#define APS_VIC_VICVECTPRIORITY3_0_DUAL                         0x0
#define APS_VIC_VICVECTPRIORITY3_0_SCR                  0
#define APS_VIC_VICVECTPRIORITY3_0_SCRREG                       0
#define APS_VIC_VICVECTPRIORITY3_0_WORD_COUNT                   0x1
#define APS_VIC_VICVECTPRIORITY3_0_RESET_VAL                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY3_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY3_0_READ_MASK                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY3_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_SHIFT)
#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_RANGE                       3:0
#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_MSB                 MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_WOFFSET                     0x0
#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_DEFAULT                     MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY4_0
#define APS_VIC_VICVECTPRIORITY4_0                      MK_ADDR_CONST(0x210)
#define APS_VIC_VICVECTPRIORITY4_0_SECURE                       0x0
#define APS_VIC_VICVECTPRIORITY4_0_DUAL                         0x0
#define APS_VIC_VICVECTPRIORITY4_0_SCR                  0
#define APS_VIC_VICVECTPRIORITY4_0_SCRREG                       0
#define APS_VIC_VICVECTPRIORITY4_0_WORD_COUNT                   0x1
#define APS_VIC_VICVECTPRIORITY4_0_RESET_VAL                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY4_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY4_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY4_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY4_0_READ_MASK                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY4_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_SHIFT)
#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_RANGE                       3:0
#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_MSB                 MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_WOFFSET                     0x0
#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_DEFAULT                     MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY5_0
#define APS_VIC_VICVECTPRIORITY5_0                      MK_ADDR_CONST(0x214)
#define APS_VIC_VICVECTPRIORITY5_0_SECURE                       0x0
#define APS_VIC_VICVECTPRIORITY5_0_DUAL                         0x0
#define APS_VIC_VICVECTPRIORITY5_0_SCR                  0
#define APS_VIC_VICVECTPRIORITY5_0_SCRREG                       0
#define APS_VIC_VICVECTPRIORITY5_0_WORD_COUNT                   0x1
#define APS_VIC_VICVECTPRIORITY5_0_RESET_VAL                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY5_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY5_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY5_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY5_0_READ_MASK                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY5_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_SHIFT)
#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_RANGE                       3:0
#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_MSB                 MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_WOFFSET                     0x0
#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_DEFAULT                     MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY6_0
#define APS_VIC_VICVECTPRIORITY6_0                      MK_ADDR_CONST(0x218)
#define APS_VIC_VICVECTPRIORITY6_0_SECURE                       0x0
#define APS_VIC_VICVECTPRIORITY6_0_DUAL                         0x0
#define APS_VIC_VICVECTPRIORITY6_0_SCR                  0
#define APS_VIC_VICVECTPRIORITY6_0_SCRREG                       0
#define APS_VIC_VICVECTPRIORITY6_0_WORD_COUNT                   0x1
#define APS_VIC_VICVECTPRIORITY6_0_RESET_VAL                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY6_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY6_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY6_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY6_0_READ_MASK                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY6_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_SHIFT)
#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_RANGE                       3:0
#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_MSB                 MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_WOFFSET                     0x0
#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_DEFAULT                     MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY7_0
#define APS_VIC_VICVECTPRIORITY7_0                      MK_ADDR_CONST(0x21c)
#define APS_VIC_VICVECTPRIORITY7_0_SECURE                       0x0
#define APS_VIC_VICVECTPRIORITY7_0_DUAL                         0x0
#define APS_VIC_VICVECTPRIORITY7_0_SCR                  0
#define APS_VIC_VICVECTPRIORITY7_0_SCRREG                       0
#define APS_VIC_VICVECTPRIORITY7_0_WORD_COUNT                   0x1
#define APS_VIC_VICVECTPRIORITY7_0_RESET_VAL                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY7_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY7_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY7_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY7_0_READ_MASK                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY7_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_SHIFT)
#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_RANGE                       3:0
#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_MSB                 MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_WOFFSET                     0x0
#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_DEFAULT                     MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY8_0
#define APS_VIC_VICVECTPRIORITY8_0                      MK_ADDR_CONST(0x220)
#define APS_VIC_VICVECTPRIORITY8_0_SECURE                       0x0
#define APS_VIC_VICVECTPRIORITY8_0_DUAL                         0x0
#define APS_VIC_VICVECTPRIORITY8_0_SCR                  0
#define APS_VIC_VICVECTPRIORITY8_0_SCRREG                       0
#define APS_VIC_VICVECTPRIORITY8_0_WORD_COUNT                   0x1
#define APS_VIC_VICVECTPRIORITY8_0_RESET_VAL                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY8_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY8_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY8_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY8_0_READ_MASK                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY8_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_SHIFT)
#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_RANGE                       3:0
#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_MSB                 MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_WOFFSET                     0x0
#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_DEFAULT                     MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY9_0
#define APS_VIC_VICVECTPRIORITY9_0                      MK_ADDR_CONST(0x224)
#define APS_VIC_VICVECTPRIORITY9_0_SECURE                       0x0
#define APS_VIC_VICVECTPRIORITY9_0_DUAL                         0x0
#define APS_VIC_VICVECTPRIORITY9_0_SCR                  0
#define APS_VIC_VICVECTPRIORITY9_0_SCRREG                       0
#define APS_VIC_VICVECTPRIORITY9_0_WORD_COUNT                   0x1
#define APS_VIC_VICVECTPRIORITY9_0_RESET_VAL                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY9_0_RESET_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY9_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY9_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY9_0_READ_MASK                    MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY9_0_WRITE_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_SHIFT)
#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_RANGE                       3:0
#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_MSB                 MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_WOFFSET                     0x0
#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_DEFAULT                     MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY10_0
#define APS_VIC_VICVECTPRIORITY10_0                     MK_ADDR_CONST(0x228)
#define APS_VIC_VICVECTPRIORITY10_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY10_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY10_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY10_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY10_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY10_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY10_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY10_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY10_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY10_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY10_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_SHIFT)
#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY11_0
#define APS_VIC_VICVECTPRIORITY11_0                     MK_ADDR_CONST(0x22c)
#define APS_VIC_VICVECTPRIORITY11_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY11_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY11_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY11_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY11_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY11_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY11_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY11_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY11_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY11_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY11_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_SHIFT)
#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY12_0
#define APS_VIC_VICVECTPRIORITY12_0                     MK_ADDR_CONST(0x230)
#define APS_VIC_VICVECTPRIORITY12_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY12_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY12_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY12_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY12_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY12_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY12_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY12_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY12_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY12_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY12_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_SHIFT)
#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY13_0
#define APS_VIC_VICVECTPRIORITY13_0                     MK_ADDR_CONST(0x234)
#define APS_VIC_VICVECTPRIORITY13_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY13_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY13_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY13_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY13_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY13_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY13_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY13_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY13_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY13_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY13_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_SHIFT)
#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY14_0
#define APS_VIC_VICVECTPRIORITY14_0                     MK_ADDR_CONST(0x238)
#define APS_VIC_VICVECTPRIORITY14_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY14_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY14_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY14_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY14_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY14_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY14_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY14_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY14_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY14_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY14_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_SHIFT)
#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY15_0
#define APS_VIC_VICVECTPRIORITY15_0                     MK_ADDR_CONST(0x23c)
#define APS_VIC_VICVECTPRIORITY15_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY15_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY15_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY15_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY15_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY15_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY15_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY15_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY15_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY15_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY15_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_SHIFT)
#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY16_0
#define APS_VIC_VICVECTPRIORITY16_0                     MK_ADDR_CONST(0x240)
#define APS_VIC_VICVECTPRIORITY16_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY16_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY16_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY16_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY16_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY16_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY16_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY16_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY16_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY16_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY16_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_SHIFT)
#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY17_0
#define APS_VIC_VICVECTPRIORITY17_0                     MK_ADDR_CONST(0x244)
#define APS_VIC_VICVECTPRIORITY17_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY17_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY17_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY17_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY17_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY17_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY17_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY17_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY17_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY17_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY17_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_SHIFT)
#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY18_0
#define APS_VIC_VICVECTPRIORITY18_0                     MK_ADDR_CONST(0x248)
#define APS_VIC_VICVECTPRIORITY18_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY18_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY18_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY18_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY18_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY18_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY18_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY18_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY18_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY18_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY18_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_SHIFT)
#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY19_0
#define APS_VIC_VICVECTPRIORITY19_0                     MK_ADDR_CONST(0x24c)
#define APS_VIC_VICVECTPRIORITY19_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY19_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY19_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY19_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY19_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY19_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY19_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY19_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY19_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY19_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY19_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_SHIFT)
#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY20_0
#define APS_VIC_VICVECTPRIORITY20_0                     MK_ADDR_CONST(0x250)
#define APS_VIC_VICVECTPRIORITY20_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY20_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY20_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY20_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY20_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY20_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY20_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY20_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY20_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY20_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY20_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_SHIFT)
#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY21_0
#define APS_VIC_VICVECTPRIORITY21_0                     MK_ADDR_CONST(0x254)
#define APS_VIC_VICVECTPRIORITY21_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY21_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY21_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY21_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY21_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY21_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY21_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY21_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY21_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY21_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY21_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_SHIFT)
#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY22_0
#define APS_VIC_VICVECTPRIORITY22_0                     MK_ADDR_CONST(0x258)
#define APS_VIC_VICVECTPRIORITY22_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY22_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY22_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY22_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY22_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY22_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY22_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY22_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY22_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY22_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY22_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_SHIFT)
#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY23_0
#define APS_VIC_VICVECTPRIORITY23_0                     MK_ADDR_CONST(0x25c)
#define APS_VIC_VICVECTPRIORITY23_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY23_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY23_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY23_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY23_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY23_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY23_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY23_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY23_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY23_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY23_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_SHIFT)
#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY24_0
#define APS_VIC_VICVECTPRIORITY24_0                     MK_ADDR_CONST(0x260)
#define APS_VIC_VICVECTPRIORITY24_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY24_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY24_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY24_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY24_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY24_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY24_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY24_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY24_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY24_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY24_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_SHIFT)
#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY25_0
#define APS_VIC_VICVECTPRIORITY25_0                     MK_ADDR_CONST(0x264)
#define APS_VIC_VICVECTPRIORITY25_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY25_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY25_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY25_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY25_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY25_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY25_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY25_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY25_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY25_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY25_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_SHIFT)
#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY26_0
#define APS_VIC_VICVECTPRIORITY26_0                     MK_ADDR_CONST(0x268)
#define APS_VIC_VICVECTPRIORITY26_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY26_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY26_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY26_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY26_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY26_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY26_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY26_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY26_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY26_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY26_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_SHIFT)
#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY27_0
#define APS_VIC_VICVECTPRIORITY27_0                     MK_ADDR_CONST(0x26c)
#define APS_VIC_VICVECTPRIORITY27_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY27_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY27_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY27_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY27_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY27_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY27_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY27_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY27_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY27_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY27_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_SHIFT)
#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY28_0
#define APS_VIC_VICVECTPRIORITY28_0                     MK_ADDR_CONST(0x270)
#define APS_VIC_VICVECTPRIORITY28_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY28_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY28_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY28_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY28_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY28_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY28_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY28_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY28_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY28_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY28_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_SHIFT)
#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY29_0
#define APS_VIC_VICVECTPRIORITY29_0                     MK_ADDR_CONST(0x274)
#define APS_VIC_VICVECTPRIORITY29_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY29_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY29_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY29_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY29_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY29_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY29_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY29_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY29_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY29_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY29_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_SHIFT)
#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY30_0
#define APS_VIC_VICVECTPRIORITY30_0                     MK_ADDR_CONST(0x278)
#define APS_VIC_VICVECTPRIORITY30_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY30_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY30_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY30_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY30_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY30_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY30_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY30_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY30_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY30_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY30_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_SHIFT)
#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register APS_VIC_VICVECTPRIORITY31_0
#define APS_VIC_VICVECTPRIORITY31_0                     MK_ADDR_CONST(0x27c)
#define APS_VIC_VICVECTPRIORITY31_0_SECURE                      0x0
#define APS_VIC_VICVECTPRIORITY31_0_DUAL                        0x0
#define APS_VIC_VICVECTPRIORITY31_0_SCR                         0
#define APS_VIC_VICVECTPRIORITY31_0_SCRREG                      0
#define APS_VIC_VICVECTPRIORITY31_0_WORD_COUNT                  0x1
#define APS_VIC_VICVECTPRIORITY31_0_RESET_VAL                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY31_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY31_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY31_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY31_0_READ_MASK                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY31_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_SHIFT                     MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_SHIFT)
#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_RANGE                     3:0
#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_MSB                       MK_SHIFT_CONST(3)
#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_LSB                       MK_SHIFT_CONST(0)
#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_WOFFSET                   0x0
#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_DEFAULT                   MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_DEFAULT_MASK                      MK_MASK_CONST(0xf)
#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Reserved address 0x280

// Reserved address 0x284

// Reserved address 0x288

// Reserved address 0x28c

// Reserved address 0x290

// Reserved address 0x294

// Reserved address 0x298

// Reserved address 0x29c

// Reserved address 0x2a0

// Reserved address 0x2a4

// Reserved address 0x2a8

// Reserved address 0x2ac

// Reserved address 0x2b0

// Reserved address 0x2b4

// Reserved address 0x2b8

// Reserved address 0x2bc

// Reserved address 0x2c0

// Reserved address 0x2c4

// Reserved address 0x2c8

// Reserved address 0x2cc

// Reserved address 0x2d0

// Reserved address 0x2d4

// Reserved address 0x2d8

// Reserved address 0x2dc

// Reserved address 0x2e0

// Reserved address 0x2e4

// Reserved address 0x2e8

// Reserved address 0x2ec

// Reserved address 0x2f0

// Reserved address 0x2f4

// Reserved address 0x2f8

// Reserved address 0x2fc

// Register APS_VIC_VICITCR_0
#define APS_VIC_VICITCR_0                       MK_ADDR_CONST(0x300)
#define APS_VIC_VICITCR_0_SECURE                        0x0
#define APS_VIC_VICITCR_0_DUAL                  0x0
#define APS_VIC_VICITCR_0_SCR                   0
#define APS_VIC_VICITCR_0_SCRREG                        0
#define APS_VIC_VICITCR_0_WORD_COUNT                    0x1
#define APS_VIC_VICITCR_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define APS_VIC_VICITCR_0_RESET_MASK                    MK_MASK_CONST(0x3)
#define APS_VIC_VICITCR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICITCR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITCR_0_READ_MASK                     MK_MASK_CONST(0x3)
#define APS_VIC_VICITCR_0_WRITE_MASK                    MK_MASK_CONST(0x3)
#define APS_VIC_VICITCR_0_ISS_SHIFT                     MK_SHIFT_CONST(1)
#define APS_VIC_VICITCR_0_ISS_FIELD                     MK_FIELD_CONST(0x1, APS_VIC_VICITCR_0_ISS_SHIFT)
#define APS_VIC_VICITCR_0_ISS_RANGE                     1:1
#define APS_VIC_VICITCR_0_ISS_MSB                       MK_SHIFT_CONST(1)
#define APS_VIC_VICITCR_0_ISS_LSB                       MK_SHIFT_CONST(1)
#define APS_VIC_VICITCR_0_ISS_WOFFSET                   0x0
#define APS_VIC_VICITCR_0_ISS_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICITCR_0_ISS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define APS_VIC_VICITCR_0_ISS_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICITCR_0_ISS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICITCR_0_ISS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define APS_VIC_VICITCR_0_ISS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define APS_VIC_VICITCR_0_ITEN_SHIFT                    MK_SHIFT_CONST(0)
#define APS_VIC_VICITCR_0_ITEN_FIELD                    MK_FIELD_CONST(0x1, APS_VIC_VICITCR_0_ITEN_SHIFT)
#define APS_VIC_VICITCR_0_ITEN_RANGE                    0:0
#define APS_VIC_VICITCR_0_ITEN_MSB                      MK_SHIFT_CONST(0)
#define APS_VIC_VICITCR_0_ITEN_LSB                      MK_SHIFT_CONST(0)
#define APS_VIC_VICITCR_0_ITEN_WOFFSET                  0x0
#define APS_VIC_VICITCR_0_ITEN_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICITCR_0_ITEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define APS_VIC_VICITCR_0_ITEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITCR_0_ITEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICITCR_0_ITEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define APS_VIC_VICITCR_0_ITEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register APS_VIC_VICITIP1_0
#define APS_VIC_VICITIP1_0                      MK_ADDR_CONST(0x304)
#define APS_VIC_VICITIP1_0_SECURE                       0x0
#define APS_VIC_VICITIP1_0_DUAL                         0x0
#define APS_VIC_VICITIP1_0_SCR                  0
#define APS_VIC_VICITIP1_0_SCRREG                       0
#define APS_VIC_VICITIP1_0_WORD_COUNT                   0x1
#define APS_VIC_VICITIP1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_READ_MASK                    MK_MASK_CONST(0x7c0)
#define APS_VIC_VICITIP1_0_WRITE_MASK                   MK_MASK_CONST(0x1c0)
#define APS_VIC_VICITIP1_0_VICFIQINREG_SHIFT                    MK_SHIFT_CONST(10)
#define APS_VIC_VICITIP1_0_VICFIQINREG_FIELD                    MK_FIELD_CONST(0x1, APS_VIC_VICITIP1_0_VICFIQINREG_SHIFT)
#define APS_VIC_VICITIP1_0_VICFIQINREG_RANGE                    10:10
#define APS_VIC_VICITIP1_0_VICFIQINREG_MSB                      MK_SHIFT_CONST(10)
#define APS_VIC_VICITIP1_0_VICFIQINREG_LSB                      MK_SHIFT_CONST(10)
#define APS_VIC_VICITIP1_0_VICFIQINREG_WOFFSET                  0x0
#define APS_VIC_VICITIP1_0_VICFIQINREG_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICFIQINREG_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICFIQINREG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICFIQINREG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICFIQINREG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICFIQINREG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define APS_VIC_VICITIP1_0_VICIRQINREG_SHIFT                    MK_SHIFT_CONST(9)
#define APS_VIC_VICITIP1_0_VICIRQINREG_FIELD                    MK_FIELD_CONST(0x1, APS_VIC_VICITIP1_0_VICIRQINREG_SHIFT)
#define APS_VIC_VICITIP1_0_VICIRQINREG_RANGE                    9:9
#define APS_VIC_VICITIP1_0_VICIRQINREG_MSB                      MK_SHIFT_CONST(9)
#define APS_VIC_VICITIP1_0_VICIRQINREG_LSB                      MK_SHIFT_CONST(9)
#define APS_VIC_VICITIP1_0_VICIRQINREG_WOFFSET                  0x0
#define APS_VIC_VICITIP1_0_VICIRQINREG_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICIRQINREG_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICIRQINREG_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICIRQINREG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICIRQINREG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICIRQINREG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define APS_VIC_VICITIP1_0_VICIRQACK_SHIFT                      MK_SHIFT_CONST(8)
#define APS_VIC_VICITIP1_0_VICIRQACK_FIELD                      MK_FIELD_CONST(0x1, APS_VIC_VICITIP1_0_VICIRQACK_SHIFT)
#define APS_VIC_VICITIP1_0_VICIRQACK_RANGE                      8:8
#define APS_VIC_VICITIP1_0_VICIRQACK_MSB                        MK_SHIFT_CONST(8)
#define APS_VIC_VICITIP1_0_VICIRQACK_LSB                        MK_SHIFT_CONST(8)
#define APS_VIC_VICITIP1_0_VICIRQACK_WOFFSET                    0x0
#define APS_VIC_VICITIP1_0_VICIRQACK_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICIRQACK_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICIRQACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICIRQACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICIRQACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_VICIRQACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define APS_VIC_VICITIP1_0_NVICIRQIN_SHIFT                      MK_SHIFT_CONST(7)
#define APS_VIC_VICITIP1_0_NVICIRQIN_FIELD                      MK_FIELD_CONST(0x1, APS_VIC_VICITIP1_0_NVICIRQIN_SHIFT)
#define APS_VIC_VICITIP1_0_NVICIRQIN_RANGE                      7:7
#define APS_VIC_VICITIP1_0_NVICIRQIN_MSB                        MK_SHIFT_CONST(7)
#define APS_VIC_VICITIP1_0_NVICIRQIN_LSB                        MK_SHIFT_CONST(7)
#define APS_VIC_VICITIP1_0_NVICIRQIN_WOFFSET                    0x0
#define APS_VIC_VICITIP1_0_NVICIRQIN_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_NVICIRQIN_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_NVICIRQIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_NVICIRQIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_NVICIRQIN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_NVICIRQIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define APS_VIC_VICITIP1_0_NVICFIQIN_SHIFT                      MK_SHIFT_CONST(6)
#define APS_VIC_VICITIP1_0_NVICFIQIN_FIELD                      MK_FIELD_CONST(0x1, APS_VIC_VICITIP1_0_NVICFIQIN_SHIFT)
#define APS_VIC_VICITIP1_0_NVICFIQIN_RANGE                      6:6
#define APS_VIC_VICITIP1_0_NVICFIQIN_MSB                        MK_SHIFT_CONST(6)
#define APS_VIC_VICITIP1_0_NVICFIQIN_LSB                        MK_SHIFT_CONST(6)
#define APS_VIC_VICITIP1_0_NVICFIQIN_WOFFSET                    0x0
#define APS_VIC_VICITIP1_0_NVICFIQIN_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_NVICFIQIN_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_NVICFIQIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_NVICFIQIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_NVICFIQIN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP1_0_NVICFIQIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register APS_VIC_VICITIP2_0
#define APS_VIC_VICITIP2_0                      MK_ADDR_CONST(0x308)
#define APS_VIC_VICITIP2_0_SECURE                       0x0
#define APS_VIC_VICITIP2_0_DUAL                         0x0
#define APS_VIC_VICITIP2_0_SCR                  0
#define APS_VIC_VICITIP2_0_SCRREG                       0
#define APS_VIC_VICITIP2_0_WORD_COUNT                   0x1
#define APS_VIC_VICITIP2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP2_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP2_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICITIP2_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICITIP2_0_VICVECTADDRIN_SHIFT                  MK_SHIFT_CONST(0)
#define APS_VIC_VICITIP2_0_VICVECTADDRIN_FIELD                  MK_FIELD_CONST(0xffffffff, APS_VIC_VICITIP2_0_VICVECTADDRIN_SHIFT)
#define APS_VIC_VICITIP2_0_VICVECTADDRIN_RANGE                  31:0
#define APS_VIC_VICITIP2_0_VICVECTADDRIN_MSB                    MK_SHIFT_CONST(31)
#define APS_VIC_VICITIP2_0_VICVECTADDRIN_LSB                    MK_SHIFT_CONST(0)
#define APS_VIC_VICITIP2_0_VICVECTADDRIN_WOFFSET                        0x0
#define APS_VIC_VICITIP2_0_VICVECTADDRIN_DEFAULT                        MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP2_0_VICVECTADDRIN_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP2_0_VICVECTADDRIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP2_0_VICVECTADDRIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP2_0_VICVECTADDRIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define APS_VIC_VICITIP2_0_VICVECTADDRIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register APS_VIC_VICITOP1_0
#define APS_VIC_VICITOP1_0                      MK_ADDR_CONST(0x30c)
#define APS_VIC_VICITOP1_0_SECURE                       0x0
#define APS_VIC_VICITOP1_0_DUAL                         0x0
#define APS_VIC_VICITOP1_0_SCR                  0
#define APS_VIC_VICITOP1_0_SCRREG                       0
#define APS_VIC_VICITOP1_0_WORD_COUNT                   0x1
#define APS_VIC_VICITOP1_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_RESET_MASK                   MK_MASK_CONST(0x3c0)
#define APS_VIC_VICITOP1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_READ_MASK                    MK_MASK_CONST(0x3c0)
#define APS_VIC_VICITOP1_0_WRITE_MASK                   MK_MASK_CONST(0x3c0)
#define APS_VIC_VICITOP1_0_VICIRQACKOUT_SHIFT                   MK_SHIFT_CONST(9)
#define APS_VIC_VICITOP1_0_VICIRQACKOUT_FIELD                   MK_FIELD_CONST(0x1, APS_VIC_VICITOP1_0_VICIRQACKOUT_SHIFT)
#define APS_VIC_VICITOP1_0_VICIRQACKOUT_RANGE                   9:9
#define APS_VIC_VICITOP1_0_VICIRQACKOUT_MSB                     MK_SHIFT_CONST(9)
#define APS_VIC_VICITOP1_0_VICIRQACKOUT_LSB                     MK_SHIFT_CONST(9)
#define APS_VIC_VICITOP1_0_VICIRQACKOUT_WOFFSET                 0x0
#define APS_VIC_VICITOP1_0_VICIRQACKOUT_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICIRQACKOUT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_VIC_VICITOP1_0_VICIRQACKOUT_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICIRQACKOUT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICIRQACKOUT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICIRQACKOUT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_VIC_VICITOP1_0_VICVECTADDRV_SHIFT                   MK_SHIFT_CONST(8)
#define APS_VIC_VICITOP1_0_VICVECTADDRV_FIELD                   MK_FIELD_CONST(0x1, APS_VIC_VICITOP1_0_VICVECTADDRV_SHIFT)
#define APS_VIC_VICITOP1_0_VICVECTADDRV_RANGE                   8:8
#define APS_VIC_VICITOP1_0_VICVECTADDRV_MSB                     MK_SHIFT_CONST(8)
#define APS_VIC_VICITOP1_0_VICVECTADDRV_LSB                     MK_SHIFT_CONST(8)
#define APS_VIC_VICITOP1_0_VICVECTADDRV_WOFFSET                 0x0
#define APS_VIC_VICITOP1_0_VICVECTADDRV_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICVECTADDRV_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define APS_VIC_VICITOP1_0_VICVECTADDRV_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICVECTADDRV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICVECTADDRV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICVECTADDRV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define APS_VIC_VICITOP1_0_VICIRQ_SHIFT                 MK_SHIFT_CONST(7)
#define APS_VIC_VICITOP1_0_VICIRQ_FIELD                 MK_FIELD_CONST(0x1, APS_VIC_VICITOP1_0_VICIRQ_SHIFT)
#define APS_VIC_VICITOP1_0_VICIRQ_RANGE                 7:7
#define APS_VIC_VICITOP1_0_VICIRQ_MSB                   MK_SHIFT_CONST(7)
#define APS_VIC_VICITOP1_0_VICIRQ_LSB                   MK_SHIFT_CONST(7)
#define APS_VIC_VICITOP1_0_VICIRQ_WOFFSET                       0x0
#define APS_VIC_VICITOP1_0_VICIRQ_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICIRQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define APS_VIC_VICITOP1_0_VICIRQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICIRQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICIRQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICIRQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define APS_VIC_VICITOP1_0_VICFIQ_SHIFT                 MK_SHIFT_CONST(6)
#define APS_VIC_VICITOP1_0_VICFIQ_FIELD                 MK_FIELD_CONST(0x1, APS_VIC_VICITOP1_0_VICFIQ_SHIFT)
#define APS_VIC_VICITOP1_0_VICFIQ_RANGE                 6:6
#define APS_VIC_VICITOP1_0_VICFIQ_MSB                   MK_SHIFT_CONST(6)
#define APS_VIC_VICITOP1_0_VICFIQ_LSB                   MK_SHIFT_CONST(6)
#define APS_VIC_VICITOP1_0_VICFIQ_WOFFSET                       0x0
#define APS_VIC_VICITOP1_0_VICFIQ_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICFIQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define APS_VIC_VICITOP1_0_VICFIQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICFIQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICFIQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP1_0_VICFIQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register APS_VIC_VICITOP2_0
#define APS_VIC_VICITOP2_0                      MK_ADDR_CONST(0x310)
#define APS_VIC_VICITOP2_0_SECURE                       0x0
#define APS_VIC_VICITOP2_0_DUAL                         0x0
#define APS_VIC_VICITOP2_0_SCR                  0
#define APS_VIC_VICITOP2_0_SCRREG                       0
#define APS_VIC_VICITOP2_0_WORD_COUNT                   0x1
#define APS_VIC_VICITOP2_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP2_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICITOP2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP2_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICITOP2_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICITOP2_0_VICVECTADDROUT_SHIFT                 MK_SHIFT_CONST(0)
#define APS_VIC_VICITOP2_0_VICVECTADDROUT_FIELD                 MK_FIELD_CONST(0xffffffff, APS_VIC_VICITOP2_0_VICVECTADDROUT_SHIFT)
#define APS_VIC_VICITOP2_0_VICVECTADDROUT_RANGE                 31:0
#define APS_VIC_VICITOP2_0_VICVECTADDROUT_MSB                   MK_SHIFT_CONST(31)
#define APS_VIC_VICITOP2_0_VICVECTADDROUT_LSB                   MK_SHIFT_CONST(0)
#define APS_VIC_VICITOP2_0_VICVECTADDROUT_WOFFSET                       0x0
#define APS_VIC_VICITOP2_0_VICVECTADDROUT_DEFAULT                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP2_0_VICVECTADDROUT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICITOP2_0_VICVECTADDROUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP2_0_VICVECTADDROUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP2_0_VICVECTADDROUT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define APS_VIC_VICITOP2_0_VICVECTADDROUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register APS_VIC_VICINTSSTATUS_0
#define APS_VIC_VICINTSSTATUS_0                 MK_ADDR_CONST(0x314)
#define APS_VIC_VICINTSSTATUS_0_SECURE                  0x0
#define APS_VIC_VICINTSSTATUS_0_DUAL                    0x0
#define APS_VIC_VICINTSSTATUS_0_SCR                     0
#define APS_VIC_VICINTSSTATUS_0_SCRREG                  0
#define APS_VIC_VICINTSSTATUS_0_WORD_COUNT                      0x1
#define APS_VIC_VICINTSSTATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICINTSSTATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICINTSSTATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_SHIFT                        MK_SHIFT_CONST(0)
#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_FIELD                        MK_FIELD_CONST(0xffffffff, APS_VIC_VICINTSSTATUS_0_INTSSTATUS_SHIFT)
#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_RANGE                        31:0
#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_MSB                  MK_SHIFT_CONST(31)
#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_LSB                  MK_SHIFT_CONST(0)
#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_WOFFSET                      0x0
#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register APS_VIC_VICINTSSTATUSCLEAR_0
#define APS_VIC_VICINTSSTATUSCLEAR_0                    MK_ADDR_CONST(0x318)
#define APS_VIC_VICINTSSTATUSCLEAR_0_SECURE                     0x0
#define APS_VIC_VICINTSSTATUSCLEAR_0_DUAL                       0x0
#define APS_VIC_VICINTSSTATUSCLEAR_0_SCR                        0
#define APS_VIC_VICINTSSTATUSCLEAR_0_SCRREG                     0
#define APS_VIC_VICINTSSTATUSCLEAR_0_WORD_COUNT                         0x1
#define APS_VIC_VICINTSSTATUSCLEAR_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUSCLEAR_0_RESET_MASK                         MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUSCLEAR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUSCLEAR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUSCLEAR_0_READ_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUSCLEAR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_SHIFT                   MK_SHIFT_CONST(0)
#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_FIELD                   MK_FIELD_CONST(0xffffffff, APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_SHIFT)
#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_RANGE                   31:0
#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_MSB                     MK_SHIFT_CONST(31)
#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_LSB                     MK_SHIFT_CONST(0)
#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_WOFFSET                 0x0
#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Reserved address 0x31c

// Reserved address 0x320

// Reserved address 0x324

// Reserved address 0x328

// Reserved address 0x32c

// Reserved address 0x330

// Reserved address 0x334

// Reserved address 0x338

// Reserved address 0x33c

// Reserved address 0x340

// Reserved address 0x344

// Reserved address 0x348

// Reserved address 0x34c

// Reserved address 0x350

// Reserved address 0x354

// Reserved address 0x358

// Reserved address 0x35c

// Reserved address 0x360

// Reserved address 0x364

// Reserved address 0x368

// Reserved address 0x36c

// Reserved address 0x370

// Reserved address 0x374

// Reserved address 0x378

// Reserved address 0x37c

// Reserved address 0x380

// Reserved address 0x384

// Reserved address 0x388

// Reserved address 0x38c

// Reserved address 0x390

// Reserved address 0x394

// Reserved address 0x398

// Reserved address 0x39c

// Reserved address 0x3a0

// Reserved address 0x3a4

// Reserved address 0x3a8

// Reserved address 0x3ac

// Reserved address 0x3b0

// Reserved address 0x3b4

// Reserved address 0x3b8

// Reserved address 0x3bc

// Reserved address 0x3c0

// Reserved address 0x3c4

// Reserved address 0x3c8

// Reserved address 0x3cc

// Reserved address 0x3d0

// Reserved address 0x3d4

// Reserved address 0x3d8

// Reserved address 0x3dc

// Reserved address 0x3e0

// Reserved address 0x3e4

// Reserved address 0x3e8

// Reserved address 0x3ec

// Reserved address 0x3f0

// Reserved address 0x3f4

// Reserved address 0x3f8

// Reserved address 0x3fc

// Reserved address 0x400

// Reserved address 0x404

// Reserved address 0x408

// Reserved address 0x40c

// Reserved address 0x410

// Reserved address 0x414

// Reserved address 0x418

// Reserved address 0x41c

// Reserved address 0x420

// Reserved address 0x424

// Reserved address 0x428

// Reserved address 0x42c

// Reserved address 0x430

// Reserved address 0x434

// Reserved address 0x438

// Reserved address 0x43c

// Reserved address 0x440

// Reserved address 0x444

// Reserved address 0x448

// Reserved address 0x44c

// Reserved address 0x450

// Reserved address 0x454

// Reserved address 0x458

// Reserved address 0x45c

// Reserved address 0x460

// Reserved address 0x464

// Reserved address 0x468

// Reserved address 0x46c

// Reserved address 0x470

// Reserved address 0x474

// Reserved address 0x478

// Reserved address 0x47c

// Reserved address 0x480

// Reserved address 0x484

// Reserved address 0x488

// Reserved address 0x48c

// Reserved address 0x490

// Reserved address 0x494

// Reserved address 0x498

// Reserved address 0x49c

// Reserved address 0x4a0

// Reserved address 0x4a4

// Reserved address 0x4a8

// Reserved address 0x4ac

// Reserved address 0x4b0

// Reserved address 0x4b4

// Reserved address 0x4b8

// Reserved address 0x4bc

// Reserved address 0x4c0

// Reserved address 0x4c4

// Reserved address 0x4c8

// Reserved address 0x4cc

// Reserved address 0x4d0

// Reserved address 0x4d4

// Reserved address 0x4d8

// Reserved address 0x4dc

// Reserved address 0x4e0

// Reserved address 0x4e4

// Reserved address 0x4e8

// Reserved address 0x4ec

// Reserved address 0x4f0

// Reserved address 0x4f4

// Reserved address 0x4f8

// Reserved address 0x4fc

// Reserved address 0x500

// Reserved address 0x504

// Reserved address 0x508

// Reserved address 0x50c

// Reserved address 0x510

// Reserved address 0x514

// Reserved address 0x518

// Reserved address 0x51c

// Reserved address 0x520

// Reserved address 0x524

// Reserved address 0x528

// Reserved address 0x52c

// Reserved address 0x530

// Reserved address 0x534

// Reserved address 0x538

// Reserved address 0x53c

// Reserved address 0x540

// Reserved address 0x544

// Reserved address 0x548

// Reserved address 0x54c

// Reserved address 0x550

// Reserved address 0x554

// Reserved address 0x558

// Reserved address 0x55c

// Reserved address 0x560

// Reserved address 0x564

// Reserved address 0x568

// Reserved address 0x56c

// Reserved address 0x570

// Reserved address 0x574

// Reserved address 0x578

// Reserved address 0x57c

// Reserved address 0x580

// Reserved address 0x584

// Reserved address 0x588

// Reserved address 0x58c

// Reserved address 0x590

// Reserved address 0x594

// Reserved address 0x598

// Reserved address 0x59c

// Reserved address 0x5a0

// Reserved address 0x5a4

// Reserved address 0x5a8

// Reserved address 0x5ac

// Reserved address 0x5b0

// Reserved address 0x5b4

// Reserved address 0x5b8

// Reserved address 0x5bc

// Reserved address 0x5c0

// Reserved address 0x5c4

// Reserved address 0x5c8

// Reserved address 0x5cc

// Reserved address 0x5d0

// Reserved address 0x5d4

// Reserved address 0x5d8

// Reserved address 0x5dc

// Reserved address 0x5e0

// Reserved address 0x5e4

// Reserved address 0x5e8

// Reserved address 0x5ec

// Reserved address 0x5f0

// Reserved address 0x5f4

// Reserved address 0x5f8

// Reserved address 0x5fc

// Reserved address 0x600

// Reserved address 0x604

// Reserved address 0x608

// Reserved address 0x60c

// Reserved address 0x610

// Reserved address 0x614

// Reserved address 0x618

// Reserved address 0x61c

// Reserved address 0x620

// Reserved address 0x624

// Reserved address 0x628

// Reserved address 0x62c

// Reserved address 0x630

// Reserved address 0x634

// Reserved address 0x638

// Reserved address 0x63c

// Reserved address 0x640

// Reserved address 0x644

// Reserved address 0x648

// Reserved address 0x64c

// Reserved address 0x650

// Reserved address 0x654

// Reserved address 0x658

// Reserved address 0x65c

// Reserved address 0x660

// Reserved address 0x664

// Reserved address 0x668

// Reserved address 0x66c

// Reserved address 0x670

// Reserved address 0x674

// Reserved address 0x678

// Reserved address 0x67c

// Reserved address 0x680

// Reserved address 0x684

// Reserved address 0x688

// Reserved address 0x68c

// Reserved address 0x690

// Reserved address 0x694

// Reserved address 0x698

// Reserved address 0x69c

// Reserved address 0x6a0

// Reserved address 0x6a4

// Reserved address 0x6a8

// Reserved address 0x6ac

// Reserved address 0x6b0

// Reserved address 0x6b4

// Reserved address 0x6b8

// Reserved address 0x6bc

// Reserved address 0x6c0

// Reserved address 0x6c4

// Reserved address 0x6c8

// Reserved address 0x6cc

// Reserved address 0x6d0

// Reserved address 0x6d4

// Reserved address 0x6d8

// Reserved address 0x6dc

// Reserved address 0x6e0

// Reserved address 0x6e4

// Reserved address 0x6e8

// Reserved address 0x6ec

// Reserved address 0x6f0

// Reserved address 0x6f4

// Reserved address 0x6f8

// Reserved address 0x6fc

// Reserved address 0x700

// Reserved address 0x704

// Reserved address 0x708

// Reserved address 0x70c

// Reserved address 0x710

// Reserved address 0x714

// Reserved address 0x718

// Reserved address 0x71c

// Reserved address 0x720

// Reserved address 0x724

// Reserved address 0x728

// Reserved address 0x72c

// Reserved address 0x730

// Reserved address 0x734

// Reserved address 0x738

// Reserved address 0x73c

// Reserved address 0x740

// Reserved address 0x744

// Reserved address 0x748

// Reserved address 0x74c

// Reserved address 0x750

// Reserved address 0x754

// Reserved address 0x758

// Reserved address 0x75c

// Reserved address 0x760

// Reserved address 0x764

// Reserved address 0x768

// Reserved address 0x76c

// Reserved address 0x770

// Reserved address 0x774

// Reserved address 0x778

// Reserved address 0x77c

// Reserved address 0x780

// Reserved address 0x784

// Reserved address 0x788

// Reserved address 0x78c

// Reserved address 0x790

// Reserved address 0x794

// Reserved address 0x798

// Reserved address 0x79c

// Reserved address 0x7a0

// Reserved address 0x7a4

// Reserved address 0x7a8

// Reserved address 0x7ac

// Reserved address 0x7b0

// Reserved address 0x7b4

// Reserved address 0x7b8

// Reserved address 0x7bc

// Reserved address 0x7c0

// Reserved address 0x7c4

// Reserved address 0x7c8

// Reserved address 0x7cc

// Reserved address 0x7d0

// Reserved address 0x7d4

// Reserved address 0x7d8

// Reserved address 0x7dc

// Reserved address 0x7e0

// Reserved address 0x7e4

// Reserved address 0x7e8

// Reserved address 0x7ec

// Reserved address 0x7f0

// Reserved address 0x7f4

// Reserved address 0x7f8

// Reserved address 0x7fc

// Reserved address 0x800

// Reserved address 0x804

// Reserved address 0x808

// Reserved address 0x80c

// Reserved address 0x810

// Reserved address 0x814

// Reserved address 0x818

// Reserved address 0x81c

// Reserved address 0x820

// Reserved address 0x824

// Reserved address 0x828

// Reserved address 0x82c

// Reserved address 0x830

// Reserved address 0x834

// Reserved address 0x838

// Reserved address 0x83c

// Reserved address 0x840

// Reserved address 0x844

// Reserved address 0x848

// Reserved address 0x84c

// Reserved address 0x850

// Reserved address 0x854

// Reserved address 0x858

// Reserved address 0x85c

// Reserved address 0x860

// Reserved address 0x864

// Reserved address 0x868

// Reserved address 0x86c

// Reserved address 0x870

// Reserved address 0x874

// Reserved address 0x878

// Reserved address 0x87c

// Reserved address 0x880

// Reserved address 0x884

// Reserved address 0x888

// Reserved address 0x88c

// Reserved address 0x890

// Reserved address 0x894

// Reserved address 0x898

// Reserved address 0x89c

// Reserved address 0x8a0

// Reserved address 0x8a4

// Reserved address 0x8a8

// Reserved address 0x8ac

// Reserved address 0x8b0

// Reserved address 0x8b4

// Reserved address 0x8b8

// Reserved address 0x8bc

// Reserved address 0x8c0

// Reserved address 0x8c4

// Reserved address 0x8c8

// Reserved address 0x8cc

// Reserved address 0x8d0

// Reserved address 0x8d4

// Reserved address 0x8d8

// Reserved address 0x8dc

// Reserved address 0x8e0

// Reserved address 0x8e4

// Reserved address 0x8e8

// Reserved address 0x8ec

// Reserved address 0x8f0

// Reserved address 0x8f4

// Reserved address 0x8f8

// Reserved address 0x8fc

// Reserved address 0x900

// Reserved address 0x904

// Reserved address 0x908

// Reserved address 0x90c

// Reserved address 0x910

// Reserved address 0x914

// Reserved address 0x918

// Reserved address 0x91c

// Reserved address 0x920

// Reserved address 0x924

// Reserved address 0x928

// Reserved address 0x92c

// Reserved address 0x930

// Reserved address 0x934

// Reserved address 0x938

// Reserved address 0x93c

// Reserved address 0x940

// Reserved address 0x944

// Reserved address 0x948

// Reserved address 0x94c

// Reserved address 0x950

// Reserved address 0x954

// Reserved address 0x958

// Reserved address 0x95c

// Reserved address 0x960

// Reserved address 0x964

// Reserved address 0x968

// Reserved address 0x96c

// Reserved address 0x970

// Reserved address 0x974

// Reserved address 0x978

// Reserved address 0x97c

// Reserved address 0x980

// Reserved address 0x984

// Reserved address 0x988

// Reserved address 0x98c

// Reserved address 0x990

// Reserved address 0x994

// Reserved address 0x998

// Reserved address 0x99c

// Reserved address 0x9a0

// Reserved address 0x9a4

// Reserved address 0x9a8

// Reserved address 0x9ac

// Reserved address 0x9b0

// Reserved address 0x9b4

// Reserved address 0x9b8

// Reserved address 0x9bc

// Reserved address 0x9c0

// Reserved address 0x9c4

// Reserved address 0x9c8

// Reserved address 0x9cc

// Reserved address 0x9d0

// Reserved address 0x9d4

// Reserved address 0x9d8

// Reserved address 0x9dc

// Reserved address 0x9e0

// Reserved address 0x9e4

// Reserved address 0x9e8

// Reserved address 0x9ec

// Reserved address 0x9f0

// Reserved address 0x9f4

// Reserved address 0x9f8

// Reserved address 0x9fc

// Reserved address 0xa00

// Reserved address 0xa04

// Reserved address 0xa08

// Reserved address 0xa0c

// Reserved address 0xa10

// Reserved address 0xa14

// Reserved address 0xa18

// Reserved address 0xa1c

// Reserved address 0xa20

// Reserved address 0xa24

// Reserved address 0xa28

// Reserved address 0xa2c

// Reserved address 0xa30

// Reserved address 0xa34

// Reserved address 0xa38

// Reserved address 0xa3c

// Reserved address 0xa40

// Reserved address 0xa44

// Reserved address 0xa48

// Reserved address 0xa4c

// Reserved address 0xa50

// Reserved address 0xa54

// Reserved address 0xa58

// Reserved address 0xa5c

// Reserved address 0xa60

// Reserved address 0xa64

// Reserved address 0xa68

// Reserved address 0xa6c

// Reserved address 0xa70

// Reserved address 0xa74

// Reserved address 0xa78

// Reserved address 0xa7c

// Reserved address 0xa80

// Reserved address 0xa84

// Reserved address 0xa88

// Reserved address 0xa8c

// Reserved address 0xa90

// Reserved address 0xa94

// Reserved address 0xa98

// Reserved address 0xa9c

// Reserved address 0xaa0

// Reserved address 0xaa4

// Reserved address 0xaa8

// Reserved address 0xaac

// Reserved address 0xab0

// Reserved address 0xab4

// Reserved address 0xab8

// Reserved address 0xabc

// Reserved address 0xac0

// Reserved address 0xac4

// Reserved address 0xac8

// Reserved address 0xacc

// Reserved address 0xad0

// Reserved address 0xad4

// Reserved address 0xad8

// Reserved address 0xadc

// Reserved address 0xae0

// Reserved address 0xae4

// Reserved address 0xae8

// Reserved address 0xaec

// Reserved address 0xaf0

// Reserved address 0xaf4

// Reserved address 0xaf8

// Reserved address 0xafc

// Reserved address 0xb00

// Reserved address 0xb04

// Reserved address 0xb08

// Reserved address 0xb0c

// Reserved address 0xb10

// Reserved address 0xb14

// Reserved address 0xb18

// Reserved address 0xb1c

// Reserved address 0xb20

// Reserved address 0xb24

// Reserved address 0xb28

// Reserved address 0xb2c

// Reserved address 0xb30

// Reserved address 0xb34

// Reserved address 0xb38

// Reserved address 0xb3c

// Reserved address 0xb40

// Reserved address 0xb44

// Reserved address 0xb48

// Reserved address 0xb4c

// Reserved address 0xb50

// Reserved address 0xb54

// Reserved address 0xb58

// Reserved address 0xb5c

// Reserved address 0xb60

// Reserved address 0xb64

// Reserved address 0xb68

// Reserved address 0xb6c

// Reserved address 0xb70

// Reserved address 0xb74

// Reserved address 0xb78

// Reserved address 0xb7c

// Reserved address 0xb80

// Reserved address 0xb84

// Reserved address 0xb88

// Reserved address 0xb8c

// Reserved address 0xb90

// Reserved address 0xb94

// Reserved address 0xb98

// Reserved address 0xb9c

// Reserved address 0xba0

// Reserved address 0xba4

// Reserved address 0xba8

// Reserved address 0xbac

// Reserved address 0xbb0

// Reserved address 0xbb4

// Reserved address 0xbb8

// Reserved address 0xbbc

// Reserved address 0xbc0

// Reserved address 0xbc4

// Reserved address 0xbc8

// Reserved address 0xbcc

// Reserved address 0xbd0

// Reserved address 0xbd4

// Reserved address 0xbd8

// Reserved address 0xbdc

// Reserved address 0xbe0

// Reserved address 0xbe4

// Reserved address 0xbe8

// Reserved address 0xbec

// Reserved address 0xbf0

// Reserved address 0xbf4

// Reserved address 0xbf8

// Reserved address 0xbfc

// Reserved address 0xc00

// Reserved address 0xc04

// Reserved address 0xc08

// Reserved address 0xc0c

// Reserved address 0xc10

// Reserved address 0xc14

// Reserved address 0xc18

// Reserved address 0xc1c

// Reserved address 0xc20

// Reserved address 0xc24

// Reserved address 0xc28

// Reserved address 0xc2c

// Reserved address 0xc30

// Reserved address 0xc34

// Reserved address 0xc38

// Reserved address 0xc3c

// Reserved address 0xc40

// Reserved address 0xc44

// Reserved address 0xc48

// Reserved address 0xc4c

// Reserved address 0xc50

// Reserved address 0xc54

// Reserved address 0xc58

// Reserved address 0xc5c

// Reserved address 0xc60

// Reserved address 0xc64

// Reserved address 0xc68

// Reserved address 0xc6c

// Reserved address 0xc70

// Reserved address 0xc74

// Reserved address 0xc78

// Reserved address 0xc7c

// Reserved address 0xc80

// Reserved address 0xc84

// Reserved address 0xc88

// Reserved address 0xc8c

// Reserved address 0xc90

// Reserved address 0xc94

// Reserved address 0xc98

// Reserved address 0xc9c

// Reserved address 0xca0

// Reserved address 0xca4

// Reserved address 0xca8

// Reserved address 0xcac

// Reserved address 0xcb0

// Reserved address 0xcb4

// Reserved address 0xcb8

// Reserved address 0xcbc

// Reserved address 0xcc0

// Reserved address 0xcc4

// Reserved address 0xcc8

// Reserved address 0xccc

// Reserved address 0xcd0

// Reserved address 0xcd4

// Reserved address 0xcd8

// Reserved address 0xcdc

// Reserved address 0xce0

// Reserved address 0xce4

// Reserved address 0xce8

// Reserved address 0xcec

// Reserved address 0xcf0

// Reserved address 0xcf4

// Reserved address 0xcf8

// Reserved address 0xcfc

// Reserved address 0xd00

// Reserved address 0xd04

// Reserved address 0xd08

// Reserved address 0xd0c

// Reserved address 0xd10

// Reserved address 0xd14

// Reserved address 0xd18

// Reserved address 0xd1c

// Reserved address 0xd20

// Reserved address 0xd24

// Reserved address 0xd28

// Reserved address 0xd2c

// Reserved address 0xd30

// Reserved address 0xd34

// Reserved address 0xd38

// Reserved address 0xd3c

// Reserved address 0xd40

// Reserved address 0xd44

// Reserved address 0xd48

// Reserved address 0xd4c

// Reserved address 0xd50

// Reserved address 0xd54

// Reserved address 0xd58

// Reserved address 0xd5c

// Reserved address 0xd60

// Reserved address 0xd64

// Reserved address 0xd68

// Reserved address 0xd6c

// Reserved address 0xd70

// Reserved address 0xd74

// Reserved address 0xd78

// Reserved address 0xd7c

// Reserved address 0xd80

// Reserved address 0xd84

// Reserved address 0xd88

// Reserved address 0xd8c

// Reserved address 0xd90

// Reserved address 0xd94

// Reserved address 0xd98

// Reserved address 0xd9c

// Reserved address 0xda0

// Reserved address 0xda4

// Reserved address 0xda8

// Reserved address 0xdac

// Reserved address 0xdb0

// Reserved address 0xdb4

// Reserved address 0xdb8

// Reserved address 0xdbc

// Reserved address 0xdc0

// Reserved address 0xdc4

// Reserved address 0xdc8

// Reserved address 0xdcc

// Reserved address 0xdd0

// Reserved address 0xdd4

// Reserved address 0xdd8

// Reserved address 0xddc

// Reserved address 0xde0

// Reserved address 0xde4

// Reserved address 0xde8

// Reserved address 0xdec

// Reserved address 0xdf0

// Reserved address 0xdf4

// Reserved address 0xdf8

// Reserved address 0xdfc

// Reserved address 0xe00

// Reserved address 0xe04

// Reserved address 0xe08

// Reserved address 0xe0c

// Reserved address 0xe10

// Reserved address 0xe14

// Reserved address 0xe18

// Reserved address 0xe1c

// Reserved address 0xe20

// Reserved address 0xe24

// Reserved address 0xe28

// Reserved address 0xe2c

// Reserved address 0xe30

// Reserved address 0xe34

// Reserved address 0xe38

// Reserved address 0xe3c

// Reserved address 0xe40

// Reserved address 0xe44

// Reserved address 0xe48

// Reserved address 0xe4c

// Reserved address 0xe50

// Reserved address 0xe54

// Reserved address 0xe58

// Reserved address 0xe5c

// Reserved address 0xe60

// Reserved address 0xe64

// Reserved address 0xe68

// Reserved address 0xe6c

// Reserved address 0xe70

// Reserved address 0xe74

// Reserved address 0xe78

// Reserved address 0xe7c

// Reserved address 0xe80

// Reserved address 0xe84

// Reserved address 0xe88

// Reserved address 0xe8c

// Reserved address 0xe90

// Reserved address 0xe94

// Reserved address 0xe98

// Reserved address 0xe9c

// Reserved address 0xea0

// Reserved address 0xea4

// Reserved address 0xea8

// Reserved address 0xeac

// Reserved address 0xeb0

// Reserved address 0xeb4

// Reserved address 0xeb8

// Reserved address 0xebc

// Reserved address 0xec0

// Reserved address 0xec4

// Reserved address 0xec8

// Reserved address 0xecc

// Reserved address 0xed0

// Reserved address 0xed4

// Reserved address 0xed8

// Reserved address 0xedc

// Reserved address 0xee0

// Reserved address 0xee4

// Reserved address 0xee8

// Reserved address 0xeec

// Reserved address 0xef0

// Reserved address 0xef4

// Reserved address 0xef8

// Reserved address 0xefc

// Register APS_VIC_VICADDRESS_0
#define APS_VIC_VICADDRESS_0                    MK_ADDR_CONST(0xf00)
#define APS_VIC_VICADDRESS_0_SECURE                     0x0
#define APS_VIC_VICADDRESS_0_DUAL                       0x0
#define APS_VIC_VICADDRESS_0_SCR                        0
#define APS_VIC_VICADDRESS_0_SCRREG                     0
#define APS_VIC_VICADDRESS_0_WORD_COUNT                         0x1
#define APS_VIC_VICADDRESS_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define APS_VIC_VICADDRESS_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICADDRESS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define APS_VIC_VICADDRESS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define APS_VIC_VICADDRESS_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICADDRESS_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICADDRESS_0_VICADDRESS_SHIFT                   MK_SHIFT_CONST(0)
#define APS_VIC_VICADDRESS_0_VICADDRESS_FIELD                   MK_FIELD_CONST(0xffffffff, APS_VIC_VICADDRESS_0_VICADDRESS_SHIFT)
#define APS_VIC_VICADDRESS_0_VICADDRESS_RANGE                   31:0
#define APS_VIC_VICADDRESS_0_VICADDRESS_MSB                     MK_SHIFT_CONST(31)
#define APS_VIC_VICADDRESS_0_VICADDRESS_LSB                     MK_SHIFT_CONST(0)
#define APS_VIC_VICADDRESS_0_VICADDRESS_WOFFSET                 0x0
#define APS_VIC_VICADDRESS_0_VICADDRESS_DEFAULT                 MK_MASK_CONST(0x0)
#define APS_VIC_VICADDRESS_0_VICADDRESS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
#define APS_VIC_VICADDRESS_0_VICADDRESS_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define APS_VIC_VICADDRESS_0_VICADDRESS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define APS_VIC_VICADDRESS_0_VICADDRESS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define APS_VIC_VICADDRESS_0_VICADDRESS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Reserved address 0xf04

// Reserved address 0xf08

// Reserved address 0xf0c

// Reserved address 0xf10

// Reserved address 0xf14

// Reserved address 0xf18

// Reserved address 0xf1c

// Reserved address 0xf20

// Reserved address 0xf24

// Reserved address 0xf28

// Reserved address 0xf2c

// Reserved address 0xf30

// Reserved address 0xf34

// Reserved address 0xf38

// Reserved address 0xf3c

// Reserved address 0xf40

// Reserved address 0xf44

// Reserved address 0xf48

// Reserved address 0xf4c

// Reserved address 0xf50

// Reserved address 0xf54

// Reserved address 0xf58

// Reserved address 0xf5c

// Reserved address 0xf60

// Reserved address 0xf64

// Reserved address 0xf68

// Reserved address 0xf6c

// Reserved address 0xf70

// Reserved address 0xf74

// Reserved address 0xf78

// Reserved address 0xf7c

// Reserved address 0xf80

// Reserved address 0xf84

// Reserved address 0xf88

// Reserved address 0xf8c

// Reserved address 0xf90

// Reserved address 0xf94

// Reserved address 0xf98

// Reserved address 0xf9c

// Reserved address 0xfa0

// Reserved address 0xfa4

// Reserved address 0xfa8

// Reserved address 0xfac

// Reserved address 0xfb0

// Reserved address 0xfb4

// Reserved address 0xfb8

// Reserved address 0xfbc

// Reserved address 0xfc0

// Reserved address 0xfc4

// Reserved address 0xfc8

// Reserved address 0xfcc

// Reserved address 0xfd0

// Reserved address 0xfd4

// Reserved address 0xfd8

// Reserved address 0xfdc

// Register APS_VIC_VICPERIPHID0_0
#define APS_VIC_VICPERIPHID0_0                  MK_ADDR_CONST(0xfe0)
#define APS_VIC_VICPERIPHID0_0_SECURE                   0x0
#define APS_VIC_VICPERIPHID0_0_DUAL                     0x0
#define APS_VIC_VICPERIPHID0_0_SCR                      0
#define APS_VIC_VICPERIPHID0_0_SCRREG                   0
#define APS_VIC_VICPERIPHID0_0_WORD_COUNT                       0x1
#define APS_VIC_VICPERIPHID0_0_RESET_VAL                        MK_MASK_CONST(0x92)
#define APS_VIC_VICPERIPHID0_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define APS_VIC_VICPERIPHID0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID0_0_READ_MASK                        MK_MASK_CONST(0xff)
#define APS_VIC_VICPERIPHID0_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_FIELD                       MK_FIELD_CONST(0xff, APS_VIC_VICPERIPHID0_0_VICPERIPHID0_SHIFT)
#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_RANGE                       7:0
#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_MSB                 MK_SHIFT_CONST(7)
#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_WOFFSET                     0x0
#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_DEFAULT                     MK_MASK_CONST(0x92)
#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICPERIPHID1_0
#define APS_VIC_VICPERIPHID1_0                  MK_ADDR_CONST(0xfe4)
#define APS_VIC_VICPERIPHID1_0_SECURE                   0x0
#define APS_VIC_VICPERIPHID1_0_DUAL                     0x0
#define APS_VIC_VICPERIPHID1_0_SCR                      0
#define APS_VIC_VICPERIPHID1_0_SCRREG                   0
#define APS_VIC_VICPERIPHID1_0_WORD_COUNT                       0x1
#define APS_VIC_VICPERIPHID1_0_RESET_VAL                        MK_MASK_CONST(0x11)
#define APS_VIC_VICPERIPHID1_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define APS_VIC_VICPERIPHID1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID1_0_READ_MASK                        MK_MASK_CONST(0xff)
#define APS_VIC_VICPERIPHID1_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_FIELD                       MK_FIELD_CONST(0xff, APS_VIC_VICPERIPHID1_0_VICPERIPHID1_SHIFT)
#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_RANGE                       7:0
#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_MSB                 MK_SHIFT_CONST(7)
#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_WOFFSET                     0x0
#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_DEFAULT                     MK_MASK_CONST(0x11)
#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICPERIPHID2_0
#define APS_VIC_VICPERIPHID2_0                  MK_ADDR_CONST(0xfe8)
#define APS_VIC_VICPERIPHID2_0_SECURE                   0x0
#define APS_VIC_VICPERIPHID2_0_DUAL                     0x0
#define APS_VIC_VICPERIPHID2_0_SCR                      0
#define APS_VIC_VICPERIPHID2_0_SCRREG                   0
#define APS_VIC_VICPERIPHID2_0_WORD_COUNT                       0x1
#define APS_VIC_VICPERIPHID2_0_RESET_VAL                        MK_MASK_CONST(0x4)
#define APS_VIC_VICPERIPHID2_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define APS_VIC_VICPERIPHID2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID2_0_READ_MASK                        MK_MASK_CONST(0xff)
#define APS_VIC_VICPERIPHID2_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_FIELD                       MK_FIELD_CONST(0xff, APS_VIC_VICPERIPHID2_0_VICPERIPHID2_SHIFT)
#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_RANGE                       7:0
#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_MSB                 MK_SHIFT_CONST(7)
#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_WOFFSET                     0x0
#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_DEFAULT                     MK_MASK_CONST(0x4)
#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICPERIPHID3_0
#define APS_VIC_VICPERIPHID3_0                  MK_ADDR_CONST(0xfec)
#define APS_VIC_VICPERIPHID3_0_SECURE                   0x0
#define APS_VIC_VICPERIPHID3_0_DUAL                     0x0
#define APS_VIC_VICPERIPHID3_0_SCR                      0
#define APS_VIC_VICPERIPHID3_0_SCRREG                   0
#define APS_VIC_VICPERIPHID3_0_WORD_COUNT                       0x1
#define APS_VIC_VICPERIPHID3_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID3_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define APS_VIC_VICPERIPHID3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID3_0_READ_MASK                        MK_MASK_CONST(0xff)
#define APS_VIC_VICPERIPHID3_0_WRITE_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_SHIFT                       MK_SHIFT_CONST(0)
#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_FIELD                       MK_FIELD_CONST(0xff, APS_VIC_VICPERIPHID3_0_VICPERIPHID3_SHIFT)
#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_RANGE                       7:0
#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_MSB                 MK_SHIFT_CONST(7)
#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_LSB                 MK_SHIFT_CONST(0)
#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_WOFFSET                     0x0
#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_DEFAULT                     MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register APS_VIC_VICPCELLID0_0
#define APS_VIC_VICPCELLID0_0                   MK_ADDR_CONST(0xff0)
#define APS_VIC_VICPCELLID0_0_SECURE                    0x0
#define APS_VIC_VICPCELLID0_0_DUAL                      0x0
#define APS_VIC_VICPCELLID0_0_SCR                       0
#define APS_VIC_VICPCELLID0_0_SCRREG                    0
#define APS_VIC_VICPCELLID0_0_WORD_COUNT                        0x1
#define APS_VIC_VICPCELLID0_0_RESET_VAL                         MK_MASK_CONST(0xd)
#define APS_VIC_VICPCELLID0_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define APS_VIC_VICPCELLID0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID0_0_READ_MASK                         MK_MASK_CONST(0xff)
#define APS_VIC_VICPCELLID0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID0_0_VICPCELLID0_SHIFT                 MK_SHIFT_CONST(0)
#define APS_VIC_VICPCELLID0_0_VICPCELLID0_FIELD                 MK_FIELD_CONST(0xff, APS_VIC_VICPCELLID0_0_VICPCELLID0_SHIFT)
#define APS_VIC_VICPCELLID0_0_VICPCELLID0_RANGE                 7:0
#define APS_VIC_VICPCELLID0_0_VICPCELLID0_MSB                   MK_SHIFT_CONST(7)
#define APS_VIC_VICPCELLID0_0_VICPCELLID0_LSB                   MK_SHIFT_CONST(0)
#define APS_VIC_VICPCELLID0_0_VICPCELLID0_WOFFSET                       0x0
#define APS_VIC_VICPCELLID0_0_VICPCELLID0_DEFAULT                       MK_MASK_CONST(0xd)
#define APS_VIC_VICPCELLID0_0_VICPCELLID0_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define APS_VIC_VICPCELLID0_0_VICPCELLID0_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID0_0_VICPCELLID0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID0_0_VICPCELLID0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID0_0_VICPCELLID0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register APS_VIC_VICPCELLID1_0
#define APS_VIC_VICPCELLID1_0                   MK_ADDR_CONST(0xff4)
#define APS_VIC_VICPCELLID1_0_SECURE                    0x0
#define APS_VIC_VICPCELLID1_0_DUAL                      0x0
#define APS_VIC_VICPCELLID1_0_SCR                       0
#define APS_VIC_VICPCELLID1_0_SCRREG                    0
#define APS_VIC_VICPCELLID1_0_WORD_COUNT                        0x1
#define APS_VIC_VICPCELLID1_0_RESET_VAL                         MK_MASK_CONST(0xf0)
#define APS_VIC_VICPCELLID1_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define APS_VIC_VICPCELLID1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID1_0_READ_MASK                         MK_MASK_CONST(0xff)
#define APS_VIC_VICPCELLID1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID1_0_VICPCELLID1_SHIFT                 MK_SHIFT_CONST(0)
#define APS_VIC_VICPCELLID1_0_VICPCELLID1_FIELD                 MK_FIELD_CONST(0xff, APS_VIC_VICPCELLID1_0_VICPCELLID1_SHIFT)
#define APS_VIC_VICPCELLID1_0_VICPCELLID1_RANGE                 7:0
#define APS_VIC_VICPCELLID1_0_VICPCELLID1_MSB                   MK_SHIFT_CONST(7)
#define APS_VIC_VICPCELLID1_0_VICPCELLID1_LSB                   MK_SHIFT_CONST(0)
#define APS_VIC_VICPCELLID1_0_VICPCELLID1_WOFFSET                       0x0
#define APS_VIC_VICPCELLID1_0_VICPCELLID1_DEFAULT                       MK_MASK_CONST(0xf0)
#define APS_VIC_VICPCELLID1_0_VICPCELLID1_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define APS_VIC_VICPCELLID1_0_VICPCELLID1_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID1_0_VICPCELLID1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID1_0_VICPCELLID1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID1_0_VICPCELLID1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register APS_VIC_VICPCELLID2_0
#define APS_VIC_VICPCELLID2_0                   MK_ADDR_CONST(0xff8)
#define APS_VIC_VICPCELLID2_0_SECURE                    0x0
#define APS_VIC_VICPCELLID2_0_DUAL                      0x0
#define APS_VIC_VICPCELLID2_0_SCR                       0
#define APS_VIC_VICPCELLID2_0_SCRREG                    0
#define APS_VIC_VICPCELLID2_0_WORD_COUNT                        0x1
#define APS_VIC_VICPCELLID2_0_RESET_VAL                         MK_MASK_CONST(0x5)
#define APS_VIC_VICPCELLID2_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define APS_VIC_VICPCELLID2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID2_0_READ_MASK                         MK_MASK_CONST(0xff)
#define APS_VIC_VICPCELLID2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID2_0_VICPCELLID2_SHIFT                 MK_SHIFT_CONST(0)
#define APS_VIC_VICPCELLID2_0_VICPCELLID2_FIELD                 MK_FIELD_CONST(0xff, APS_VIC_VICPCELLID2_0_VICPCELLID2_SHIFT)
#define APS_VIC_VICPCELLID2_0_VICPCELLID2_RANGE                 7:0
#define APS_VIC_VICPCELLID2_0_VICPCELLID2_MSB                   MK_SHIFT_CONST(7)
#define APS_VIC_VICPCELLID2_0_VICPCELLID2_LSB                   MK_SHIFT_CONST(0)
#define APS_VIC_VICPCELLID2_0_VICPCELLID2_WOFFSET                       0x0
#define APS_VIC_VICPCELLID2_0_VICPCELLID2_DEFAULT                       MK_MASK_CONST(0x5)
#define APS_VIC_VICPCELLID2_0_VICPCELLID2_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define APS_VIC_VICPCELLID2_0_VICPCELLID2_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID2_0_VICPCELLID2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID2_0_VICPCELLID2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID2_0_VICPCELLID2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register APS_VIC_VICPCELLID3_0
#define APS_VIC_VICPCELLID3_0                   MK_ADDR_CONST(0xffc)
#define APS_VIC_VICPCELLID3_0_SECURE                    0x0
#define APS_VIC_VICPCELLID3_0_DUAL                      0x0
#define APS_VIC_VICPCELLID3_0_SCR                       0
#define APS_VIC_VICPCELLID3_0_SCRREG                    0
#define APS_VIC_VICPCELLID3_0_WORD_COUNT                        0x1
#define APS_VIC_VICPCELLID3_0_RESET_VAL                         MK_MASK_CONST(0xb1)
#define APS_VIC_VICPCELLID3_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define APS_VIC_VICPCELLID3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID3_0_READ_MASK                         MK_MASK_CONST(0xff)
#define APS_VIC_VICPCELLID3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID3_0_VICPCELLID3_SHIFT                 MK_SHIFT_CONST(0)
#define APS_VIC_VICPCELLID3_0_VICPCELLID3_FIELD                 MK_FIELD_CONST(0xff, APS_VIC_VICPCELLID3_0_VICPCELLID3_SHIFT)
#define APS_VIC_VICPCELLID3_0_VICPCELLID3_RANGE                 7:0
#define APS_VIC_VICPCELLID3_0_VICPCELLID3_MSB                   MK_SHIFT_CONST(7)
#define APS_VIC_VICPCELLID3_0_VICPCELLID3_LSB                   MK_SHIFT_CONST(0)
#define APS_VIC_VICPCELLID3_0_VICPCELLID3_WOFFSET                       0x0
#define APS_VIC_VICPCELLID3_0_VICPCELLID3_DEFAULT                       MK_MASK_CONST(0xb1)
#define APS_VIC_VICPCELLID3_0_VICPCELLID3_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define APS_VIC_VICPCELLID3_0_VICPCELLID3_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID3_0_VICPCELLID3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID3_0_VICPCELLID3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define APS_VIC_VICPCELLID3_0_VICPCELLID3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARAPS_VIC_REGS(_op_) \
_op_(APS_VIC_VICIRQSTATUS_0) \
_op_(APS_VIC_VICFIQSTATUS_0) \
_op_(APS_VIC_VICRAWINTR_0) \
_op_(APS_VIC_VICINTSELECT_0) \
_op_(APS_VIC_VICINTENABLE_0) \
_op_(APS_VIC_VICINTENCLEAR_0) \
_op_(APS_VIC_VICSOFTINT_0) \
_op_(APS_VIC_VICSOFTINTCLEAR_0) \
_op_(APS_VIC_VICPROTECTION_0) \
_op_(APS_VIC_VICSWPRIORITY_0) \
_op_(APS_VIC_VICPRIORITYDAISY_0) \
_op_(APS_VIC_VICVECTADDR0_0) \
_op_(APS_VIC_VICVECTADDR1_0) \
_op_(APS_VIC_VICVECTADDR2_0) \
_op_(APS_VIC_VICVECTADDR3_0) \
_op_(APS_VIC_VICVECTADDR4_0) \
_op_(APS_VIC_VICVECTADDR5_0) \
_op_(APS_VIC_VICVECTADDR6_0) \
_op_(APS_VIC_VICVECTADDR7_0) \
_op_(APS_VIC_VICVECTADDR8_0) \
_op_(APS_VIC_VICVECTADDR9_0) \
_op_(APS_VIC_VICVECTADDR10_0) \
_op_(APS_VIC_VICVECTADDR11_0) \
_op_(APS_VIC_VICVECTADDR12_0) \
_op_(APS_VIC_VICVECTADDR13_0) \
_op_(APS_VIC_VICVECTADDR14_0) \
_op_(APS_VIC_VICVECTADDR15_0) \
_op_(APS_VIC_VICVECTADDR16_0) \
_op_(APS_VIC_VICVECTADDR17_0) \
_op_(APS_VIC_VICVECTADDR18_0) \
_op_(APS_VIC_VICVECTADDR19_0) \
_op_(APS_VIC_VICVECTADDR20_0) \
_op_(APS_VIC_VICVECTADDR21_0) \
_op_(APS_VIC_VICVECTADDR22_0) \
_op_(APS_VIC_VICVECTADDR23_0) \
_op_(APS_VIC_VICVECTADDR24_0) \
_op_(APS_VIC_VICVECTADDR25_0) \
_op_(APS_VIC_VICVECTADDR26_0) \
_op_(APS_VIC_VICVECTADDR27_0) \
_op_(APS_VIC_VICVECTADDR28_0) \
_op_(APS_VIC_VICVECTADDR29_0) \
_op_(APS_VIC_VICVECTADDR30_0) \
_op_(APS_VIC_VICVECTADDR31_0) \
_op_(APS_VIC_VICVECTPRIORITY0_0) \
_op_(APS_VIC_VICVECTPRIORITY1_0) \
_op_(APS_VIC_VICVECTPRIORITY2_0) \
_op_(APS_VIC_VICVECTPRIORITY3_0) \
_op_(APS_VIC_VICVECTPRIORITY4_0) \
_op_(APS_VIC_VICVECTPRIORITY5_0) \
_op_(APS_VIC_VICVECTPRIORITY6_0) \
_op_(APS_VIC_VICVECTPRIORITY7_0) \
_op_(APS_VIC_VICVECTPRIORITY8_0) \
_op_(APS_VIC_VICVECTPRIORITY9_0) \
_op_(APS_VIC_VICVECTPRIORITY10_0) \
_op_(APS_VIC_VICVECTPRIORITY11_0) \
_op_(APS_VIC_VICVECTPRIORITY12_0) \
_op_(APS_VIC_VICVECTPRIORITY13_0) \
_op_(APS_VIC_VICVECTPRIORITY14_0) \
_op_(APS_VIC_VICVECTPRIORITY15_0) \
_op_(APS_VIC_VICVECTPRIORITY16_0) \
_op_(APS_VIC_VICVECTPRIORITY17_0) \
_op_(APS_VIC_VICVECTPRIORITY18_0) \
_op_(APS_VIC_VICVECTPRIORITY19_0) \
_op_(APS_VIC_VICVECTPRIORITY20_0) \
_op_(APS_VIC_VICVECTPRIORITY21_0) \
_op_(APS_VIC_VICVECTPRIORITY22_0) \
_op_(APS_VIC_VICVECTPRIORITY23_0) \
_op_(APS_VIC_VICVECTPRIORITY24_0) \
_op_(APS_VIC_VICVECTPRIORITY25_0) \
_op_(APS_VIC_VICVECTPRIORITY26_0) \
_op_(APS_VIC_VICVECTPRIORITY27_0) \
_op_(APS_VIC_VICVECTPRIORITY28_0) \
_op_(APS_VIC_VICVECTPRIORITY29_0) \
_op_(APS_VIC_VICVECTPRIORITY30_0) \
_op_(APS_VIC_VICVECTPRIORITY31_0) \
_op_(APS_VIC_VICITCR_0) \
_op_(APS_VIC_VICITIP1_0) \
_op_(APS_VIC_VICITIP2_0) \
_op_(APS_VIC_VICITOP1_0) \
_op_(APS_VIC_VICITOP2_0) \
_op_(APS_VIC_VICINTSSTATUS_0) \
_op_(APS_VIC_VICINTSSTATUSCLEAR_0) \
_op_(APS_VIC_VICADDRESS_0) \
_op_(APS_VIC_VICPERIPHID0_0) \
_op_(APS_VIC_VICPERIPHID1_0) \
_op_(APS_VIC_VICPERIPHID2_0) \
_op_(APS_VIC_VICPERIPHID3_0) \
_op_(APS_VIC_VICPCELLID0_0) \
_op_(APS_VIC_VICPCELLID1_0) \
_op_(APS_VIC_VICPCELLID2_0) \
_op_(APS_VIC_VICPCELLID3_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_APS_VIC    0x00000000

//
// ARAPS_VIC REGISTER BANKS
//

#define APS_VIC0_FIRST_REG 0x0000 // APS_VIC_VICIRQSTATUS_0
#define APS_VIC0_LAST_REG 0x0028 // APS_VIC_VICPRIORITYDAISY_0
#define APS_VIC1_FIRST_REG 0x0100 // APS_VIC_VICVECTADDR0_0
#define APS_VIC1_LAST_REG 0x017c // APS_VIC_VICVECTADDR31_0
#define APS_VIC2_FIRST_REG 0x0200 // APS_VIC_VICVECTPRIORITY0_0
#define APS_VIC2_LAST_REG 0x027c // APS_VIC_VICVECTPRIORITY31_0
#define APS_VIC3_FIRST_REG 0x0300 // APS_VIC_VICITCR_0
#define APS_VIC3_LAST_REG 0x0318 // APS_VIC_VICINTSSTATUSCLEAR_0
#define APS_VIC4_FIRST_REG 0x0f00 // APS_VIC_VICADDRESS_0
#define APS_VIC4_LAST_REG 0x0f00 // APS_VIC_VICADDRESS_0
#define APS_VIC5_FIRST_REG 0x0fe0 // APS_VIC_VICPERIPHID0_0
#define APS_VIC5_LAST_REG 0x0ffc // APS_VIC_VICPCELLID3_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARAPS_VIC_H_INC
