//
// Copyright (c) 2021 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARGPIO_AON_H_INC
#define ARGPIO_AON_H_INC
#define NV_MOBILE_ARGPIO_AON_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARGPIO_AON_H_SCRREG_NOMENCLATURE EXACT


// Register GPIO_EE_ENABLE_CONFIG_00_0
#define GPIO_EE_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x1000)
#define GPIO_EE_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_EE_ENABLE_CONFIG_00_0_DUAL                         0x0
#define GPIO_EE_ENABLE_CONFIG_00_0_SCR                  GPIO_EE_SCR_00_0
#define GPIO_EE_ENABLE_CONFIG_00_0_SCRREG                       GPIO_EE_SCR_00_0
#define GPIO_EE_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_EE_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_EE_DEBOUNCE_THRESHOLD_00_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x1004)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_EE_SCR_00_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_EE_SCR_00_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_INPUT_00_0
#define GPIO_EE_INPUT_00_0                      MK_ADDR_CONST(0x1008)
#define GPIO_EE_INPUT_00_0_SECURE                       0x0
#define GPIO_EE_INPUT_00_0_DUAL                         0x0
#define GPIO_EE_INPUT_00_0_SCR                  GPIO_EE_SCR_00_0
#define GPIO_EE_INPUT_00_0_SCRREG                       GPIO_EE_SCR_00_0
#define GPIO_EE_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_EE_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_EE_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_EE_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_EE_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_OUTPUT_CONTROL_00_0
#define GPIO_EE_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x100c)
#define GPIO_EE_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_EE_OUTPUT_CONTROL_00_0_DUAL                        0x0
#define GPIO_EE_OUTPUT_CONTROL_00_0_SCR                         GPIO_EE_SCR_00_0
#define GPIO_EE_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_EE_SCR_00_0
#define GPIO_EE_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_EE_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_EE_OUTPUT_VALUE_00_0
#define GPIO_EE_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x1010)
#define GPIO_EE_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_EE_OUTPUT_VALUE_00_0_DUAL                  0x0
#define GPIO_EE_OUTPUT_VALUE_00_0_SCR                   GPIO_EE_SCR_00_0
#define GPIO_EE_OUTPUT_VALUE_00_0_SCRREG                        GPIO_EE_SCR_00_0
#define GPIO_EE_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_EE_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_CLEAR_00_0
#define GPIO_EE_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x1014)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_EE_INTERRUPT_CLEAR_00_0_DUAL                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_00_0_SCR                        GPIO_EE_SCR_00_0
#define GPIO_EE_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_EE_SCR_00_0
#define GPIO_EE_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_EE_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1018

// Reserved address 0x101c

// Register GPIO_EE_ENABLE_CONFIG_01_0
#define GPIO_EE_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x1020)
#define GPIO_EE_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_EE_ENABLE_CONFIG_01_0_DUAL                         0x0
#define GPIO_EE_ENABLE_CONFIG_01_0_SCR                  GPIO_EE_SCR_01_0
#define GPIO_EE_ENABLE_CONFIG_01_0_SCRREG                       GPIO_EE_SCR_01_0
#define GPIO_EE_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_EE_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_EE_DEBOUNCE_THRESHOLD_01_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x1024)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_EE_SCR_01_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_EE_SCR_01_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_INPUT_01_0
#define GPIO_EE_INPUT_01_0                      MK_ADDR_CONST(0x1028)
#define GPIO_EE_INPUT_01_0_SECURE                       0x0
#define GPIO_EE_INPUT_01_0_DUAL                         0x0
#define GPIO_EE_INPUT_01_0_SCR                  GPIO_EE_SCR_01_0
#define GPIO_EE_INPUT_01_0_SCRREG                       GPIO_EE_SCR_01_0
#define GPIO_EE_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_EE_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_EE_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_EE_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_EE_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_OUTPUT_CONTROL_01_0
#define GPIO_EE_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x102c)
#define GPIO_EE_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_EE_OUTPUT_CONTROL_01_0_DUAL                        0x0
#define GPIO_EE_OUTPUT_CONTROL_01_0_SCR                         GPIO_EE_SCR_01_0
#define GPIO_EE_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_EE_SCR_01_0
#define GPIO_EE_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_EE_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_EE_OUTPUT_VALUE_01_0
#define GPIO_EE_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x1030)
#define GPIO_EE_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_EE_OUTPUT_VALUE_01_0_DUAL                  0x0
#define GPIO_EE_OUTPUT_VALUE_01_0_SCR                   GPIO_EE_SCR_01_0
#define GPIO_EE_OUTPUT_VALUE_01_0_SCRREG                        GPIO_EE_SCR_01_0
#define GPIO_EE_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_EE_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_CLEAR_01_0
#define GPIO_EE_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x1034)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_EE_INTERRUPT_CLEAR_01_0_DUAL                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_01_0_SCR                        GPIO_EE_SCR_01_0
#define GPIO_EE_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_EE_SCR_01_0
#define GPIO_EE_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_EE_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1038

// Reserved address 0x103c

// Register GPIO_EE_ENABLE_CONFIG_02_0
#define GPIO_EE_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x1040)
#define GPIO_EE_ENABLE_CONFIG_02_0_SECURE                       0x0
#define GPIO_EE_ENABLE_CONFIG_02_0_DUAL                         0x0
#define GPIO_EE_ENABLE_CONFIG_02_0_SCR                  GPIO_EE_SCR_02_0
#define GPIO_EE_ENABLE_CONFIG_02_0_SCRREG                       GPIO_EE_SCR_02_0
#define GPIO_EE_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
#define GPIO_EE_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_EE_DEBOUNCE_THRESHOLD_02_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x1044)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_EE_SCR_02_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_EE_SCR_02_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_INPUT_02_0
#define GPIO_EE_INPUT_02_0                      MK_ADDR_CONST(0x1048)
#define GPIO_EE_INPUT_02_0_SECURE                       0x0
#define GPIO_EE_INPUT_02_0_DUAL                         0x0
#define GPIO_EE_INPUT_02_0_SCR                  GPIO_EE_SCR_02_0
#define GPIO_EE_INPUT_02_0_SCRREG                       GPIO_EE_SCR_02_0
#define GPIO_EE_INPUT_02_0_WORD_COUNT                   0x1
#define GPIO_EE_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_EE_INPUT_02_0_GPIO_IN_RANGE                        0:0
#define GPIO_EE_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_EE_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_OUTPUT_CONTROL_02_0
#define GPIO_EE_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x104c)
#define GPIO_EE_OUTPUT_CONTROL_02_0_SECURE                      0x0
#define GPIO_EE_OUTPUT_CONTROL_02_0_DUAL                        0x0
#define GPIO_EE_OUTPUT_CONTROL_02_0_SCR                         GPIO_EE_SCR_02_0
#define GPIO_EE_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_EE_SCR_02_0
#define GPIO_EE_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
#define GPIO_EE_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_EE_OUTPUT_VALUE_02_0
#define GPIO_EE_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x1050)
#define GPIO_EE_OUTPUT_VALUE_02_0_SECURE                        0x0
#define GPIO_EE_OUTPUT_VALUE_02_0_DUAL                  0x0
#define GPIO_EE_OUTPUT_VALUE_02_0_SCR                   GPIO_EE_SCR_02_0
#define GPIO_EE_OUTPUT_VALUE_02_0_SCRREG                        GPIO_EE_SCR_02_0
#define GPIO_EE_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
#define GPIO_EE_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_CLEAR_02_0
#define GPIO_EE_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x1054)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_SECURE                     0x0
#define GPIO_EE_INTERRUPT_CLEAR_02_0_DUAL                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_02_0_SCR                        GPIO_EE_SCR_02_0
#define GPIO_EE_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_EE_SCR_02_0
#define GPIO_EE_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
#define GPIO_EE_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1058

// Reserved address 0x105c

// Register GPIO_EE_ENABLE_CONFIG_03_0
#define GPIO_EE_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x1060)
#define GPIO_EE_ENABLE_CONFIG_03_0_SECURE                       0x0
#define GPIO_EE_ENABLE_CONFIG_03_0_DUAL                         0x0
#define GPIO_EE_ENABLE_CONFIG_03_0_SCR                  GPIO_EE_SCR_03_0
#define GPIO_EE_ENABLE_CONFIG_03_0_SCRREG                       GPIO_EE_SCR_03_0
#define GPIO_EE_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
#define GPIO_EE_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_EE_DEBOUNCE_THRESHOLD_03_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x1064)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_EE_SCR_03_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_EE_SCR_03_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_INPUT_03_0
#define GPIO_EE_INPUT_03_0                      MK_ADDR_CONST(0x1068)
#define GPIO_EE_INPUT_03_0_SECURE                       0x0
#define GPIO_EE_INPUT_03_0_DUAL                         0x0
#define GPIO_EE_INPUT_03_0_SCR                  GPIO_EE_SCR_03_0
#define GPIO_EE_INPUT_03_0_SCRREG                       GPIO_EE_SCR_03_0
#define GPIO_EE_INPUT_03_0_WORD_COUNT                   0x1
#define GPIO_EE_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_EE_INPUT_03_0_GPIO_IN_RANGE                        0:0
#define GPIO_EE_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_EE_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_OUTPUT_CONTROL_03_0
#define GPIO_EE_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x106c)
#define GPIO_EE_OUTPUT_CONTROL_03_0_SECURE                      0x0
#define GPIO_EE_OUTPUT_CONTROL_03_0_DUAL                        0x0
#define GPIO_EE_OUTPUT_CONTROL_03_0_SCR                         GPIO_EE_SCR_03_0
#define GPIO_EE_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_EE_SCR_03_0
#define GPIO_EE_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
#define GPIO_EE_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_EE_OUTPUT_VALUE_03_0
#define GPIO_EE_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x1070)
#define GPIO_EE_OUTPUT_VALUE_03_0_SECURE                        0x0
#define GPIO_EE_OUTPUT_VALUE_03_0_DUAL                  0x0
#define GPIO_EE_OUTPUT_VALUE_03_0_SCR                   GPIO_EE_SCR_03_0
#define GPIO_EE_OUTPUT_VALUE_03_0_SCRREG                        GPIO_EE_SCR_03_0
#define GPIO_EE_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
#define GPIO_EE_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_CLEAR_03_0
#define GPIO_EE_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x1074)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_SECURE                     0x0
#define GPIO_EE_INTERRUPT_CLEAR_03_0_DUAL                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_03_0_SCR                        GPIO_EE_SCR_03_0
#define GPIO_EE_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_EE_SCR_03_0
#define GPIO_EE_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
#define GPIO_EE_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1078

// Reserved address 0x107c

// Register GPIO_EE_ENABLE_CONFIG_04_0
#define GPIO_EE_ENABLE_CONFIG_04_0                      MK_ADDR_CONST(0x1080)
#define GPIO_EE_ENABLE_CONFIG_04_0_SECURE                       0x0
#define GPIO_EE_ENABLE_CONFIG_04_0_DUAL                         0x0
#define GPIO_EE_ENABLE_CONFIG_04_0_SCR                  GPIO_EE_SCR_04_0
#define GPIO_EE_ENABLE_CONFIG_04_0_SCRREG                       GPIO_EE_SCR_04_0
#define GPIO_EE_ENABLE_CONFIG_04_0_WORD_COUNT                   0x1
#define GPIO_EE_ENABLE_CONFIG_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_04_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_RANGE                 1:1
#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                       0x0
#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_EE_DEBOUNCE_THRESHOLD_04_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0                 MK_ADDR_CONST(0x1084)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_SECURE                  0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DUAL                    0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_SCR                     GPIO_EE_SCR_04_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_SCRREG                  GPIO_EE_SCR_04_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                      0x1
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_INPUT_04_0
#define GPIO_EE_INPUT_04_0                      MK_ADDR_CONST(0x1088)
#define GPIO_EE_INPUT_04_0_SECURE                       0x0
#define GPIO_EE_INPUT_04_0_DUAL                         0x0
#define GPIO_EE_INPUT_04_0_SCR                  GPIO_EE_SCR_04_0
#define GPIO_EE_INPUT_04_0_SCRREG                       GPIO_EE_SCR_04_0
#define GPIO_EE_INPUT_04_0_WORD_COUNT                   0x1
#define GPIO_EE_INPUT_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_04_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_INPUT_04_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_04_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_04_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_EE_INPUT_04_0_GPIO_IN_RANGE                        0:0
#define GPIO_EE_INPUT_04_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_04_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_04_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_EE_INPUT_04_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_04_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_04_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_OUTPUT_CONTROL_04_0
#define GPIO_EE_OUTPUT_CONTROL_04_0                     MK_ADDR_CONST(0x108c)
#define GPIO_EE_OUTPUT_CONTROL_04_0_SECURE                      0x0
#define GPIO_EE_OUTPUT_CONTROL_04_0_DUAL                        0x0
#define GPIO_EE_OUTPUT_CONTROL_04_0_SCR                         GPIO_EE_SCR_04_0
#define GPIO_EE_OUTPUT_CONTROL_04_0_SCRREG                      GPIO_EE_SCR_04_0
#define GPIO_EE_OUTPUT_CONTROL_04_0_WORD_COUNT                  0x1
#define GPIO_EE_OUTPUT_CONTROL_04_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_EE_OUTPUT_VALUE_04_0
#define GPIO_EE_OUTPUT_VALUE_04_0                       MK_ADDR_CONST(0x1090)
#define GPIO_EE_OUTPUT_VALUE_04_0_SECURE                        0x0
#define GPIO_EE_OUTPUT_VALUE_04_0_DUAL                  0x0
#define GPIO_EE_OUTPUT_VALUE_04_0_SCR                   GPIO_EE_SCR_04_0
#define GPIO_EE_OUTPUT_VALUE_04_0_SCRREG                        GPIO_EE_SCR_04_0
#define GPIO_EE_OUTPUT_VALUE_04_0_WORD_COUNT                    0x1
#define GPIO_EE_OUTPUT_VALUE_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_04_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_04_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_CLEAR_04_0
#define GPIO_EE_INTERRUPT_CLEAR_04_0                    MK_ADDR_CONST(0x1094)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_SECURE                     0x0
#define GPIO_EE_INTERRUPT_CLEAR_04_0_DUAL                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_04_0_SCR                        GPIO_EE_SCR_04_0
#define GPIO_EE_INTERRUPT_CLEAR_04_0_SCRREG                     GPIO_EE_SCR_04_0
#define GPIO_EE_INTERRUPT_CLEAR_04_0_WORD_COUNT                         0x1
#define GPIO_EE_INTERRUPT_CLEAR_04_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1098

// Reserved address 0x109c

// Register GPIO_EE_ENABLE_CONFIG_05_0
#define GPIO_EE_ENABLE_CONFIG_05_0                      MK_ADDR_CONST(0x10a0)
#define GPIO_EE_ENABLE_CONFIG_05_0_SECURE                       0x0
#define GPIO_EE_ENABLE_CONFIG_05_0_DUAL                         0x0
#define GPIO_EE_ENABLE_CONFIG_05_0_SCR                  GPIO_EE_SCR_05_0
#define GPIO_EE_ENABLE_CONFIG_05_0_SCRREG                       GPIO_EE_SCR_05_0
#define GPIO_EE_ENABLE_CONFIG_05_0_WORD_COUNT                   0x1
#define GPIO_EE_ENABLE_CONFIG_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_05_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_RANGE                 1:1
#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                       0x0
#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_EE_DEBOUNCE_THRESHOLD_05_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0                 MK_ADDR_CONST(0x10a4)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_SECURE                  0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DUAL                    0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_SCR                     GPIO_EE_SCR_05_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_SCRREG                  GPIO_EE_SCR_05_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                      0x1
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_INPUT_05_0
#define GPIO_EE_INPUT_05_0                      MK_ADDR_CONST(0x10a8)
#define GPIO_EE_INPUT_05_0_SECURE                       0x0
#define GPIO_EE_INPUT_05_0_DUAL                         0x0
#define GPIO_EE_INPUT_05_0_SCR                  GPIO_EE_SCR_05_0
#define GPIO_EE_INPUT_05_0_SCRREG                       GPIO_EE_SCR_05_0
#define GPIO_EE_INPUT_05_0_WORD_COUNT                   0x1
#define GPIO_EE_INPUT_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_05_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_INPUT_05_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_05_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_05_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_EE_INPUT_05_0_GPIO_IN_RANGE                        0:0
#define GPIO_EE_INPUT_05_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_05_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_05_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_EE_INPUT_05_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_05_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_05_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_OUTPUT_CONTROL_05_0
#define GPIO_EE_OUTPUT_CONTROL_05_0                     MK_ADDR_CONST(0x10ac)
#define GPIO_EE_OUTPUT_CONTROL_05_0_SECURE                      0x0
#define GPIO_EE_OUTPUT_CONTROL_05_0_DUAL                        0x0
#define GPIO_EE_OUTPUT_CONTROL_05_0_SCR                         GPIO_EE_SCR_05_0
#define GPIO_EE_OUTPUT_CONTROL_05_0_SCRREG                      GPIO_EE_SCR_05_0
#define GPIO_EE_OUTPUT_CONTROL_05_0_WORD_COUNT                  0x1
#define GPIO_EE_OUTPUT_CONTROL_05_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_EE_OUTPUT_VALUE_05_0
#define GPIO_EE_OUTPUT_VALUE_05_0                       MK_ADDR_CONST(0x10b0)
#define GPIO_EE_OUTPUT_VALUE_05_0_SECURE                        0x0
#define GPIO_EE_OUTPUT_VALUE_05_0_DUAL                  0x0
#define GPIO_EE_OUTPUT_VALUE_05_0_SCR                   GPIO_EE_SCR_05_0
#define GPIO_EE_OUTPUT_VALUE_05_0_SCRREG                        GPIO_EE_SCR_05_0
#define GPIO_EE_OUTPUT_VALUE_05_0_WORD_COUNT                    0x1
#define GPIO_EE_OUTPUT_VALUE_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_05_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_05_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_CLEAR_05_0
#define GPIO_EE_INTERRUPT_CLEAR_05_0                    MK_ADDR_CONST(0x10b4)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_SECURE                     0x0
#define GPIO_EE_INTERRUPT_CLEAR_05_0_DUAL                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_05_0_SCR                        GPIO_EE_SCR_05_0
#define GPIO_EE_INTERRUPT_CLEAR_05_0_SCRREG                     GPIO_EE_SCR_05_0
#define GPIO_EE_INTERRUPT_CLEAR_05_0_WORD_COUNT                         0x1
#define GPIO_EE_INTERRUPT_CLEAR_05_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x10b8

// Reserved address 0x10bc

// Register GPIO_EE_ENABLE_CONFIG_06_0
#define GPIO_EE_ENABLE_CONFIG_06_0                      MK_ADDR_CONST(0x10c0)
#define GPIO_EE_ENABLE_CONFIG_06_0_SECURE                       0x0
#define GPIO_EE_ENABLE_CONFIG_06_0_DUAL                         0x0
#define GPIO_EE_ENABLE_CONFIG_06_0_SCR                  GPIO_EE_SCR_06_0
#define GPIO_EE_ENABLE_CONFIG_06_0_SCRREG                       GPIO_EE_SCR_06_0
#define GPIO_EE_ENABLE_CONFIG_06_0_WORD_COUNT                   0x1
#define GPIO_EE_ENABLE_CONFIG_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_06_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_RANGE                 1:1
#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                       0x0
#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_EE_DEBOUNCE_THRESHOLD_06_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0                 MK_ADDR_CONST(0x10c4)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_SECURE                  0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DUAL                    0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_SCR                     GPIO_EE_SCR_06_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_SCRREG                  GPIO_EE_SCR_06_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                      0x1
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_INPUT_06_0
#define GPIO_EE_INPUT_06_0                      MK_ADDR_CONST(0x10c8)
#define GPIO_EE_INPUT_06_0_SECURE                       0x0
#define GPIO_EE_INPUT_06_0_DUAL                         0x0
#define GPIO_EE_INPUT_06_0_SCR                  GPIO_EE_SCR_06_0
#define GPIO_EE_INPUT_06_0_SCRREG                       GPIO_EE_SCR_06_0
#define GPIO_EE_INPUT_06_0_WORD_COUNT                   0x1
#define GPIO_EE_INPUT_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_06_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_INPUT_06_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_06_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_06_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_EE_INPUT_06_0_GPIO_IN_RANGE                        0:0
#define GPIO_EE_INPUT_06_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_06_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_06_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_EE_INPUT_06_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_06_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_06_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_OUTPUT_CONTROL_06_0
#define GPIO_EE_OUTPUT_CONTROL_06_0                     MK_ADDR_CONST(0x10cc)
#define GPIO_EE_OUTPUT_CONTROL_06_0_SECURE                      0x0
#define GPIO_EE_OUTPUT_CONTROL_06_0_DUAL                        0x0
#define GPIO_EE_OUTPUT_CONTROL_06_0_SCR                         GPIO_EE_SCR_06_0
#define GPIO_EE_OUTPUT_CONTROL_06_0_SCRREG                      GPIO_EE_SCR_06_0
#define GPIO_EE_OUTPUT_CONTROL_06_0_WORD_COUNT                  0x1
#define GPIO_EE_OUTPUT_CONTROL_06_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_EE_OUTPUT_VALUE_06_0
#define GPIO_EE_OUTPUT_VALUE_06_0                       MK_ADDR_CONST(0x10d0)
#define GPIO_EE_OUTPUT_VALUE_06_0_SECURE                        0x0
#define GPIO_EE_OUTPUT_VALUE_06_0_DUAL                  0x0
#define GPIO_EE_OUTPUT_VALUE_06_0_SCR                   GPIO_EE_SCR_06_0
#define GPIO_EE_OUTPUT_VALUE_06_0_SCRREG                        GPIO_EE_SCR_06_0
#define GPIO_EE_OUTPUT_VALUE_06_0_WORD_COUNT                    0x1
#define GPIO_EE_OUTPUT_VALUE_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_06_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_06_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_CLEAR_06_0
#define GPIO_EE_INTERRUPT_CLEAR_06_0                    MK_ADDR_CONST(0x10d4)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_SECURE                     0x0
#define GPIO_EE_INTERRUPT_CLEAR_06_0_DUAL                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_06_0_SCR                        GPIO_EE_SCR_06_0
#define GPIO_EE_INTERRUPT_CLEAR_06_0_SCRREG                     GPIO_EE_SCR_06_0
#define GPIO_EE_INTERRUPT_CLEAR_06_0_WORD_COUNT                         0x1
#define GPIO_EE_INTERRUPT_CLEAR_06_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x10d8

// Reserved address 0x10dc

// Register GPIO_EE_ENABLE_CONFIG_07_0
#define GPIO_EE_ENABLE_CONFIG_07_0                      MK_ADDR_CONST(0x10e0)
#define GPIO_EE_ENABLE_CONFIG_07_0_SECURE                       0x0
#define GPIO_EE_ENABLE_CONFIG_07_0_DUAL                         0x0
#define GPIO_EE_ENABLE_CONFIG_07_0_SCR                  GPIO_EE_SCR_07_0
#define GPIO_EE_ENABLE_CONFIG_07_0_SCRREG                       GPIO_EE_SCR_07_0
#define GPIO_EE_ENABLE_CONFIG_07_0_WORD_COUNT                   0x1
#define GPIO_EE_ENABLE_CONFIG_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_07_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_RANGE                 1:1
#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                       0x0
#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_EE_DEBOUNCE_THRESHOLD_07_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0                 MK_ADDR_CONST(0x10e4)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_SECURE                  0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DUAL                    0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_SCR                     GPIO_EE_SCR_07_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_SCRREG                  GPIO_EE_SCR_07_0
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                      0x1
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_INPUT_07_0
#define GPIO_EE_INPUT_07_0                      MK_ADDR_CONST(0x10e8)
#define GPIO_EE_INPUT_07_0_SECURE                       0x0
#define GPIO_EE_INPUT_07_0_DUAL                         0x0
#define GPIO_EE_INPUT_07_0_SCR                  GPIO_EE_SCR_07_0
#define GPIO_EE_INPUT_07_0_SCRREG                       GPIO_EE_SCR_07_0
#define GPIO_EE_INPUT_07_0_WORD_COUNT                   0x1
#define GPIO_EE_INPUT_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_07_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_INPUT_07_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_07_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_07_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_EE_INPUT_07_0_GPIO_IN_RANGE                        0:0
#define GPIO_EE_INPUT_07_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_07_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_EE_INPUT_07_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_EE_INPUT_07_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_07_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_07_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_EE_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_EE_OUTPUT_CONTROL_07_0
#define GPIO_EE_OUTPUT_CONTROL_07_0                     MK_ADDR_CONST(0x10ec)
#define GPIO_EE_OUTPUT_CONTROL_07_0_SECURE                      0x0
#define GPIO_EE_OUTPUT_CONTROL_07_0_DUAL                        0x0
#define GPIO_EE_OUTPUT_CONTROL_07_0_SCR                         GPIO_EE_SCR_07_0
#define GPIO_EE_OUTPUT_CONTROL_07_0_SCRREG                      GPIO_EE_SCR_07_0
#define GPIO_EE_OUTPUT_CONTROL_07_0_WORD_COUNT                  0x1
#define GPIO_EE_OUTPUT_CONTROL_07_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_EE_OUTPUT_VALUE_07_0
#define GPIO_EE_OUTPUT_VALUE_07_0                       MK_ADDR_CONST(0x10f0)
#define GPIO_EE_OUTPUT_VALUE_07_0_SECURE                        0x0
#define GPIO_EE_OUTPUT_VALUE_07_0_DUAL                  0x0
#define GPIO_EE_OUTPUT_VALUE_07_0_SCR                   GPIO_EE_SCR_07_0
#define GPIO_EE_OUTPUT_VALUE_07_0_SCRREG                        GPIO_EE_SCR_07_0
#define GPIO_EE_OUTPUT_VALUE_07_0_WORD_COUNT                    0x1
#define GPIO_EE_OUTPUT_VALUE_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_07_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_07_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_CLEAR_07_0
#define GPIO_EE_INTERRUPT_CLEAR_07_0                    MK_ADDR_CONST(0x10f4)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_SECURE                     0x0
#define GPIO_EE_INTERRUPT_CLEAR_07_0_DUAL                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_07_0_SCR                        GPIO_EE_SCR_07_0
#define GPIO_EE_INTERRUPT_CLEAR_07_0_SCRREG                     GPIO_EE_SCR_07_0
#define GPIO_EE_INTERRUPT_CLEAR_07_0_WORD_COUNT                         0x1
#define GPIO_EE_INTERRUPT_CLEAR_07_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x10f8

// Reserved address 0x10fc

// Register GPIO_EE_INTERRUPT_STATUS_G0_0
#define GPIO_EE_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x1100)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_EE_INTERRUPT_STATUS_G0_0_DUAL                      0x0
#define GPIO_EE_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_EE_INTERRUPT_STATUS_G0_0_SCRREG                    0
#define GPIO_EE_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_EE_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_STATUS_G1_0
#define GPIO_EE_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x1104)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_EE_INTERRUPT_STATUS_G1_0_DUAL                      0x0
#define GPIO_EE_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_EE_INTERRUPT_STATUS_G1_0_SCRREG                    0
#define GPIO_EE_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_EE_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_STATUS_G2_0
#define GPIO_EE_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x1108)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_EE_INTERRUPT_STATUS_G2_0_DUAL                      0x0
#define GPIO_EE_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_EE_INTERRUPT_STATUS_G2_0_SCRREG                    0
#define GPIO_EE_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_EE_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_STATUS_G3_0
#define GPIO_EE_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x110c)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_EE_INTERRUPT_STATUS_G3_0_DUAL                      0x0
#define GPIO_EE_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_EE_INTERRUPT_STATUS_G3_0_SCRREG                    0
#define GPIO_EE_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_EE_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_STATUS_G4_0
#define GPIO_EE_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x1110)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_EE_INTERRUPT_STATUS_G4_0_DUAL                      0x0
#define GPIO_EE_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_EE_INTERRUPT_STATUS_G4_0_SCRREG                    0
#define GPIO_EE_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_EE_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_STATUS_G5_0
#define GPIO_EE_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x1114)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_EE_INTERRUPT_STATUS_G5_0_DUAL                      0x0
#define GPIO_EE_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_EE_INTERRUPT_STATUS_G5_0_SCRREG                    0
#define GPIO_EE_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_EE_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_STATUS_G6_0
#define GPIO_EE_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x1118)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_EE_INTERRUPT_STATUS_G6_0_DUAL                      0x0
#define GPIO_EE_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_EE_INTERRUPT_STATUS_G6_0_SCRREG                    0
#define GPIO_EE_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_EE_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_EE_INTERRUPT_STATUS_G7_0
#define GPIO_EE_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x111c)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_EE_INTERRUPT_STATUS_G7_0_DUAL                      0x0
#define GPIO_EE_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_EE_INTERRUPT_STATUS_G7_0_SCRREG                    0
#define GPIO_EE_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_EE_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x1120

// Reserved address 0x1124

// Reserved address 0x1128

// Reserved address 0x112c

// Reserved address 0x1130

// Reserved address 0x1134

// Reserved address 0x1138

// Reserved address 0x113c

// Reserved address 0x1140

// Reserved address 0x1144

// Reserved address 0x1148

// Reserved address 0x114c

// Reserved address 0x1150

// Reserved address 0x1154

// Reserved address 0x1158

// Reserved address 0x115c

// Reserved address 0x1160

// Reserved address 0x1164

// Reserved address 0x1168

// Reserved address 0x116c

// Reserved address 0x1170

// Reserved address 0x1174

// Reserved address 0x1178

// Reserved address 0x117c

// Reserved address 0x1180

// Reserved address 0x1184

// Reserved address 0x1188

// Reserved address 0x118c

// Reserved address 0x1190

// Reserved address 0x1194

// Reserved address 0x1198

// Reserved address 0x119c

// Reserved address 0x11a0

// Reserved address 0x11a4

// Reserved address 0x11a8

// Reserved address 0x11ac

// Reserved address 0x11b0

// Reserved address 0x11b4

// Reserved address 0x11b8

// Reserved address 0x11bc

// Reserved address 0x11c0

// Reserved address 0x11c4

// Reserved address 0x11c8

// Reserved address 0x11cc

// Reserved address 0x11d0

// Reserved address 0x11d4

// Reserved address 0x11d8

// Reserved address 0x11dc

// Reserved address 0x11e0

// Reserved address 0x11e4

// Reserved address 0x11e8

// Reserved address 0x11ec

// Reserved address 0x11f0

// Reserved address 0x11f4

// Reserved address 0x11f8

// Reserved address 0x11fc

// Register GPIO_GG_ENABLE_CONFIG_00_0
#define GPIO_GG_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x1200)
#define GPIO_GG_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_DUAL                         0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_SCR                  GPIO_GG_SCR_00_0
#define GPIO_GG_ENABLE_CONFIG_00_0_SCRREG                       GPIO_GG_SCR_00_0
#define GPIO_GG_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_GG_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_GG_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_GG_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_GG_DEBOUNCE_THRESHOLD_00_0
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x1204)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_GG_SCR_00_0
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_GG_SCR_00_0
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_GG_INPUT_00_0
#define GPIO_GG_INPUT_00_0                      MK_ADDR_CONST(0x1208)
#define GPIO_GG_INPUT_00_0_SECURE                       0x0
#define GPIO_GG_INPUT_00_0_DUAL                         0x0
#define GPIO_GG_INPUT_00_0_SCR                  GPIO_GG_SCR_00_0
#define GPIO_GG_INPUT_00_0_SCRREG                       GPIO_GG_SCR_00_0
#define GPIO_GG_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_GG_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_GG_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_GG_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_GG_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_GG_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_GG_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_GG_OUTPUT_CONTROL_00_0
#define GPIO_GG_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x120c)
#define GPIO_GG_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_GG_OUTPUT_CONTROL_00_0_DUAL                        0x0
#define GPIO_GG_OUTPUT_CONTROL_00_0_SCR                         GPIO_GG_SCR_00_0
#define GPIO_GG_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_GG_SCR_00_0
#define GPIO_GG_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_GG_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_GG_OUTPUT_VALUE_00_0
#define GPIO_GG_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x1210)
#define GPIO_GG_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_GG_OUTPUT_VALUE_00_0_DUAL                  0x0
#define GPIO_GG_OUTPUT_VALUE_00_0_SCR                   GPIO_GG_SCR_00_0
#define GPIO_GG_OUTPUT_VALUE_00_0_SCRREG                        GPIO_GG_SCR_00_0
#define GPIO_GG_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_GG_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_CLEAR_00_0
#define GPIO_GG_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x1214)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_GG_INTERRUPT_CLEAR_00_0_DUAL                       0x0
#define GPIO_GG_INTERRUPT_CLEAR_00_0_SCR                        GPIO_GG_SCR_00_0
#define GPIO_GG_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_GG_SCR_00_0
#define GPIO_GG_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_GG_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1218

// Reserved address 0x121c

// Reserved address 0x1220

// Reserved address 0x1224

// Reserved address 0x1228

// Reserved address 0x122c

// Reserved address 0x1230

// Reserved address 0x1234

// Reserved address 0x1238

// Reserved address 0x123c

// Reserved address 0x1240

// Reserved address 0x1244

// Reserved address 0x1248

// Reserved address 0x124c

// Reserved address 0x1250

// Reserved address 0x1254

// Reserved address 0x1258

// Reserved address 0x125c

// Reserved address 0x1260

// Reserved address 0x1264

// Reserved address 0x1268

// Reserved address 0x126c

// Reserved address 0x1270

// Reserved address 0x1274

// Reserved address 0x1278

// Reserved address 0x127c

// Reserved address 0x1280

// Reserved address 0x1284

// Reserved address 0x1288

// Reserved address 0x128c

// Reserved address 0x1290

// Reserved address 0x1294

// Reserved address 0x1298

// Reserved address 0x129c

// Reserved address 0x12a0

// Reserved address 0x12a4

// Reserved address 0x12a8

// Reserved address 0x12ac

// Reserved address 0x12b0

// Reserved address 0x12b4

// Reserved address 0x12b8

// Reserved address 0x12bc

// Reserved address 0x12c0

// Reserved address 0x12c4

// Reserved address 0x12c8

// Reserved address 0x12cc

// Reserved address 0x12d0

// Reserved address 0x12d4

// Reserved address 0x12d8

// Reserved address 0x12dc

// Reserved address 0x12e0

// Reserved address 0x12e4

// Reserved address 0x12e8

// Reserved address 0x12ec

// Reserved address 0x12f0

// Reserved address 0x12f4

// Reserved address 0x12f8

// Reserved address 0x12fc

// Register GPIO_GG_INTERRUPT_STATUS_G0_0
#define GPIO_GG_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x1300)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G0_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G0_0_SCRREG                    0
#define GPIO_GG_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G1_0
#define GPIO_GG_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x1304)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G1_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G1_0_SCRREG                    0
#define GPIO_GG_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G2_0
#define GPIO_GG_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x1308)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G2_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G2_0_SCRREG                    0
#define GPIO_GG_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G3_0
#define GPIO_GG_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x130c)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G3_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G3_0_SCRREG                    0
#define GPIO_GG_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G4_0
#define GPIO_GG_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x1310)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G4_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G4_0_SCRREG                    0
#define GPIO_GG_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G5_0
#define GPIO_GG_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x1314)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G5_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G5_0_SCRREG                    0
#define GPIO_GG_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G6_0
#define GPIO_GG_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x1318)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G6_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G6_0_SCRREG                    0
#define GPIO_GG_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G7_0
#define GPIO_GG_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x131c)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G7_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G7_0_SCRREG                    0
#define GPIO_GG_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x1320

// Reserved address 0x1324

// Reserved address 0x1328

// Reserved address 0x132c

// Reserved address 0x1330

// Reserved address 0x1334

// Reserved address 0x1338

// Reserved address 0x133c

// Reserved address 0x1340

// Reserved address 0x1344

// Reserved address 0x1348

// Reserved address 0x134c

// Reserved address 0x1350

// Reserved address 0x1354

// Reserved address 0x1358

// Reserved address 0x135c

// Reserved address 0x1360

// Reserved address 0x1364

// Reserved address 0x1368

// Reserved address 0x136c

// Reserved address 0x1370

// Reserved address 0x1374

// Reserved address 0x1378

// Reserved address 0x137c

// Reserved address 0x1380

// Reserved address 0x1384

// Reserved address 0x1388

// Reserved address 0x138c

// Reserved address 0x1390

// Reserved address 0x1394

// Reserved address 0x1398

// Reserved address 0x139c

// Reserved address 0x13a0

// Reserved address 0x13a4

// Reserved address 0x13a8

// Reserved address 0x13ac

// Reserved address 0x13b0

// Reserved address 0x13b4

// Reserved address 0x13b8

// Reserved address 0x13bc

// Reserved address 0x13c0

// Reserved address 0x13c4

// Reserved address 0x13c8

// Reserved address 0x13cc

// Reserved address 0x13d0

// Reserved address 0x13d4

// Reserved address 0x13d8

// Reserved address 0x13dc

// Reserved address 0x13e0

// Reserved address 0x13e4

// Reserved address 0x13e8

// Reserved address 0x13ec

// Reserved address 0x13f0

// Reserved address 0x13f4

// Reserved address 0x13f8

// Reserved address 0x13fc

// Register GPIO_CC_ENABLE_CONFIG_00_0
#define GPIO_CC_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x1400)
#define GPIO_CC_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_DUAL                         0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_SCR                  GPIO_CC_SCR_00_0
#define GPIO_CC_ENABLE_CONFIG_00_0_SCRREG                       GPIO_CC_SCR_00_0
#define GPIO_CC_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_CC_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_CC_DEBOUNCE_THRESHOLD_00_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x1404)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_CC_SCR_00_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_CC_SCR_00_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_INPUT_00_0
#define GPIO_CC_INPUT_00_0                      MK_ADDR_CONST(0x1408)
#define GPIO_CC_INPUT_00_0_SECURE                       0x0
#define GPIO_CC_INPUT_00_0_DUAL                         0x0
#define GPIO_CC_INPUT_00_0_SCR                  GPIO_CC_SCR_00_0
#define GPIO_CC_INPUT_00_0_SCRREG                       GPIO_CC_SCR_00_0
#define GPIO_CC_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_CC_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_CC_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_CC_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_CC_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_OUTPUT_CONTROL_00_0
#define GPIO_CC_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x140c)
#define GPIO_CC_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_CC_OUTPUT_CONTROL_00_0_DUAL                        0x0
#define GPIO_CC_OUTPUT_CONTROL_00_0_SCR                         GPIO_CC_SCR_00_0
#define GPIO_CC_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_CC_SCR_00_0
#define GPIO_CC_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_CC_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_CC_OUTPUT_VALUE_00_0
#define GPIO_CC_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x1410)
#define GPIO_CC_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_CC_OUTPUT_VALUE_00_0_DUAL                  0x0
#define GPIO_CC_OUTPUT_VALUE_00_0_SCR                   GPIO_CC_SCR_00_0
#define GPIO_CC_OUTPUT_VALUE_00_0_SCRREG                        GPIO_CC_SCR_00_0
#define GPIO_CC_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_CC_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_CLEAR_00_0
#define GPIO_CC_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x1414)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_CC_INTERRUPT_CLEAR_00_0_DUAL                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_00_0_SCR                        GPIO_CC_SCR_00_0
#define GPIO_CC_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_CC_SCR_00_0
#define GPIO_CC_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_CC_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1418

// Reserved address 0x141c

// Register GPIO_CC_ENABLE_CONFIG_01_0
#define GPIO_CC_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x1420)
#define GPIO_CC_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_DUAL                         0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_SCR                  GPIO_CC_SCR_01_0
#define GPIO_CC_ENABLE_CONFIG_01_0_SCRREG                       GPIO_CC_SCR_01_0
#define GPIO_CC_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_CC_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_CC_DEBOUNCE_THRESHOLD_01_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x1424)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_CC_SCR_01_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_CC_SCR_01_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_INPUT_01_0
#define GPIO_CC_INPUT_01_0                      MK_ADDR_CONST(0x1428)
#define GPIO_CC_INPUT_01_0_SECURE                       0x0
#define GPIO_CC_INPUT_01_0_DUAL                         0x0
#define GPIO_CC_INPUT_01_0_SCR                  GPIO_CC_SCR_01_0
#define GPIO_CC_INPUT_01_0_SCRREG                       GPIO_CC_SCR_01_0
#define GPIO_CC_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_CC_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_CC_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_CC_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_CC_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_OUTPUT_CONTROL_01_0
#define GPIO_CC_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x142c)
#define GPIO_CC_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_CC_OUTPUT_CONTROL_01_0_DUAL                        0x0
#define GPIO_CC_OUTPUT_CONTROL_01_0_SCR                         GPIO_CC_SCR_01_0
#define GPIO_CC_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_CC_SCR_01_0
#define GPIO_CC_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_CC_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_CC_OUTPUT_VALUE_01_0
#define GPIO_CC_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x1430)
#define GPIO_CC_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_CC_OUTPUT_VALUE_01_0_DUAL                  0x0
#define GPIO_CC_OUTPUT_VALUE_01_0_SCR                   GPIO_CC_SCR_01_0
#define GPIO_CC_OUTPUT_VALUE_01_0_SCRREG                        GPIO_CC_SCR_01_0
#define GPIO_CC_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_CC_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_CLEAR_01_0
#define GPIO_CC_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x1434)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_CC_INTERRUPT_CLEAR_01_0_DUAL                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_01_0_SCR                        GPIO_CC_SCR_01_0
#define GPIO_CC_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_CC_SCR_01_0
#define GPIO_CC_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_CC_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1438

// Reserved address 0x143c

// Register GPIO_CC_ENABLE_CONFIG_02_0
#define GPIO_CC_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x1440)
#define GPIO_CC_ENABLE_CONFIG_02_0_SECURE                       0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_DUAL                         0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_SCR                  GPIO_CC_SCR_02_0
#define GPIO_CC_ENABLE_CONFIG_02_0_SCRREG                       GPIO_CC_SCR_02_0
#define GPIO_CC_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
#define GPIO_CC_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_CC_DEBOUNCE_THRESHOLD_02_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x1444)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_CC_SCR_02_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_CC_SCR_02_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_INPUT_02_0
#define GPIO_CC_INPUT_02_0                      MK_ADDR_CONST(0x1448)
#define GPIO_CC_INPUT_02_0_SECURE                       0x0
#define GPIO_CC_INPUT_02_0_DUAL                         0x0
#define GPIO_CC_INPUT_02_0_SCR                  GPIO_CC_SCR_02_0
#define GPIO_CC_INPUT_02_0_SCRREG                       GPIO_CC_SCR_02_0
#define GPIO_CC_INPUT_02_0_WORD_COUNT                   0x1
#define GPIO_CC_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_CC_INPUT_02_0_GPIO_IN_RANGE                        0:0
#define GPIO_CC_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_CC_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_OUTPUT_CONTROL_02_0
#define GPIO_CC_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x144c)
#define GPIO_CC_OUTPUT_CONTROL_02_0_SECURE                      0x0
#define GPIO_CC_OUTPUT_CONTROL_02_0_DUAL                        0x0
#define GPIO_CC_OUTPUT_CONTROL_02_0_SCR                         GPIO_CC_SCR_02_0
#define GPIO_CC_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_CC_SCR_02_0
#define GPIO_CC_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
#define GPIO_CC_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_CC_OUTPUT_VALUE_02_0
#define GPIO_CC_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x1450)
#define GPIO_CC_OUTPUT_VALUE_02_0_SECURE                        0x0
#define GPIO_CC_OUTPUT_VALUE_02_0_DUAL                  0x0
#define GPIO_CC_OUTPUT_VALUE_02_0_SCR                   GPIO_CC_SCR_02_0
#define GPIO_CC_OUTPUT_VALUE_02_0_SCRREG                        GPIO_CC_SCR_02_0
#define GPIO_CC_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
#define GPIO_CC_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_CLEAR_02_0
#define GPIO_CC_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x1454)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_SECURE                     0x0
#define GPIO_CC_INTERRUPT_CLEAR_02_0_DUAL                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_02_0_SCR                        GPIO_CC_SCR_02_0
#define GPIO_CC_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_CC_SCR_02_0
#define GPIO_CC_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
#define GPIO_CC_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1458

// Reserved address 0x145c

// Register GPIO_CC_ENABLE_CONFIG_03_0
#define GPIO_CC_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x1460)
#define GPIO_CC_ENABLE_CONFIG_03_0_SECURE                       0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_DUAL                         0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_SCR                  GPIO_CC_SCR_03_0
#define GPIO_CC_ENABLE_CONFIG_03_0_SCRREG                       GPIO_CC_SCR_03_0
#define GPIO_CC_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
#define GPIO_CC_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_CC_DEBOUNCE_THRESHOLD_03_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x1464)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_CC_SCR_03_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_CC_SCR_03_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_INPUT_03_0
#define GPIO_CC_INPUT_03_0                      MK_ADDR_CONST(0x1468)
#define GPIO_CC_INPUT_03_0_SECURE                       0x0
#define GPIO_CC_INPUT_03_0_DUAL                         0x0
#define GPIO_CC_INPUT_03_0_SCR                  GPIO_CC_SCR_03_0
#define GPIO_CC_INPUT_03_0_SCRREG                       GPIO_CC_SCR_03_0
#define GPIO_CC_INPUT_03_0_WORD_COUNT                   0x1
#define GPIO_CC_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_CC_INPUT_03_0_GPIO_IN_RANGE                        0:0
#define GPIO_CC_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_CC_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_OUTPUT_CONTROL_03_0
#define GPIO_CC_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x146c)
#define GPIO_CC_OUTPUT_CONTROL_03_0_SECURE                      0x0
#define GPIO_CC_OUTPUT_CONTROL_03_0_DUAL                        0x0
#define GPIO_CC_OUTPUT_CONTROL_03_0_SCR                         GPIO_CC_SCR_03_0
#define GPIO_CC_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_CC_SCR_03_0
#define GPIO_CC_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
#define GPIO_CC_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_CC_OUTPUT_VALUE_03_0
#define GPIO_CC_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x1470)
#define GPIO_CC_OUTPUT_VALUE_03_0_SECURE                        0x0
#define GPIO_CC_OUTPUT_VALUE_03_0_DUAL                  0x0
#define GPIO_CC_OUTPUT_VALUE_03_0_SCR                   GPIO_CC_SCR_03_0
#define GPIO_CC_OUTPUT_VALUE_03_0_SCRREG                        GPIO_CC_SCR_03_0
#define GPIO_CC_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
#define GPIO_CC_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_CLEAR_03_0
#define GPIO_CC_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x1474)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_SECURE                     0x0
#define GPIO_CC_INTERRUPT_CLEAR_03_0_DUAL                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_03_0_SCR                        GPIO_CC_SCR_03_0
#define GPIO_CC_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_CC_SCR_03_0
#define GPIO_CC_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
#define GPIO_CC_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1478

// Reserved address 0x147c

// Register GPIO_CC_ENABLE_CONFIG_04_0
#define GPIO_CC_ENABLE_CONFIG_04_0                      MK_ADDR_CONST(0x1480)
#define GPIO_CC_ENABLE_CONFIG_04_0_SECURE                       0x0
#define GPIO_CC_ENABLE_CONFIG_04_0_DUAL                         0x0
#define GPIO_CC_ENABLE_CONFIG_04_0_SCR                  GPIO_CC_SCR_04_0
#define GPIO_CC_ENABLE_CONFIG_04_0_SCRREG                       GPIO_CC_SCR_04_0
#define GPIO_CC_ENABLE_CONFIG_04_0_WORD_COUNT                   0x1
#define GPIO_CC_ENABLE_CONFIG_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_04_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_RANGE                 1:1
#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                       0x0
#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_CC_DEBOUNCE_THRESHOLD_04_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0                 MK_ADDR_CONST(0x1484)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_SECURE                  0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DUAL                    0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_SCR                     GPIO_CC_SCR_04_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_SCRREG                  GPIO_CC_SCR_04_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                      0x1
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_INPUT_04_0
#define GPIO_CC_INPUT_04_0                      MK_ADDR_CONST(0x1488)
#define GPIO_CC_INPUT_04_0_SECURE                       0x0
#define GPIO_CC_INPUT_04_0_DUAL                         0x0
#define GPIO_CC_INPUT_04_0_SCR                  GPIO_CC_SCR_04_0
#define GPIO_CC_INPUT_04_0_SCRREG                       GPIO_CC_SCR_04_0
#define GPIO_CC_INPUT_04_0_WORD_COUNT                   0x1
#define GPIO_CC_INPUT_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_04_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_INPUT_04_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_04_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_04_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_CC_INPUT_04_0_GPIO_IN_RANGE                        0:0
#define GPIO_CC_INPUT_04_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_04_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_04_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_CC_INPUT_04_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_04_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_04_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_OUTPUT_CONTROL_04_0
#define GPIO_CC_OUTPUT_CONTROL_04_0                     MK_ADDR_CONST(0x148c)
#define GPIO_CC_OUTPUT_CONTROL_04_0_SECURE                      0x0
#define GPIO_CC_OUTPUT_CONTROL_04_0_DUAL                        0x0
#define GPIO_CC_OUTPUT_CONTROL_04_0_SCR                         GPIO_CC_SCR_04_0
#define GPIO_CC_OUTPUT_CONTROL_04_0_SCRREG                      GPIO_CC_SCR_04_0
#define GPIO_CC_OUTPUT_CONTROL_04_0_WORD_COUNT                  0x1
#define GPIO_CC_OUTPUT_CONTROL_04_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_CC_OUTPUT_VALUE_04_0
#define GPIO_CC_OUTPUT_VALUE_04_0                       MK_ADDR_CONST(0x1490)
#define GPIO_CC_OUTPUT_VALUE_04_0_SECURE                        0x0
#define GPIO_CC_OUTPUT_VALUE_04_0_DUAL                  0x0
#define GPIO_CC_OUTPUT_VALUE_04_0_SCR                   GPIO_CC_SCR_04_0
#define GPIO_CC_OUTPUT_VALUE_04_0_SCRREG                        GPIO_CC_SCR_04_0
#define GPIO_CC_OUTPUT_VALUE_04_0_WORD_COUNT                    0x1
#define GPIO_CC_OUTPUT_VALUE_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_04_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_04_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_CLEAR_04_0
#define GPIO_CC_INTERRUPT_CLEAR_04_0                    MK_ADDR_CONST(0x1494)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_SECURE                     0x0
#define GPIO_CC_INTERRUPT_CLEAR_04_0_DUAL                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_04_0_SCR                        GPIO_CC_SCR_04_0
#define GPIO_CC_INTERRUPT_CLEAR_04_0_SCRREG                     GPIO_CC_SCR_04_0
#define GPIO_CC_INTERRUPT_CLEAR_04_0_WORD_COUNT                         0x1
#define GPIO_CC_INTERRUPT_CLEAR_04_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1498

// Reserved address 0x149c

// Register GPIO_CC_ENABLE_CONFIG_05_0
#define GPIO_CC_ENABLE_CONFIG_05_0                      MK_ADDR_CONST(0x14a0)
#define GPIO_CC_ENABLE_CONFIG_05_0_SECURE                       0x0
#define GPIO_CC_ENABLE_CONFIG_05_0_DUAL                         0x0
#define GPIO_CC_ENABLE_CONFIG_05_0_SCR                  GPIO_CC_SCR_05_0
#define GPIO_CC_ENABLE_CONFIG_05_0_SCRREG                       GPIO_CC_SCR_05_0
#define GPIO_CC_ENABLE_CONFIG_05_0_WORD_COUNT                   0x1
#define GPIO_CC_ENABLE_CONFIG_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_05_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_RANGE                 1:1
#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                       0x0
#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_CC_DEBOUNCE_THRESHOLD_05_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0                 MK_ADDR_CONST(0x14a4)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_SECURE                  0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DUAL                    0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_SCR                     GPIO_CC_SCR_05_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_SCRREG                  GPIO_CC_SCR_05_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                      0x1
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_INPUT_05_0
#define GPIO_CC_INPUT_05_0                      MK_ADDR_CONST(0x14a8)
#define GPIO_CC_INPUT_05_0_SECURE                       0x0
#define GPIO_CC_INPUT_05_0_DUAL                         0x0
#define GPIO_CC_INPUT_05_0_SCR                  GPIO_CC_SCR_05_0
#define GPIO_CC_INPUT_05_0_SCRREG                       GPIO_CC_SCR_05_0
#define GPIO_CC_INPUT_05_0_WORD_COUNT                   0x1
#define GPIO_CC_INPUT_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_05_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_INPUT_05_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_05_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_05_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_CC_INPUT_05_0_GPIO_IN_RANGE                        0:0
#define GPIO_CC_INPUT_05_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_05_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_05_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_CC_INPUT_05_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_05_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_05_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_OUTPUT_CONTROL_05_0
#define GPIO_CC_OUTPUT_CONTROL_05_0                     MK_ADDR_CONST(0x14ac)
#define GPIO_CC_OUTPUT_CONTROL_05_0_SECURE                      0x0
#define GPIO_CC_OUTPUT_CONTROL_05_0_DUAL                        0x0
#define GPIO_CC_OUTPUT_CONTROL_05_0_SCR                         GPIO_CC_SCR_05_0
#define GPIO_CC_OUTPUT_CONTROL_05_0_SCRREG                      GPIO_CC_SCR_05_0
#define GPIO_CC_OUTPUT_CONTROL_05_0_WORD_COUNT                  0x1
#define GPIO_CC_OUTPUT_CONTROL_05_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_CC_OUTPUT_VALUE_05_0
#define GPIO_CC_OUTPUT_VALUE_05_0                       MK_ADDR_CONST(0x14b0)
#define GPIO_CC_OUTPUT_VALUE_05_0_SECURE                        0x0
#define GPIO_CC_OUTPUT_VALUE_05_0_DUAL                  0x0
#define GPIO_CC_OUTPUT_VALUE_05_0_SCR                   GPIO_CC_SCR_05_0
#define GPIO_CC_OUTPUT_VALUE_05_0_SCRREG                        GPIO_CC_SCR_05_0
#define GPIO_CC_OUTPUT_VALUE_05_0_WORD_COUNT                    0x1
#define GPIO_CC_OUTPUT_VALUE_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_05_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_05_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_CLEAR_05_0
#define GPIO_CC_INTERRUPT_CLEAR_05_0                    MK_ADDR_CONST(0x14b4)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_SECURE                     0x0
#define GPIO_CC_INTERRUPT_CLEAR_05_0_DUAL                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_05_0_SCR                        GPIO_CC_SCR_05_0
#define GPIO_CC_INTERRUPT_CLEAR_05_0_SCRREG                     GPIO_CC_SCR_05_0
#define GPIO_CC_INTERRUPT_CLEAR_05_0_WORD_COUNT                         0x1
#define GPIO_CC_INTERRUPT_CLEAR_05_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x14b8

// Reserved address 0x14bc

// Register GPIO_CC_ENABLE_CONFIG_06_0
#define GPIO_CC_ENABLE_CONFIG_06_0                      MK_ADDR_CONST(0x14c0)
#define GPIO_CC_ENABLE_CONFIG_06_0_SECURE                       0x0
#define GPIO_CC_ENABLE_CONFIG_06_0_DUAL                         0x0
#define GPIO_CC_ENABLE_CONFIG_06_0_SCR                  GPIO_CC_SCR_06_0
#define GPIO_CC_ENABLE_CONFIG_06_0_SCRREG                       GPIO_CC_SCR_06_0
#define GPIO_CC_ENABLE_CONFIG_06_0_WORD_COUNT                   0x1
#define GPIO_CC_ENABLE_CONFIG_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_06_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_RANGE                 1:1
#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                       0x0
#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_CC_DEBOUNCE_THRESHOLD_06_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0                 MK_ADDR_CONST(0x14c4)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_SECURE                  0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DUAL                    0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_SCR                     GPIO_CC_SCR_06_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_SCRREG                  GPIO_CC_SCR_06_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                      0x1
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_INPUT_06_0
#define GPIO_CC_INPUT_06_0                      MK_ADDR_CONST(0x14c8)
#define GPIO_CC_INPUT_06_0_SECURE                       0x0
#define GPIO_CC_INPUT_06_0_DUAL                         0x0
#define GPIO_CC_INPUT_06_0_SCR                  GPIO_CC_SCR_06_0
#define GPIO_CC_INPUT_06_0_SCRREG                       GPIO_CC_SCR_06_0
#define GPIO_CC_INPUT_06_0_WORD_COUNT                   0x1
#define GPIO_CC_INPUT_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_06_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_INPUT_06_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_06_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_06_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_CC_INPUT_06_0_GPIO_IN_RANGE                        0:0
#define GPIO_CC_INPUT_06_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_06_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_06_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_CC_INPUT_06_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_06_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_06_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_OUTPUT_CONTROL_06_0
#define GPIO_CC_OUTPUT_CONTROL_06_0                     MK_ADDR_CONST(0x14cc)
#define GPIO_CC_OUTPUT_CONTROL_06_0_SECURE                      0x0
#define GPIO_CC_OUTPUT_CONTROL_06_0_DUAL                        0x0
#define GPIO_CC_OUTPUT_CONTROL_06_0_SCR                         GPIO_CC_SCR_06_0
#define GPIO_CC_OUTPUT_CONTROL_06_0_SCRREG                      GPIO_CC_SCR_06_0
#define GPIO_CC_OUTPUT_CONTROL_06_0_WORD_COUNT                  0x1
#define GPIO_CC_OUTPUT_CONTROL_06_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_CC_OUTPUT_VALUE_06_0
#define GPIO_CC_OUTPUT_VALUE_06_0                       MK_ADDR_CONST(0x14d0)
#define GPIO_CC_OUTPUT_VALUE_06_0_SECURE                        0x0
#define GPIO_CC_OUTPUT_VALUE_06_0_DUAL                  0x0
#define GPIO_CC_OUTPUT_VALUE_06_0_SCR                   GPIO_CC_SCR_06_0
#define GPIO_CC_OUTPUT_VALUE_06_0_SCRREG                        GPIO_CC_SCR_06_0
#define GPIO_CC_OUTPUT_VALUE_06_0_WORD_COUNT                    0x1
#define GPIO_CC_OUTPUT_VALUE_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_06_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_06_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_CLEAR_06_0
#define GPIO_CC_INTERRUPT_CLEAR_06_0                    MK_ADDR_CONST(0x14d4)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_SECURE                     0x0
#define GPIO_CC_INTERRUPT_CLEAR_06_0_DUAL                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_06_0_SCR                        GPIO_CC_SCR_06_0
#define GPIO_CC_INTERRUPT_CLEAR_06_0_SCRREG                     GPIO_CC_SCR_06_0
#define GPIO_CC_INTERRUPT_CLEAR_06_0_WORD_COUNT                         0x1
#define GPIO_CC_INTERRUPT_CLEAR_06_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x14d8

// Reserved address 0x14dc

// Register GPIO_CC_ENABLE_CONFIG_07_0
#define GPIO_CC_ENABLE_CONFIG_07_0                      MK_ADDR_CONST(0x14e0)
#define GPIO_CC_ENABLE_CONFIG_07_0_SECURE                       0x0
#define GPIO_CC_ENABLE_CONFIG_07_0_DUAL                         0x0
#define GPIO_CC_ENABLE_CONFIG_07_0_SCR                  GPIO_CC_SCR_07_0
#define GPIO_CC_ENABLE_CONFIG_07_0_SCRREG                       GPIO_CC_SCR_07_0
#define GPIO_CC_ENABLE_CONFIG_07_0_WORD_COUNT                   0x1
#define GPIO_CC_ENABLE_CONFIG_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_07_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_RANGE                 1:1
#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                       0x0
#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_CC_DEBOUNCE_THRESHOLD_07_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0                 MK_ADDR_CONST(0x14e4)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_SECURE                  0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DUAL                    0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_SCR                     GPIO_CC_SCR_07_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_SCRREG                  GPIO_CC_SCR_07_0
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                      0x1
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_INPUT_07_0
#define GPIO_CC_INPUT_07_0                      MK_ADDR_CONST(0x14e8)
#define GPIO_CC_INPUT_07_0_SECURE                       0x0
#define GPIO_CC_INPUT_07_0_DUAL                         0x0
#define GPIO_CC_INPUT_07_0_SCR                  GPIO_CC_SCR_07_0
#define GPIO_CC_INPUT_07_0_SCRREG                       GPIO_CC_SCR_07_0
#define GPIO_CC_INPUT_07_0_WORD_COUNT                   0x1
#define GPIO_CC_INPUT_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_07_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_INPUT_07_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_07_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_07_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_CC_INPUT_07_0_GPIO_IN_RANGE                        0:0
#define GPIO_CC_INPUT_07_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_07_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_CC_INPUT_07_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_CC_INPUT_07_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_07_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_07_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CC_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_CC_OUTPUT_CONTROL_07_0
#define GPIO_CC_OUTPUT_CONTROL_07_0                     MK_ADDR_CONST(0x14ec)
#define GPIO_CC_OUTPUT_CONTROL_07_0_SECURE                      0x0
#define GPIO_CC_OUTPUT_CONTROL_07_0_DUAL                        0x0
#define GPIO_CC_OUTPUT_CONTROL_07_0_SCR                         GPIO_CC_SCR_07_0
#define GPIO_CC_OUTPUT_CONTROL_07_0_SCRREG                      GPIO_CC_SCR_07_0
#define GPIO_CC_OUTPUT_CONTROL_07_0_WORD_COUNT                  0x1
#define GPIO_CC_OUTPUT_CONTROL_07_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_CC_OUTPUT_VALUE_07_0
#define GPIO_CC_OUTPUT_VALUE_07_0                       MK_ADDR_CONST(0x14f0)
#define GPIO_CC_OUTPUT_VALUE_07_0_SECURE                        0x0
#define GPIO_CC_OUTPUT_VALUE_07_0_DUAL                  0x0
#define GPIO_CC_OUTPUT_VALUE_07_0_SCR                   GPIO_CC_SCR_07_0
#define GPIO_CC_OUTPUT_VALUE_07_0_SCRREG                        GPIO_CC_SCR_07_0
#define GPIO_CC_OUTPUT_VALUE_07_0_WORD_COUNT                    0x1
#define GPIO_CC_OUTPUT_VALUE_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_07_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_07_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_CLEAR_07_0
#define GPIO_CC_INTERRUPT_CLEAR_07_0                    MK_ADDR_CONST(0x14f4)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_SECURE                     0x0
#define GPIO_CC_INTERRUPT_CLEAR_07_0_DUAL                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_07_0_SCR                        GPIO_CC_SCR_07_0
#define GPIO_CC_INTERRUPT_CLEAR_07_0_SCRREG                     GPIO_CC_SCR_07_0
#define GPIO_CC_INTERRUPT_CLEAR_07_0_WORD_COUNT                         0x1
#define GPIO_CC_INTERRUPT_CLEAR_07_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x14f8

// Reserved address 0x14fc

// Register GPIO_CC_INTERRUPT_STATUS_G0_0
#define GPIO_CC_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x1500)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G0_0_DUAL                      0x0
#define GPIO_CC_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G0_0_SCRREG                    0
#define GPIO_CC_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_STATUS_G1_0
#define GPIO_CC_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x1504)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G1_0_DUAL                      0x0
#define GPIO_CC_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G1_0_SCRREG                    0
#define GPIO_CC_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_STATUS_G2_0
#define GPIO_CC_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x1508)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G2_0_DUAL                      0x0
#define GPIO_CC_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G2_0_SCRREG                    0
#define GPIO_CC_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_STATUS_G3_0
#define GPIO_CC_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x150c)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G3_0_DUAL                      0x0
#define GPIO_CC_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G3_0_SCRREG                    0
#define GPIO_CC_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_STATUS_G4_0
#define GPIO_CC_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x1510)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G4_0_DUAL                      0x0
#define GPIO_CC_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G4_0_SCRREG                    0
#define GPIO_CC_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_STATUS_G5_0
#define GPIO_CC_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x1514)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G5_0_DUAL                      0x0
#define GPIO_CC_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G5_0_SCRREG                    0
#define GPIO_CC_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_STATUS_G6_0
#define GPIO_CC_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x1518)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G6_0_DUAL                      0x0
#define GPIO_CC_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G6_0_SCRREG                    0
#define GPIO_CC_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CC_INTERRUPT_STATUS_G7_0
#define GPIO_CC_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x151c)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_CC_INTERRUPT_STATUS_G7_0_DUAL                      0x0
#define GPIO_CC_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_CC_INTERRUPT_STATUS_G7_0_SCRREG                    0
#define GPIO_CC_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_CC_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x1520

// Reserved address 0x1524

// Reserved address 0x1528

// Reserved address 0x152c

// Reserved address 0x1530

// Reserved address 0x1534

// Reserved address 0x1538

// Reserved address 0x153c

// Reserved address 0x1540

// Reserved address 0x1544

// Reserved address 0x1548

// Reserved address 0x154c

// Reserved address 0x1550

// Reserved address 0x1554

// Reserved address 0x1558

// Reserved address 0x155c

// Reserved address 0x1560

// Reserved address 0x1564

// Reserved address 0x1568

// Reserved address 0x156c

// Reserved address 0x1570

// Reserved address 0x1574

// Reserved address 0x1578

// Reserved address 0x157c

// Reserved address 0x1580

// Reserved address 0x1584

// Reserved address 0x1588

// Reserved address 0x158c

// Reserved address 0x1590

// Reserved address 0x1594

// Reserved address 0x1598

// Reserved address 0x159c

// Reserved address 0x15a0

// Reserved address 0x15a4

// Reserved address 0x15a8

// Reserved address 0x15ac

// Reserved address 0x15b0

// Reserved address 0x15b4

// Reserved address 0x15b8

// Reserved address 0x15bc

// Reserved address 0x15c0

// Reserved address 0x15c4

// Reserved address 0x15c8

// Reserved address 0x15cc

// Reserved address 0x15d0

// Reserved address 0x15d4

// Reserved address 0x15d8

// Reserved address 0x15dc

// Reserved address 0x15e0

// Reserved address 0x15e4

// Reserved address 0x15e8

// Reserved address 0x15ec

// Reserved address 0x15f0

// Reserved address 0x15f4

// Reserved address 0x15f8

// Reserved address 0x15fc

// Register GPIO_DD_ENABLE_CONFIG_00_0
#define GPIO_DD_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x1600)
#define GPIO_DD_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_DD_ENABLE_CONFIG_00_0_DUAL                         0x0
#define GPIO_DD_ENABLE_CONFIG_00_0_SCR                  GPIO_DD_SCR_00_0
#define GPIO_DD_ENABLE_CONFIG_00_0_SCRREG                       GPIO_DD_SCR_00_0
#define GPIO_DD_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_DD_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_DD_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_DD_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_DD_DEBOUNCE_THRESHOLD_00_0
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x1604)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_DD_SCR_00_0
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_DD_SCR_00_0
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_DD_INPUT_00_0
#define GPIO_DD_INPUT_00_0                      MK_ADDR_CONST(0x1608)
#define GPIO_DD_INPUT_00_0_SECURE                       0x0
#define GPIO_DD_INPUT_00_0_DUAL                         0x0
#define GPIO_DD_INPUT_00_0_SCR                  GPIO_DD_SCR_00_0
#define GPIO_DD_INPUT_00_0_SCRREG                       GPIO_DD_SCR_00_0
#define GPIO_DD_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_DD_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_DD_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_DD_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_DD_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_DD_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_DD_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_DD_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_DD_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_DD_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_DD_OUTPUT_CONTROL_00_0
#define GPIO_DD_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x160c)
#define GPIO_DD_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_DD_OUTPUT_CONTROL_00_0_DUAL                        0x0
#define GPIO_DD_OUTPUT_CONTROL_00_0_SCR                         GPIO_DD_SCR_00_0
#define GPIO_DD_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_DD_SCR_00_0
#define GPIO_DD_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_DD_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_DD_OUTPUT_VALUE_00_0
#define GPIO_DD_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x1610)
#define GPIO_DD_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_DD_OUTPUT_VALUE_00_0_DUAL                  0x0
#define GPIO_DD_OUTPUT_VALUE_00_0_SCR                   GPIO_DD_SCR_00_0
#define GPIO_DD_OUTPUT_VALUE_00_0_SCRREG                        GPIO_DD_SCR_00_0
#define GPIO_DD_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_DD_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_DD_INTERRUPT_CLEAR_00_0
#define GPIO_DD_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x1614)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_DD_INTERRUPT_CLEAR_00_0_DUAL                       0x0
#define GPIO_DD_INTERRUPT_CLEAR_00_0_SCR                        GPIO_DD_SCR_00_0
#define GPIO_DD_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_DD_SCR_00_0
#define GPIO_DD_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_DD_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1618

// Reserved address 0x161c

// Register GPIO_DD_ENABLE_CONFIG_01_0
#define GPIO_DD_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x1620)
#define GPIO_DD_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_DD_ENABLE_CONFIG_01_0_DUAL                         0x0
#define GPIO_DD_ENABLE_CONFIG_01_0_SCR                  GPIO_DD_SCR_01_0
#define GPIO_DD_ENABLE_CONFIG_01_0_SCRREG                       GPIO_DD_SCR_01_0
#define GPIO_DD_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_DD_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_DD_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_DD_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_DD_DEBOUNCE_THRESHOLD_01_0
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x1624)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_DD_SCR_01_0
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_DD_SCR_01_0
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_DD_INPUT_01_0
#define GPIO_DD_INPUT_01_0                      MK_ADDR_CONST(0x1628)
#define GPIO_DD_INPUT_01_0_SECURE                       0x0
#define GPIO_DD_INPUT_01_0_DUAL                         0x0
#define GPIO_DD_INPUT_01_0_SCR                  GPIO_DD_SCR_01_0
#define GPIO_DD_INPUT_01_0_SCRREG                       GPIO_DD_SCR_01_0
#define GPIO_DD_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_DD_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_DD_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_DD_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_DD_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_DD_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_DD_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_DD_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_DD_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_DD_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_DD_OUTPUT_CONTROL_01_0
#define GPIO_DD_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x162c)
#define GPIO_DD_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_DD_OUTPUT_CONTROL_01_0_DUAL                        0x0
#define GPIO_DD_OUTPUT_CONTROL_01_0_SCR                         GPIO_DD_SCR_01_0
#define GPIO_DD_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_DD_SCR_01_0
#define GPIO_DD_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_DD_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_DD_OUTPUT_VALUE_01_0
#define GPIO_DD_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x1630)
#define GPIO_DD_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_DD_OUTPUT_VALUE_01_0_DUAL                  0x0
#define GPIO_DD_OUTPUT_VALUE_01_0_SCR                   GPIO_DD_SCR_01_0
#define GPIO_DD_OUTPUT_VALUE_01_0_SCRREG                        GPIO_DD_SCR_01_0
#define GPIO_DD_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_DD_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_DD_INTERRUPT_CLEAR_01_0
#define GPIO_DD_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x1634)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_DD_INTERRUPT_CLEAR_01_0_DUAL                       0x0
#define GPIO_DD_INTERRUPT_CLEAR_01_0_SCR                        GPIO_DD_SCR_01_0
#define GPIO_DD_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_DD_SCR_01_0
#define GPIO_DD_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_DD_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1638

// Reserved address 0x163c

// Register GPIO_DD_ENABLE_CONFIG_02_0
#define GPIO_DD_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x1640)
#define GPIO_DD_ENABLE_CONFIG_02_0_SECURE                       0x0
#define GPIO_DD_ENABLE_CONFIG_02_0_DUAL                         0x0
#define GPIO_DD_ENABLE_CONFIG_02_0_SCR                  GPIO_DD_SCR_02_0
#define GPIO_DD_ENABLE_CONFIG_02_0_SCRREG                       GPIO_DD_SCR_02_0
#define GPIO_DD_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
#define GPIO_DD_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_DD_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_DD_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_DD_DEBOUNCE_THRESHOLD_02_0
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x1644)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_DD_SCR_02_0
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_DD_SCR_02_0
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_DD_INPUT_02_0
#define GPIO_DD_INPUT_02_0                      MK_ADDR_CONST(0x1648)
#define GPIO_DD_INPUT_02_0_SECURE                       0x0
#define GPIO_DD_INPUT_02_0_DUAL                         0x0
#define GPIO_DD_INPUT_02_0_SCR                  GPIO_DD_SCR_02_0
#define GPIO_DD_INPUT_02_0_SCRREG                       GPIO_DD_SCR_02_0
#define GPIO_DD_INPUT_02_0_WORD_COUNT                   0x1
#define GPIO_DD_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_DD_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_DD_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_DD_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_DD_INPUT_02_0_GPIO_IN_RANGE                        0:0
#define GPIO_DD_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_DD_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_DD_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_DD_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_DD_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_DD_OUTPUT_CONTROL_02_0
#define GPIO_DD_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x164c)
#define GPIO_DD_OUTPUT_CONTROL_02_0_SECURE                      0x0
#define GPIO_DD_OUTPUT_CONTROL_02_0_DUAL                        0x0
#define GPIO_DD_OUTPUT_CONTROL_02_0_SCR                         GPIO_DD_SCR_02_0
#define GPIO_DD_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_DD_SCR_02_0
#define GPIO_DD_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
#define GPIO_DD_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_DD_OUTPUT_VALUE_02_0
#define GPIO_DD_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x1650)
#define GPIO_DD_OUTPUT_VALUE_02_0_SECURE                        0x0
#define GPIO_DD_OUTPUT_VALUE_02_0_DUAL                  0x0
#define GPIO_DD_OUTPUT_VALUE_02_0_SCR                   GPIO_DD_SCR_02_0
#define GPIO_DD_OUTPUT_VALUE_02_0_SCRREG                        GPIO_DD_SCR_02_0
#define GPIO_DD_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
#define GPIO_DD_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_DD_INTERRUPT_CLEAR_02_0
#define GPIO_DD_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x1654)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_SECURE                     0x0
#define GPIO_DD_INTERRUPT_CLEAR_02_0_DUAL                       0x0
#define GPIO_DD_INTERRUPT_CLEAR_02_0_SCR                        GPIO_DD_SCR_02_0
#define GPIO_DD_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_DD_SCR_02_0
#define GPIO_DD_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
#define GPIO_DD_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1658

// Reserved address 0x165c

// Reserved address 0x1660

// Reserved address 0x1664

// Reserved address 0x1668

// Reserved address 0x166c

// Reserved address 0x1670

// Reserved address 0x1674

// Reserved address 0x1678

// Reserved address 0x167c

// Reserved address 0x1680

// Reserved address 0x1684

// Reserved address 0x1688

// Reserved address 0x168c

// Reserved address 0x1690

// Reserved address 0x1694

// Reserved address 0x1698

// Reserved address 0x169c

// Reserved address 0x16a0

// Reserved address 0x16a4

// Reserved address 0x16a8

// Reserved address 0x16ac

// Reserved address 0x16b0

// Reserved address 0x16b4

// Reserved address 0x16b8

// Reserved address 0x16bc

// Reserved address 0x16c0

// Reserved address 0x16c4

// Reserved address 0x16c8

// Reserved address 0x16cc

// Reserved address 0x16d0

// Reserved address 0x16d4

// Reserved address 0x16d8

// Reserved address 0x16dc

// Reserved address 0x16e0

// Reserved address 0x16e4

// Reserved address 0x16e8

// Reserved address 0x16ec

// Reserved address 0x16f0

// Reserved address 0x16f4

// Reserved address 0x16f8

// Reserved address 0x16fc

// Register GPIO_DD_INTERRUPT_STATUS_G0_0
#define GPIO_DD_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x1700)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_DD_INTERRUPT_STATUS_G0_0_DUAL                      0x0
#define GPIO_DD_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_DD_INTERRUPT_STATUS_G0_0_SCRREG                    0
#define GPIO_DD_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_DD_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_DD_INTERRUPT_STATUS_G1_0
#define GPIO_DD_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x1704)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_DD_INTERRUPT_STATUS_G1_0_DUAL                      0x0
#define GPIO_DD_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_DD_INTERRUPT_STATUS_G1_0_SCRREG                    0
#define GPIO_DD_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_DD_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_DD_INTERRUPT_STATUS_G2_0
#define GPIO_DD_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x1708)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_DD_INTERRUPT_STATUS_G2_0_DUAL                      0x0
#define GPIO_DD_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_DD_INTERRUPT_STATUS_G2_0_SCRREG                    0
#define GPIO_DD_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_DD_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_DD_INTERRUPT_STATUS_G3_0
#define GPIO_DD_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x170c)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_DD_INTERRUPT_STATUS_G3_0_DUAL                      0x0
#define GPIO_DD_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_DD_INTERRUPT_STATUS_G3_0_SCRREG                    0
#define GPIO_DD_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_DD_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_DD_INTERRUPT_STATUS_G4_0
#define GPIO_DD_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x1710)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_DD_INTERRUPT_STATUS_G4_0_DUAL                      0x0
#define GPIO_DD_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_DD_INTERRUPT_STATUS_G4_0_SCRREG                    0
#define GPIO_DD_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_DD_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_DD_INTERRUPT_STATUS_G5_0
#define GPIO_DD_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x1714)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_DD_INTERRUPT_STATUS_G5_0_DUAL                      0x0
#define GPIO_DD_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_DD_INTERRUPT_STATUS_G5_0_SCRREG                    0
#define GPIO_DD_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_DD_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_DD_INTERRUPT_STATUS_G6_0
#define GPIO_DD_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x1718)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_DD_INTERRUPT_STATUS_G6_0_DUAL                      0x0
#define GPIO_DD_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_DD_INTERRUPT_STATUS_G6_0_SCRREG                    0
#define GPIO_DD_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_DD_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_DD_INTERRUPT_STATUS_G7_0
#define GPIO_DD_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x171c)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_DD_INTERRUPT_STATUS_G7_0_DUAL                      0x0
#define GPIO_DD_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_DD_INTERRUPT_STATUS_G7_0_SCRREG                    0
#define GPIO_DD_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_DD_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x1720

// Reserved address 0x1724

// Reserved address 0x1728

// Reserved address 0x172c

// Reserved address 0x1730

// Reserved address 0x1734

// Reserved address 0x1738

// Reserved address 0x173c

// Reserved address 0x1740

// Reserved address 0x1744

// Reserved address 0x1748

// Reserved address 0x174c

// Reserved address 0x1750

// Reserved address 0x1754

// Reserved address 0x1758

// Reserved address 0x175c

// Reserved address 0x1760

// Reserved address 0x1764

// Reserved address 0x1768

// Reserved address 0x176c

// Reserved address 0x1770

// Reserved address 0x1774

// Reserved address 0x1778

// Reserved address 0x177c

// Reserved address 0x1780

// Reserved address 0x1784

// Reserved address 0x1788

// Reserved address 0x178c

// Reserved address 0x1790

// Reserved address 0x1794

// Reserved address 0x1798

// Reserved address 0x179c

// Reserved address 0x17a0

// Reserved address 0x17a4

// Reserved address 0x17a8

// Reserved address 0x17ac

// Reserved address 0x17b0

// Reserved address 0x17b4

// Reserved address 0x17b8

// Reserved address 0x17bc

// Reserved address 0x17c0

// Reserved address 0x17c4

// Reserved address 0x17c8

// Reserved address 0x17cc

// Reserved address 0x17d0

// Reserved address 0x17d4

// Reserved address 0x17d8

// Reserved address 0x17dc

// Reserved address 0x17e0

// Reserved address 0x17e4

// Reserved address 0x17e8

// Reserved address 0x17ec

// Reserved address 0x17f0

// Reserved address 0x17f4

// Reserved address 0x17f8

// Reserved address 0x17fc

// Register GPIO_AA_ENABLE_CONFIG_00_0
#define GPIO_AA_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x1800)
#define GPIO_AA_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_AA_ENABLE_CONFIG_00_0_DUAL                         0x0
#define GPIO_AA_ENABLE_CONFIG_00_0_SCR                  GPIO_AA_SCR_00_0
#define GPIO_AA_ENABLE_CONFIG_00_0_SCRREG                       GPIO_AA_SCR_00_0
#define GPIO_AA_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_AA_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AA_DEBOUNCE_THRESHOLD_00_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x1804)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_AA_SCR_00_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_AA_SCR_00_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_INPUT_00_0
#define GPIO_AA_INPUT_00_0                      MK_ADDR_CONST(0x1808)
#define GPIO_AA_INPUT_00_0_SECURE                       0x0
#define GPIO_AA_INPUT_00_0_DUAL                         0x0
#define GPIO_AA_INPUT_00_0_SCR                  GPIO_AA_SCR_00_0
#define GPIO_AA_INPUT_00_0_SCRREG                       GPIO_AA_SCR_00_0
#define GPIO_AA_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_AA_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_AA_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_AA_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AA_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_OUTPUT_CONTROL_00_0
#define GPIO_AA_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x180c)
#define GPIO_AA_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_AA_OUTPUT_CONTROL_00_0_DUAL                        0x0
#define GPIO_AA_OUTPUT_CONTROL_00_0_SCR                         GPIO_AA_SCR_00_0
#define GPIO_AA_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_AA_SCR_00_0
#define GPIO_AA_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_AA_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AA_OUTPUT_VALUE_00_0
#define GPIO_AA_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x1810)
#define GPIO_AA_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_AA_OUTPUT_VALUE_00_0_DUAL                  0x0
#define GPIO_AA_OUTPUT_VALUE_00_0_SCR                   GPIO_AA_SCR_00_0
#define GPIO_AA_OUTPUT_VALUE_00_0_SCRREG                        GPIO_AA_SCR_00_0
#define GPIO_AA_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_AA_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_CLEAR_00_0
#define GPIO_AA_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x1814)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_AA_INTERRUPT_CLEAR_00_0_DUAL                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_00_0_SCR                        GPIO_AA_SCR_00_0
#define GPIO_AA_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_AA_SCR_00_0
#define GPIO_AA_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_AA_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1818

// Reserved address 0x181c

// Register GPIO_AA_ENABLE_CONFIG_01_0
#define GPIO_AA_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x1820)
#define GPIO_AA_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_AA_ENABLE_CONFIG_01_0_DUAL                         0x0
#define GPIO_AA_ENABLE_CONFIG_01_0_SCR                  GPIO_AA_SCR_01_0
#define GPIO_AA_ENABLE_CONFIG_01_0_SCRREG                       GPIO_AA_SCR_01_0
#define GPIO_AA_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_AA_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AA_DEBOUNCE_THRESHOLD_01_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x1824)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_AA_SCR_01_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_AA_SCR_01_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_INPUT_01_0
#define GPIO_AA_INPUT_01_0                      MK_ADDR_CONST(0x1828)
#define GPIO_AA_INPUT_01_0_SECURE                       0x0
#define GPIO_AA_INPUT_01_0_DUAL                         0x0
#define GPIO_AA_INPUT_01_0_SCR                  GPIO_AA_SCR_01_0
#define GPIO_AA_INPUT_01_0_SCRREG                       GPIO_AA_SCR_01_0
#define GPIO_AA_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_AA_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_AA_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_AA_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AA_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_OUTPUT_CONTROL_01_0
#define GPIO_AA_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x182c)
#define GPIO_AA_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_AA_OUTPUT_CONTROL_01_0_DUAL                        0x0
#define GPIO_AA_OUTPUT_CONTROL_01_0_SCR                         GPIO_AA_SCR_01_0
#define GPIO_AA_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_AA_SCR_01_0
#define GPIO_AA_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_AA_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AA_OUTPUT_VALUE_01_0
#define GPIO_AA_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x1830)
#define GPIO_AA_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_AA_OUTPUT_VALUE_01_0_DUAL                  0x0
#define GPIO_AA_OUTPUT_VALUE_01_0_SCR                   GPIO_AA_SCR_01_0
#define GPIO_AA_OUTPUT_VALUE_01_0_SCRREG                        GPIO_AA_SCR_01_0
#define GPIO_AA_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_AA_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_CLEAR_01_0
#define GPIO_AA_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x1834)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_AA_INTERRUPT_CLEAR_01_0_DUAL                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_01_0_SCR                        GPIO_AA_SCR_01_0
#define GPIO_AA_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_AA_SCR_01_0
#define GPIO_AA_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_AA_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1838

// Reserved address 0x183c

// Register GPIO_AA_ENABLE_CONFIG_02_0
#define GPIO_AA_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x1840)
#define GPIO_AA_ENABLE_CONFIG_02_0_SECURE                       0x0
#define GPIO_AA_ENABLE_CONFIG_02_0_DUAL                         0x0
#define GPIO_AA_ENABLE_CONFIG_02_0_SCR                  GPIO_AA_SCR_02_0
#define GPIO_AA_ENABLE_CONFIG_02_0_SCRREG                       GPIO_AA_SCR_02_0
#define GPIO_AA_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
#define GPIO_AA_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AA_DEBOUNCE_THRESHOLD_02_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x1844)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_AA_SCR_02_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_AA_SCR_02_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_INPUT_02_0
#define GPIO_AA_INPUT_02_0                      MK_ADDR_CONST(0x1848)
#define GPIO_AA_INPUT_02_0_SECURE                       0x0
#define GPIO_AA_INPUT_02_0_DUAL                         0x0
#define GPIO_AA_INPUT_02_0_SCR                  GPIO_AA_SCR_02_0
#define GPIO_AA_INPUT_02_0_SCRREG                       GPIO_AA_SCR_02_0
#define GPIO_AA_INPUT_02_0_WORD_COUNT                   0x1
#define GPIO_AA_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_AA_INPUT_02_0_GPIO_IN_RANGE                        0:0
#define GPIO_AA_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AA_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_OUTPUT_CONTROL_02_0
#define GPIO_AA_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x184c)
#define GPIO_AA_OUTPUT_CONTROL_02_0_SECURE                      0x0
#define GPIO_AA_OUTPUT_CONTROL_02_0_DUAL                        0x0
#define GPIO_AA_OUTPUT_CONTROL_02_0_SCR                         GPIO_AA_SCR_02_0
#define GPIO_AA_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_AA_SCR_02_0
#define GPIO_AA_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
#define GPIO_AA_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AA_OUTPUT_VALUE_02_0
#define GPIO_AA_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x1850)
#define GPIO_AA_OUTPUT_VALUE_02_0_SECURE                        0x0
#define GPIO_AA_OUTPUT_VALUE_02_0_DUAL                  0x0
#define GPIO_AA_OUTPUT_VALUE_02_0_SCR                   GPIO_AA_SCR_02_0
#define GPIO_AA_OUTPUT_VALUE_02_0_SCRREG                        GPIO_AA_SCR_02_0
#define GPIO_AA_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
#define GPIO_AA_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_CLEAR_02_0
#define GPIO_AA_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x1854)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_SECURE                     0x0
#define GPIO_AA_INTERRUPT_CLEAR_02_0_DUAL                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_02_0_SCR                        GPIO_AA_SCR_02_0
#define GPIO_AA_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_AA_SCR_02_0
#define GPIO_AA_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
#define GPIO_AA_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1858

// Reserved address 0x185c

// Register GPIO_AA_ENABLE_CONFIG_03_0
#define GPIO_AA_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x1860)
#define GPIO_AA_ENABLE_CONFIG_03_0_SECURE                       0x0
#define GPIO_AA_ENABLE_CONFIG_03_0_DUAL                         0x0
#define GPIO_AA_ENABLE_CONFIG_03_0_SCR                  GPIO_AA_SCR_03_0
#define GPIO_AA_ENABLE_CONFIG_03_0_SCRREG                       GPIO_AA_SCR_03_0
#define GPIO_AA_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
#define GPIO_AA_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AA_DEBOUNCE_THRESHOLD_03_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x1864)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_AA_SCR_03_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_AA_SCR_03_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_INPUT_03_0
#define GPIO_AA_INPUT_03_0                      MK_ADDR_CONST(0x1868)
#define GPIO_AA_INPUT_03_0_SECURE                       0x0
#define GPIO_AA_INPUT_03_0_DUAL                         0x0
#define GPIO_AA_INPUT_03_0_SCR                  GPIO_AA_SCR_03_0
#define GPIO_AA_INPUT_03_0_SCRREG                       GPIO_AA_SCR_03_0
#define GPIO_AA_INPUT_03_0_WORD_COUNT                   0x1
#define GPIO_AA_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_AA_INPUT_03_0_GPIO_IN_RANGE                        0:0
#define GPIO_AA_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AA_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_OUTPUT_CONTROL_03_0
#define GPIO_AA_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x186c)
#define GPIO_AA_OUTPUT_CONTROL_03_0_SECURE                      0x0
#define GPIO_AA_OUTPUT_CONTROL_03_0_DUAL                        0x0
#define GPIO_AA_OUTPUT_CONTROL_03_0_SCR                         GPIO_AA_SCR_03_0
#define GPIO_AA_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_AA_SCR_03_0
#define GPIO_AA_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
#define GPIO_AA_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AA_OUTPUT_VALUE_03_0
#define GPIO_AA_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x1870)
#define GPIO_AA_OUTPUT_VALUE_03_0_SECURE                        0x0
#define GPIO_AA_OUTPUT_VALUE_03_0_DUAL                  0x0
#define GPIO_AA_OUTPUT_VALUE_03_0_SCR                   GPIO_AA_SCR_03_0
#define GPIO_AA_OUTPUT_VALUE_03_0_SCRREG                        GPIO_AA_SCR_03_0
#define GPIO_AA_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
#define GPIO_AA_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_CLEAR_03_0
#define GPIO_AA_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x1874)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_SECURE                     0x0
#define GPIO_AA_INTERRUPT_CLEAR_03_0_DUAL                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_03_0_SCR                        GPIO_AA_SCR_03_0
#define GPIO_AA_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_AA_SCR_03_0
#define GPIO_AA_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
#define GPIO_AA_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1878

// Reserved address 0x187c

// Register GPIO_AA_ENABLE_CONFIG_04_0
#define GPIO_AA_ENABLE_CONFIG_04_0                      MK_ADDR_CONST(0x1880)
#define GPIO_AA_ENABLE_CONFIG_04_0_SECURE                       0x0
#define GPIO_AA_ENABLE_CONFIG_04_0_DUAL                         0x0
#define GPIO_AA_ENABLE_CONFIG_04_0_SCR                  GPIO_AA_SCR_04_0
#define GPIO_AA_ENABLE_CONFIG_04_0_SCRREG                       GPIO_AA_SCR_04_0
#define GPIO_AA_ENABLE_CONFIG_04_0_WORD_COUNT                   0x1
#define GPIO_AA_ENABLE_CONFIG_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_04_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_RANGE                 1:1
#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AA_DEBOUNCE_THRESHOLD_04_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0                 MK_ADDR_CONST(0x1884)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_SECURE                  0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DUAL                    0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_SCR                     GPIO_AA_SCR_04_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_SCRREG                  GPIO_AA_SCR_04_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                      0x1
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_INPUT_04_0
#define GPIO_AA_INPUT_04_0                      MK_ADDR_CONST(0x1888)
#define GPIO_AA_INPUT_04_0_SECURE                       0x0
#define GPIO_AA_INPUT_04_0_DUAL                         0x0
#define GPIO_AA_INPUT_04_0_SCR                  GPIO_AA_SCR_04_0
#define GPIO_AA_INPUT_04_0_SCRREG                       GPIO_AA_SCR_04_0
#define GPIO_AA_INPUT_04_0_WORD_COUNT                   0x1
#define GPIO_AA_INPUT_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_04_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_INPUT_04_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_04_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_04_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_AA_INPUT_04_0_GPIO_IN_RANGE                        0:0
#define GPIO_AA_INPUT_04_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_04_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_04_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AA_INPUT_04_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_04_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_04_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_OUTPUT_CONTROL_04_0
#define GPIO_AA_OUTPUT_CONTROL_04_0                     MK_ADDR_CONST(0x188c)
#define GPIO_AA_OUTPUT_CONTROL_04_0_SECURE                      0x0
#define GPIO_AA_OUTPUT_CONTROL_04_0_DUAL                        0x0
#define GPIO_AA_OUTPUT_CONTROL_04_0_SCR                         GPIO_AA_SCR_04_0
#define GPIO_AA_OUTPUT_CONTROL_04_0_SCRREG                      GPIO_AA_SCR_04_0
#define GPIO_AA_OUTPUT_CONTROL_04_0_WORD_COUNT                  0x1
#define GPIO_AA_OUTPUT_CONTROL_04_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AA_OUTPUT_VALUE_04_0
#define GPIO_AA_OUTPUT_VALUE_04_0                       MK_ADDR_CONST(0x1890)
#define GPIO_AA_OUTPUT_VALUE_04_0_SECURE                        0x0
#define GPIO_AA_OUTPUT_VALUE_04_0_DUAL                  0x0
#define GPIO_AA_OUTPUT_VALUE_04_0_SCR                   GPIO_AA_SCR_04_0
#define GPIO_AA_OUTPUT_VALUE_04_0_SCRREG                        GPIO_AA_SCR_04_0
#define GPIO_AA_OUTPUT_VALUE_04_0_WORD_COUNT                    0x1
#define GPIO_AA_OUTPUT_VALUE_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_04_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_04_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_CLEAR_04_0
#define GPIO_AA_INTERRUPT_CLEAR_04_0                    MK_ADDR_CONST(0x1894)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_SECURE                     0x0
#define GPIO_AA_INTERRUPT_CLEAR_04_0_DUAL                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_04_0_SCR                        GPIO_AA_SCR_04_0
#define GPIO_AA_INTERRUPT_CLEAR_04_0_SCRREG                     GPIO_AA_SCR_04_0
#define GPIO_AA_INTERRUPT_CLEAR_04_0_WORD_COUNT                         0x1
#define GPIO_AA_INTERRUPT_CLEAR_04_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1898

// Reserved address 0x189c

// Register GPIO_AA_ENABLE_CONFIG_05_0
#define GPIO_AA_ENABLE_CONFIG_05_0                      MK_ADDR_CONST(0x18a0)
#define GPIO_AA_ENABLE_CONFIG_05_0_SECURE                       0x0
#define GPIO_AA_ENABLE_CONFIG_05_0_DUAL                         0x0
#define GPIO_AA_ENABLE_CONFIG_05_0_SCR                  GPIO_AA_SCR_05_0
#define GPIO_AA_ENABLE_CONFIG_05_0_SCRREG                       GPIO_AA_SCR_05_0
#define GPIO_AA_ENABLE_CONFIG_05_0_WORD_COUNT                   0x1
#define GPIO_AA_ENABLE_CONFIG_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_05_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_RANGE                 1:1
#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AA_DEBOUNCE_THRESHOLD_05_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0                 MK_ADDR_CONST(0x18a4)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_SECURE                  0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DUAL                    0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_SCR                     GPIO_AA_SCR_05_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_SCRREG                  GPIO_AA_SCR_05_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                      0x1
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_INPUT_05_0
#define GPIO_AA_INPUT_05_0                      MK_ADDR_CONST(0x18a8)
#define GPIO_AA_INPUT_05_0_SECURE                       0x0
#define GPIO_AA_INPUT_05_0_DUAL                         0x0
#define GPIO_AA_INPUT_05_0_SCR                  GPIO_AA_SCR_05_0
#define GPIO_AA_INPUT_05_0_SCRREG                       GPIO_AA_SCR_05_0
#define GPIO_AA_INPUT_05_0_WORD_COUNT                   0x1
#define GPIO_AA_INPUT_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_05_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_INPUT_05_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_05_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_05_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_AA_INPUT_05_0_GPIO_IN_RANGE                        0:0
#define GPIO_AA_INPUT_05_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_05_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_05_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AA_INPUT_05_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_05_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_05_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_OUTPUT_CONTROL_05_0
#define GPIO_AA_OUTPUT_CONTROL_05_0                     MK_ADDR_CONST(0x18ac)
#define GPIO_AA_OUTPUT_CONTROL_05_0_SECURE                      0x0
#define GPIO_AA_OUTPUT_CONTROL_05_0_DUAL                        0x0
#define GPIO_AA_OUTPUT_CONTROL_05_0_SCR                         GPIO_AA_SCR_05_0
#define GPIO_AA_OUTPUT_CONTROL_05_0_SCRREG                      GPIO_AA_SCR_05_0
#define GPIO_AA_OUTPUT_CONTROL_05_0_WORD_COUNT                  0x1
#define GPIO_AA_OUTPUT_CONTROL_05_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AA_OUTPUT_VALUE_05_0
#define GPIO_AA_OUTPUT_VALUE_05_0                       MK_ADDR_CONST(0x18b0)
#define GPIO_AA_OUTPUT_VALUE_05_0_SECURE                        0x0
#define GPIO_AA_OUTPUT_VALUE_05_0_DUAL                  0x0
#define GPIO_AA_OUTPUT_VALUE_05_0_SCR                   GPIO_AA_SCR_05_0
#define GPIO_AA_OUTPUT_VALUE_05_0_SCRREG                        GPIO_AA_SCR_05_0
#define GPIO_AA_OUTPUT_VALUE_05_0_WORD_COUNT                    0x1
#define GPIO_AA_OUTPUT_VALUE_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_05_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_05_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_CLEAR_05_0
#define GPIO_AA_INTERRUPT_CLEAR_05_0                    MK_ADDR_CONST(0x18b4)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_SECURE                     0x0
#define GPIO_AA_INTERRUPT_CLEAR_05_0_DUAL                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_05_0_SCR                        GPIO_AA_SCR_05_0
#define GPIO_AA_INTERRUPT_CLEAR_05_0_SCRREG                     GPIO_AA_SCR_05_0
#define GPIO_AA_INTERRUPT_CLEAR_05_0_WORD_COUNT                         0x1
#define GPIO_AA_INTERRUPT_CLEAR_05_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x18b8

// Reserved address 0x18bc

// Register GPIO_AA_ENABLE_CONFIG_06_0
#define GPIO_AA_ENABLE_CONFIG_06_0                      MK_ADDR_CONST(0x18c0)
#define GPIO_AA_ENABLE_CONFIG_06_0_SECURE                       0x0
#define GPIO_AA_ENABLE_CONFIG_06_0_DUAL                         0x0
#define GPIO_AA_ENABLE_CONFIG_06_0_SCR                  GPIO_AA_SCR_06_0
#define GPIO_AA_ENABLE_CONFIG_06_0_SCRREG                       GPIO_AA_SCR_06_0
#define GPIO_AA_ENABLE_CONFIG_06_0_WORD_COUNT                   0x1
#define GPIO_AA_ENABLE_CONFIG_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_06_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_RANGE                 1:1
#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AA_DEBOUNCE_THRESHOLD_06_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0                 MK_ADDR_CONST(0x18c4)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_SECURE                  0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DUAL                    0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_SCR                     GPIO_AA_SCR_06_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_SCRREG                  GPIO_AA_SCR_06_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                      0x1
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_INPUT_06_0
#define GPIO_AA_INPUT_06_0                      MK_ADDR_CONST(0x18c8)
#define GPIO_AA_INPUT_06_0_SECURE                       0x0
#define GPIO_AA_INPUT_06_0_DUAL                         0x0
#define GPIO_AA_INPUT_06_0_SCR                  GPIO_AA_SCR_06_0
#define GPIO_AA_INPUT_06_0_SCRREG                       GPIO_AA_SCR_06_0
#define GPIO_AA_INPUT_06_0_WORD_COUNT                   0x1
#define GPIO_AA_INPUT_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_06_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_INPUT_06_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_06_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_06_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_AA_INPUT_06_0_GPIO_IN_RANGE                        0:0
#define GPIO_AA_INPUT_06_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_06_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_06_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AA_INPUT_06_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_06_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_06_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_OUTPUT_CONTROL_06_0
#define GPIO_AA_OUTPUT_CONTROL_06_0                     MK_ADDR_CONST(0x18cc)
#define GPIO_AA_OUTPUT_CONTROL_06_0_SECURE                      0x0
#define GPIO_AA_OUTPUT_CONTROL_06_0_DUAL                        0x0
#define GPIO_AA_OUTPUT_CONTROL_06_0_SCR                         GPIO_AA_SCR_06_0
#define GPIO_AA_OUTPUT_CONTROL_06_0_SCRREG                      GPIO_AA_SCR_06_0
#define GPIO_AA_OUTPUT_CONTROL_06_0_WORD_COUNT                  0x1
#define GPIO_AA_OUTPUT_CONTROL_06_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AA_OUTPUT_VALUE_06_0
#define GPIO_AA_OUTPUT_VALUE_06_0                       MK_ADDR_CONST(0x18d0)
#define GPIO_AA_OUTPUT_VALUE_06_0_SECURE                        0x0
#define GPIO_AA_OUTPUT_VALUE_06_0_DUAL                  0x0
#define GPIO_AA_OUTPUT_VALUE_06_0_SCR                   GPIO_AA_SCR_06_0
#define GPIO_AA_OUTPUT_VALUE_06_0_SCRREG                        GPIO_AA_SCR_06_0
#define GPIO_AA_OUTPUT_VALUE_06_0_WORD_COUNT                    0x1
#define GPIO_AA_OUTPUT_VALUE_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_06_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_06_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_CLEAR_06_0
#define GPIO_AA_INTERRUPT_CLEAR_06_0                    MK_ADDR_CONST(0x18d4)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_SECURE                     0x0
#define GPIO_AA_INTERRUPT_CLEAR_06_0_DUAL                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_06_0_SCR                        GPIO_AA_SCR_06_0
#define GPIO_AA_INTERRUPT_CLEAR_06_0_SCRREG                     GPIO_AA_SCR_06_0
#define GPIO_AA_INTERRUPT_CLEAR_06_0_WORD_COUNT                         0x1
#define GPIO_AA_INTERRUPT_CLEAR_06_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x18d8

// Reserved address 0x18dc

// Register GPIO_AA_ENABLE_CONFIG_07_0
#define GPIO_AA_ENABLE_CONFIG_07_0                      MK_ADDR_CONST(0x18e0)
#define GPIO_AA_ENABLE_CONFIG_07_0_SECURE                       0x0
#define GPIO_AA_ENABLE_CONFIG_07_0_DUAL                         0x0
#define GPIO_AA_ENABLE_CONFIG_07_0_SCR                  GPIO_AA_SCR_07_0
#define GPIO_AA_ENABLE_CONFIG_07_0_SCRREG                       GPIO_AA_SCR_07_0
#define GPIO_AA_ENABLE_CONFIG_07_0_WORD_COUNT                   0x1
#define GPIO_AA_ENABLE_CONFIG_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_07_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_RANGE                 1:1
#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AA_DEBOUNCE_THRESHOLD_07_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0                 MK_ADDR_CONST(0x18e4)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_SECURE                  0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DUAL                    0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_SCR                     GPIO_AA_SCR_07_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_SCRREG                  GPIO_AA_SCR_07_0
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                      0x1
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_INPUT_07_0
#define GPIO_AA_INPUT_07_0                      MK_ADDR_CONST(0x18e8)
#define GPIO_AA_INPUT_07_0_SECURE                       0x0
#define GPIO_AA_INPUT_07_0_DUAL                         0x0
#define GPIO_AA_INPUT_07_0_SCR                  GPIO_AA_SCR_07_0
#define GPIO_AA_INPUT_07_0_SCRREG                       GPIO_AA_SCR_07_0
#define GPIO_AA_INPUT_07_0_WORD_COUNT                   0x1
#define GPIO_AA_INPUT_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_07_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_INPUT_07_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_07_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_07_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_AA_INPUT_07_0_GPIO_IN_RANGE                        0:0
#define GPIO_AA_INPUT_07_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_07_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AA_INPUT_07_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AA_INPUT_07_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_07_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_07_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AA_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AA_OUTPUT_CONTROL_07_0
#define GPIO_AA_OUTPUT_CONTROL_07_0                     MK_ADDR_CONST(0x18ec)
#define GPIO_AA_OUTPUT_CONTROL_07_0_SECURE                      0x0
#define GPIO_AA_OUTPUT_CONTROL_07_0_DUAL                        0x0
#define GPIO_AA_OUTPUT_CONTROL_07_0_SCR                         GPIO_AA_SCR_07_0
#define GPIO_AA_OUTPUT_CONTROL_07_0_SCRREG                      GPIO_AA_SCR_07_0
#define GPIO_AA_OUTPUT_CONTROL_07_0_WORD_COUNT                  0x1
#define GPIO_AA_OUTPUT_CONTROL_07_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AA_OUTPUT_VALUE_07_0
#define GPIO_AA_OUTPUT_VALUE_07_0                       MK_ADDR_CONST(0x18f0)
#define GPIO_AA_OUTPUT_VALUE_07_0_SECURE                        0x0
#define GPIO_AA_OUTPUT_VALUE_07_0_DUAL                  0x0
#define GPIO_AA_OUTPUT_VALUE_07_0_SCR                   GPIO_AA_SCR_07_0
#define GPIO_AA_OUTPUT_VALUE_07_0_SCRREG                        GPIO_AA_SCR_07_0
#define GPIO_AA_OUTPUT_VALUE_07_0_WORD_COUNT                    0x1
#define GPIO_AA_OUTPUT_VALUE_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_07_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_07_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_CLEAR_07_0
#define GPIO_AA_INTERRUPT_CLEAR_07_0                    MK_ADDR_CONST(0x18f4)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_SECURE                     0x0
#define GPIO_AA_INTERRUPT_CLEAR_07_0_DUAL                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_07_0_SCR                        GPIO_AA_SCR_07_0
#define GPIO_AA_INTERRUPT_CLEAR_07_0_SCRREG                     GPIO_AA_SCR_07_0
#define GPIO_AA_INTERRUPT_CLEAR_07_0_WORD_COUNT                         0x1
#define GPIO_AA_INTERRUPT_CLEAR_07_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x18f8

// Reserved address 0x18fc

// Register GPIO_AA_INTERRUPT_STATUS_G0_0
#define GPIO_AA_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x1900)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_AA_INTERRUPT_STATUS_G0_0_DUAL                      0x0
#define GPIO_AA_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_AA_INTERRUPT_STATUS_G0_0_SCRREG                    0
#define GPIO_AA_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_AA_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_STATUS_G1_0
#define GPIO_AA_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x1904)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_AA_INTERRUPT_STATUS_G1_0_DUAL                      0x0
#define GPIO_AA_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_AA_INTERRUPT_STATUS_G1_0_SCRREG                    0
#define GPIO_AA_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_AA_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_STATUS_G2_0
#define GPIO_AA_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x1908)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_AA_INTERRUPT_STATUS_G2_0_DUAL                      0x0
#define GPIO_AA_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_AA_INTERRUPT_STATUS_G2_0_SCRREG                    0
#define GPIO_AA_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_AA_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_STATUS_G3_0
#define GPIO_AA_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x190c)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_AA_INTERRUPT_STATUS_G3_0_DUAL                      0x0
#define GPIO_AA_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_AA_INTERRUPT_STATUS_G3_0_SCRREG                    0
#define GPIO_AA_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_AA_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_STATUS_G4_0
#define GPIO_AA_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x1910)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_AA_INTERRUPT_STATUS_G4_0_DUAL                      0x0
#define GPIO_AA_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_AA_INTERRUPT_STATUS_G4_0_SCRREG                    0
#define GPIO_AA_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_AA_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_STATUS_G5_0
#define GPIO_AA_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x1914)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_AA_INTERRUPT_STATUS_G5_0_DUAL                      0x0
#define GPIO_AA_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_AA_INTERRUPT_STATUS_G5_0_SCRREG                    0
#define GPIO_AA_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_AA_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_STATUS_G6_0
#define GPIO_AA_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x1918)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_AA_INTERRUPT_STATUS_G6_0_DUAL                      0x0
#define GPIO_AA_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_AA_INTERRUPT_STATUS_G6_0_SCRREG                    0
#define GPIO_AA_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_AA_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AA_INTERRUPT_STATUS_G7_0
#define GPIO_AA_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x191c)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_AA_INTERRUPT_STATUS_G7_0_DUAL                      0x0
#define GPIO_AA_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_AA_INTERRUPT_STATUS_G7_0_SCRREG                    0
#define GPIO_AA_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_AA_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x1920

// Reserved address 0x1924

// Reserved address 0x1928

// Reserved address 0x192c

// Reserved address 0x1930

// Reserved address 0x1934

// Reserved address 0x1938

// Reserved address 0x193c

// Reserved address 0x1940

// Reserved address 0x1944

// Reserved address 0x1948

// Reserved address 0x194c

// Reserved address 0x1950

// Reserved address 0x1954

// Reserved address 0x1958

// Reserved address 0x195c

// Reserved address 0x1960

// Reserved address 0x1964

// Reserved address 0x1968

// Reserved address 0x196c

// Reserved address 0x1970

// Reserved address 0x1974

// Reserved address 0x1978

// Reserved address 0x197c

// Reserved address 0x1980

// Reserved address 0x1984

// Reserved address 0x1988

// Reserved address 0x198c

// Reserved address 0x1990

// Reserved address 0x1994

// Reserved address 0x1998

// Reserved address 0x199c

// Reserved address 0x19a0

// Reserved address 0x19a4

// Reserved address 0x19a8

// Reserved address 0x19ac

// Reserved address 0x19b0

// Reserved address 0x19b4

// Reserved address 0x19b8

// Reserved address 0x19bc

// Reserved address 0x19c0

// Reserved address 0x19c4

// Reserved address 0x19c8

// Reserved address 0x19cc

// Reserved address 0x19d0

// Reserved address 0x19d4

// Reserved address 0x19d8

// Reserved address 0x19dc

// Reserved address 0x19e0

// Reserved address 0x19e4

// Reserved address 0x19e8

// Reserved address 0x19ec

// Reserved address 0x19f0

// Reserved address 0x19f4

// Reserved address 0x19f8

// Reserved address 0x19fc

// Register GPIO_BB_ENABLE_CONFIG_00_0
#define GPIO_BB_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x1a00)
#define GPIO_BB_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_DUAL                         0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_SCR                  GPIO_BB_SCR_00_0
#define GPIO_BB_ENABLE_CONFIG_00_0_SCRREG                       GPIO_BB_SCR_00_0
#define GPIO_BB_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_BB_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_BB_DEBOUNCE_THRESHOLD_00_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x1a04)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_BB_SCR_00_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_BB_SCR_00_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_BB_INPUT_00_0
#define GPIO_BB_INPUT_00_0                      MK_ADDR_CONST(0x1a08)
#define GPIO_BB_INPUT_00_0_SECURE                       0x0
#define GPIO_BB_INPUT_00_0_DUAL                         0x0
#define GPIO_BB_INPUT_00_0_SCR                  GPIO_BB_SCR_00_0
#define GPIO_BB_INPUT_00_0_SCRREG                       GPIO_BB_SCR_00_0
#define GPIO_BB_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_BB_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_BB_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_BB_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_BB_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_BB_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_BB_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_BB_OUTPUT_CONTROL_00_0
#define GPIO_BB_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x1a0c)
#define GPIO_BB_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_BB_OUTPUT_CONTROL_00_0_DUAL                        0x0
#define GPIO_BB_OUTPUT_CONTROL_00_0_SCR                         GPIO_BB_SCR_00_0
#define GPIO_BB_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_BB_SCR_00_0
#define GPIO_BB_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_BB_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_BB_OUTPUT_VALUE_00_0
#define GPIO_BB_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x1a10)
#define GPIO_BB_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_BB_OUTPUT_VALUE_00_0_DUAL                  0x0
#define GPIO_BB_OUTPUT_VALUE_00_0_SCR                   GPIO_BB_SCR_00_0
#define GPIO_BB_OUTPUT_VALUE_00_0_SCRREG                        GPIO_BB_SCR_00_0
#define GPIO_BB_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_BB_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_BB_INTERRUPT_CLEAR_00_0
#define GPIO_BB_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x1a14)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_BB_INTERRUPT_CLEAR_00_0_DUAL                       0x0
#define GPIO_BB_INTERRUPT_CLEAR_00_0_SCR                        GPIO_BB_SCR_00_0
#define GPIO_BB_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_BB_SCR_00_0
#define GPIO_BB_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_BB_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1a18

// Reserved address 0x1a1c

// Register GPIO_BB_ENABLE_CONFIG_01_0
#define GPIO_BB_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x1a20)
#define GPIO_BB_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_DUAL                         0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_SCR                  GPIO_BB_SCR_01_0
#define GPIO_BB_ENABLE_CONFIG_01_0_SCRREG                       GPIO_BB_SCR_01_0
#define GPIO_BB_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_BB_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_BB_DEBOUNCE_THRESHOLD_01_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x1a24)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_BB_SCR_01_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_BB_SCR_01_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_BB_INPUT_01_0
#define GPIO_BB_INPUT_01_0                      MK_ADDR_CONST(0x1a28)
#define GPIO_BB_INPUT_01_0_SECURE                       0x0
#define GPIO_BB_INPUT_01_0_DUAL                         0x0
#define GPIO_BB_INPUT_01_0_SCR                  GPIO_BB_SCR_01_0
#define GPIO_BB_INPUT_01_0_SCRREG                       GPIO_BB_SCR_01_0
#define GPIO_BB_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_BB_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_BB_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_BB_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_BB_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_BB_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_BB_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_BB_OUTPUT_CONTROL_01_0
#define GPIO_BB_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x1a2c)
#define GPIO_BB_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_BB_OUTPUT_CONTROL_01_0_DUAL                        0x0
#define GPIO_BB_OUTPUT_CONTROL_01_0_SCR                         GPIO_BB_SCR_01_0
#define GPIO_BB_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_BB_SCR_01_0
#define GPIO_BB_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_BB_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_BB_OUTPUT_VALUE_01_0
#define GPIO_BB_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x1a30)
#define GPIO_BB_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_BB_OUTPUT_VALUE_01_0_DUAL                  0x0
#define GPIO_BB_OUTPUT_VALUE_01_0_SCR                   GPIO_BB_SCR_01_0
#define GPIO_BB_OUTPUT_VALUE_01_0_SCRREG                        GPIO_BB_SCR_01_0
#define GPIO_BB_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_BB_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_BB_INTERRUPT_CLEAR_01_0
#define GPIO_BB_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x1a34)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_BB_INTERRUPT_CLEAR_01_0_DUAL                       0x0
#define GPIO_BB_INTERRUPT_CLEAR_01_0_SCR                        GPIO_BB_SCR_01_0
#define GPIO_BB_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_BB_SCR_01_0
#define GPIO_BB_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_BB_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1a38

// Reserved address 0x1a3c

// Register GPIO_BB_ENABLE_CONFIG_02_0
#define GPIO_BB_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x1a40)
#define GPIO_BB_ENABLE_CONFIG_02_0_SECURE                       0x0
#define GPIO_BB_ENABLE_CONFIG_02_0_DUAL                         0x0
#define GPIO_BB_ENABLE_CONFIG_02_0_SCR                  GPIO_BB_SCR_02_0
#define GPIO_BB_ENABLE_CONFIG_02_0_SCRREG                       GPIO_BB_SCR_02_0
#define GPIO_BB_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
#define GPIO_BB_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_BB_DEBOUNCE_THRESHOLD_02_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x1a44)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_BB_SCR_02_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_BB_SCR_02_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_BB_INPUT_02_0
#define GPIO_BB_INPUT_02_0                      MK_ADDR_CONST(0x1a48)
#define GPIO_BB_INPUT_02_0_SECURE                       0x0
#define GPIO_BB_INPUT_02_0_DUAL                         0x0
#define GPIO_BB_INPUT_02_0_SCR                  GPIO_BB_SCR_02_0
#define GPIO_BB_INPUT_02_0_SCRREG                       GPIO_BB_SCR_02_0
#define GPIO_BB_INPUT_02_0_WORD_COUNT                   0x1
#define GPIO_BB_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_BB_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_BB_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_BB_INPUT_02_0_GPIO_IN_RANGE                        0:0
#define GPIO_BB_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_BB_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_BB_OUTPUT_CONTROL_02_0
#define GPIO_BB_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x1a4c)
#define GPIO_BB_OUTPUT_CONTROL_02_0_SECURE                      0x0
#define GPIO_BB_OUTPUT_CONTROL_02_0_DUAL                        0x0
#define GPIO_BB_OUTPUT_CONTROL_02_0_SCR                         GPIO_BB_SCR_02_0
#define GPIO_BB_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_BB_SCR_02_0
#define GPIO_BB_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
#define GPIO_BB_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_BB_OUTPUT_VALUE_02_0
#define GPIO_BB_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x1a50)
#define GPIO_BB_OUTPUT_VALUE_02_0_SECURE                        0x0
#define GPIO_BB_OUTPUT_VALUE_02_0_DUAL                  0x0
#define GPIO_BB_OUTPUT_VALUE_02_0_SCR                   GPIO_BB_SCR_02_0
#define GPIO_BB_OUTPUT_VALUE_02_0_SCRREG                        GPIO_BB_SCR_02_0
#define GPIO_BB_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
#define GPIO_BB_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_BB_INTERRUPT_CLEAR_02_0
#define GPIO_BB_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x1a54)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_SECURE                     0x0
#define GPIO_BB_INTERRUPT_CLEAR_02_0_DUAL                       0x0
#define GPIO_BB_INTERRUPT_CLEAR_02_0_SCR                        GPIO_BB_SCR_02_0
#define GPIO_BB_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_BB_SCR_02_0
#define GPIO_BB_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
#define GPIO_BB_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1a58

// Reserved address 0x1a5c

// Register GPIO_BB_ENABLE_CONFIG_03_0
#define GPIO_BB_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x1a60)
#define GPIO_BB_ENABLE_CONFIG_03_0_SECURE                       0x0
#define GPIO_BB_ENABLE_CONFIG_03_0_DUAL                         0x0
#define GPIO_BB_ENABLE_CONFIG_03_0_SCR                  GPIO_BB_SCR_03_0
#define GPIO_BB_ENABLE_CONFIG_03_0_SCRREG                       GPIO_BB_SCR_03_0
#define GPIO_BB_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
#define GPIO_BB_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_BB_DEBOUNCE_THRESHOLD_03_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x1a64)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_BB_SCR_03_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_BB_SCR_03_0
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_BB_INPUT_03_0
#define GPIO_BB_INPUT_03_0                      MK_ADDR_CONST(0x1a68)
#define GPIO_BB_INPUT_03_0_SECURE                       0x0
#define GPIO_BB_INPUT_03_0_DUAL                         0x0
#define GPIO_BB_INPUT_03_0_SCR                  GPIO_BB_SCR_03_0
#define GPIO_BB_INPUT_03_0_SCRREG                       GPIO_BB_SCR_03_0
#define GPIO_BB_INPUT_03_0_WORD_COUNT                   0x1
#define GPIO_BB_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_BB_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_BB_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_BB_INPUT_03_0_GPIO_IN_RANGE                        0:0
#define GPIO_BB_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_BB_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_BB_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_BB_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_BB_OUTPUT_CONTROL_03_0
#define GPIO_BB_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x1a6c)
#define GPIO_BB_OUTPUT_CONTROL_03_0_SECURE                      0x0
#define GPIO_BB_OUTPUT_CONTROL_03_0_DUAL                        0x0
#define GPIO_BB_OUTPUT_CONTROL_03_0_SCR                         GPIO_BB_SCR_03_0
#define GPIO_BB_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_BB_SCR_03_0
#define GPIO_BB_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
#define GPIO_BB_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_BB_OUTPUT_VALUE_03_0
#define GPIO_BB_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x1a70)
#define GPIO_BB_OUTPUT_VALUE_03_0_SECURE                        0x0
#define GPIO_BB_OUTPUT_VALUE_03_0_DUAL                  0x0
#define GPIO_BB_OUTPUT_VALUE_03_0_SCR                   GPIO_BB_SCR_03_0
#define GPIO_BB_OUTPUT_VALUE_03_0_SCRREG                        GPIO_BB_SCR_03_0
#define GPIO_BB_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
#define GPIO_BB_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_BB_INTERRUPT_CLEAR_03_0
#define GPIO_BB_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x1a74)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_SECURE                     0x0
#define GPIO_BB_INTERRUPT_CLEAR_03_0_DUAL                       0x0
#define GPIO_BB_INTERRUPT_CLEAR_03_0_SCR                        GPIO_BB_SCR_03_0
#define GPIO_BB_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_BB_SCR_03_0
#define GPIO_BB_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
#define GPIO_BB_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x1a78

// Reserved address 0x1a7c

// Reserved address 0x1a80

// Reserved address 0x1a84

// Reserved address 0x1a88

// Reserved address 0x1a8c

// Reserved address 0x1a90

// Reserved address 0x1a94

// Reserved address 0x1a98

// Reserved address 0x1a9c

// Reserved address 0x1aa0

// Reserved address 0x1aa4

// Reserved address 0x1aa8

// Reserved address 0x1aac

// Reserved address 0x1ab0

// Reserved address 0x1ab4

// Reserved address 0x1ab8

// Reserved address 0x1abc

// Reserved address 0x1ac0

// Reserved address 0x1ac4

// Reserved address 0x1ac8

// Reserved address 0x1acc

// Reserved address 0x1ad0

// Reserved address 0x1ad4

// Reserved address 0x1ad8

// Reserved address 0x1adc

// Reserved address 0x1ae0

// Reserved address 0x1ae4

// Reserved address 0x1ae8

// Reserved address 0x1aec

// Reserved address 0x1af0

// Reserved address 0x1af4

// Reserved address 0x1af8

// Reserved address 0x1afc

// Register GPIO_BB_INTERRUPT_STATUS_G0_0
#define GPIO_BB_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x1b00)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G0_0_DUAL                      0x0
#define GPIO_BB_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G0_0_SCRREG                    0
#define GPIO_BB_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_BB_INTERRUPT_STATUS_G1_0
#define GPIO_BB_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x1b04)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G1_0_DUAL                      0x0
#define GPIO_BB_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G1_0_SCRREG                    0
#define GPIO_BB_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_BB_INTERRUPT_STATUS_G2_0
#define GPIO_BB_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x1b08)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G2_0_DUAL                      0x0
#define GPIO_BB_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G2_0_SCRREG                    0
#define GPIO_BB_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_BB_INTERRUPT_STATUS_G3_0
#define GPIO_BB_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x1b0c)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G3_0_DUAL                      0x0
#define GPIO_BB_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G3_0_SCRREG                    0
#define GPIO_BB_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_BB_INTERRUPT_STATUS_G4_0
#define GPIO_BB_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x1b10)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G4_0_DUAL                      0x0
#define GPIO_BB_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G4_0_SCRREG                    0
#define GPIO_BB_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_BB_INTERRUPT_STATUS_G5_0
#define GPIO_BB_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x1b14)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G5_0_DUAL                      0x0
#define GPIO_BB_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G5_0_SCRREG                    0
#define GPIO_BB_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_BB_INTERRUPT_STATUS_G6_0
#define GPIO_BB_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x1b18)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G6_0_DUAL                      0x0
#define GPIO_BB_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G6_0_SCRREG                    0
#define GPIO_BB_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_BB_INTERRUPT_STATUS_G7_0
#define GPIO_BB_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x1b1c)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_BB_INTERRUPT_STATUS_G7_0_DUAL                      0x0
#define GPIO_BB_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_BB_INTERRUPT_STATUS_G7_0_SCRREG                    0
#define GPIO_BB_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_BB_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x1b20

// Reserved address 0x1b24

// Reserved address 0x1b28

// Reserved address 0x1b2c

// Reserved address 0x1b30

// Reserved address 0x1b34

// Reserved address 0x1b38

// Reserved address 0x1b3c

// Reserved address 0x1b40

// Reserved address 0x1b44

// Reserved address 0x1b48

// Reserved address 0x1b4c

// Reserved address 0x1b50

// Reserved address 0x1b54

// Reserved address 0x1b58

// Reserved address 0x1b5c

// Reserved address 0x1b60

// Reserved address 0x1b64

// Reserved address 0x1b68

// Reserved address 0x1b6c

// Reserved address 0x1b70

// Reserved address 0x1b74

// Reserved address 0x1b78

// Reserved address 0x1b7c

// Reserved address 0x1b80

// Reserved address 0x1b84

// Reserved address 0x1b88

// Reserved address 0x1b8c

// Reserved address 0x1b90

// Reserved address 0x1b94

// Reserved address 0x1b98

// Reserved address 0x1b9c

// Reserved address 0x1ba0

// Reserved address 0x1ba4

// Reserved address 0x1ba8

// Reserved address 0x1bac

// Reserved address 0x1bb0

// Reserved address 0x1bb4

// Reserved address 0x1bb8

// Reserved address 0x1bbc

// Reserved address 0x1bc0

// Reserved address 0x1bc4

// Reserved address 0x1bc8

// Reserved address 0x1bcc

// Reserved address 0x1bd0

// Reserved address 0x1bd4

// Reserved address 0x1bd8

// Reserved address 0x1bdc

// Reserved address 0x1be0

// Reserved address 0x1be4

// Reserved address 0x1be8

// Reserved address 0x1bec

// Reserved address 0x1bf0

// Reserved address 0x1bf4

// Reserved address 0x1bf8

// Reserved address 0x1bfc

//
// REGISTER LIST
//
#define LIST_ARGPIO_AON_REGS(_op_) \
_op_(GPIO_EE_ENABLE_CONFIG_00_0) \
_op_(GPIO_EE_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_EE_INPUT_00_0) \
_op_(GPIO_EE_OUTPUT_CONTROL_00_0) \
_op_(GPIO_EE_OUTPUT_VALUE_00_0) \
_op_(GPIO_EE_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_EE_ENABLE_CONFIG_01_0) \
_op_(GPIO_EE_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_EE_INPUT_01_0) \
_op_(GPIO_EE_OUTPUT_CONTROL_01_0) \
_op_(GPIO_EE_OUTPUT_VALUE_01_0) \
_op_(GPIO_EE_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_EE_ENABLE_CONFIG_02_0) \
_op_(GPIO_EE_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_EE_INPUT_02_0) \
_op_(GPIO_EE_OUTPUT_CONTROL_02_0) \
_op_(GPIO_EE_OUTPUT_VALUE_02_0) \
_op_(GPIO_EE_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_EE_ENABLE_CONFIG_03_0) \
_op_(GPIO_EE_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_EE_INPUT_03_0) \
_op_(GPIO_EE_OUTPUT_CONTROL_03_0) \
_op_(GPIO_EE_OUTPUT_VALUE_03_0) \
_op_(GPIO_EE_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_EE_ENABLE_CONFIG_04_0) \
_op_(GPIO_EE_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_EE_INPUT_04_0) \
_op_(GPIO_EE_OUTPUT_CONTROL_04_0) \
_op_(GPIO_EE_OUTPUT_VALUE_04_0) \
_op_(GPIO_EE_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_EE_ENABLE_CONFIG_05_0) \
_op_(GPIO_EE_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_EE_INPUT_05_0) \
_op_(GPIO_EE_OUTPUT_CONTROL_05_0) \
_op_(GPIO_EE_OUTPUT_VALUE_05_0) \
_op_(GPIO_EE_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_EE_ENABLE_CONFIG_06_0) \
_op_(GPIO_EE_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_EE_INPUT_06_0) \
_op_(GPIO_EE_OUTPUT_CONTROL_06_0) \
_op_(GPIO_EE_OUTPUT_VALUE_06_0) \
_op_(GPIO_EE_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_EE_ENABLE_CONFIG_07_0) \
_op_(GPIO_EE_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_EE_INPUT_07_0) \
_op_(GPIO_EE_OUTPUT_CONTROL_07_0) \
_op_(GPIO_EE_OUTPUT_VALUE_07_0) \
_op_(GPIO_EE_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_EE_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_EE_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_EE_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_EE_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_EE_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_EE_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_EE_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_EE_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_GG_ENABLE_CONFIG_00_0) \
_op_(GPIO_GG_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_GG_INPUT_00_0) \
_op_(GPIO_GG_OUTPUT_CONTROL_00_0) \
_op_(GPIO_GG_OUTPUT_VALUE_00_0) \
_op_(GPIO_GG_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_CC_ENABLE_CONFIG_00_0) \
_op_(GPIO_CC_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_CC_INPUT_00_0) \
_op_(GPIO_CC_OUTPUT_CONTROL_00_0) \
_op_(GPIO_CC_OUTPUT_VALUE_00_0) \
_op_(GPIO_CC_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_CC_ENABLE_CONFIG_01_0) \
_op_(GPIO_CC_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_CC_INPUT_01_0) \
_op_(GPIO_CC_OUTPUT_CONTROL_01_0) \
_op_(GPIO_CC_OUTPUT_VALUE_01_0) \
_op_(GPIO_CC_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_CC_ENABLE_CONFIG_02_0) \
_op_(GPIO_CC_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_CC_INPUT_02_0) \
_op_(GPIO_CC_OUTPUT_CONTROL_02_0) \
_op_(GPIO_CC_OUTPUT_VALUE_02_0) \
_op_(GPIO_CC_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_CC_ENABLE_CONFIG_03_0) \
_op_(GPIO_CC_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_CC_INPUT_03_0) \
_op_(GPIO_CC_OUTPUT_CONTROL_03_0) \
_op_(GPIO_CC_OUTPUT_VALUE_03_0) \
_op_(GPIO_CC_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_CC_ENABLE_CONFIG_04_0) \
_op_(GPIO_CC_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_CC_INPUT_04_0) \
_op_(GPIO_CC_OUTPUT_CONTROL_04_0) \
_op_(GPIO_CC_OUTPUT_VALUE_04_0) \
_op_(GPIO_CC_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_CC_ENABLE_CONFIG_05_0) \
_op_(GPIO_CC_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_CC_INPUT_05_0) \
_op_(GPIO_CC_OUTPUT_CONTROL_05_0) \
_op_(GPIO_CC_OUTPUT_VALUE_05_0) \
_op_(GPIO_CC_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_CC_ENABLE_CONFIG_06_0) \
_op_(GPIO_CC_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_CC_INPUT_06_0) \
_op_(GPIO_CC_OUTPUT_CONTROL_06_0) \
_op_(GPIO_CC_OUTPUT_VALUE_06_0) \
_op_(GPIO_CC_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_CC_ENABLE_CONFIG_07_0) \
_op_(GPIO_CC_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_CC_INPUT_07_0) \
_op_(GPIO_CC_OUTPUT_CONTROL_07_0) \
_op_(GPIO_CC_OUTPUT_VALUE_07_0) \
_op_(GPIO_CC_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_CC_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_DD_ENABLE_CONFIG_00_0) \
_op_(GPIO_DD_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_DD_INPUT_00_0) \
_op_(GPIO_DD_OUTPUT_CONTROL_00_0) \
_op_(GPIO_DD_OUTPUT_VALUE_00_0) \
_op_(GPIO_DD_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_DD_ENABLE_CONFIG_01_0) \
_op_(GPIO_DD_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_DD_INPUT_01_0) \
_op_(GPIO_DD_OUTPUT_CONTROL_01_0) \
_op_(GPIO_DD_OUTPUT_VALUE_01_0) \
_op_(GPIO_DD_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_DD_ENABLE_CONFIG_02_0) \
_op_(GPIO_DD_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_DD_INPUT_02_0) \
_op_(GPIO_DD_OUTPUT_CONTROL_02_0) \
_op_(GPIO_DD_OUTPUT_VALUE_02_0) \
_op_(GPIO_DD_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_DD_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_DD_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_DD_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_DD_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_DD_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_DD_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_DD_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_DD_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_AA_ENABLE_CONFIG_00_0) \
_op_(GPIO_AA_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_AA_INPUT_00_0) \
_op_(GPIO_AA_OUTPUT_CONTROL_00_0) \
_op_(GPIO_AA_OUTPUT_VALUE_00_0) \
_op_(GPIO_AA_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_AA_ENABLE_CONFIG_01_0) \
_op_(GPIO_AA_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_AA_INPUT_01_0) \
_op_(GPIO_AA_OUTPUT_CONTROL_01_0) \
_op_(GPIO_AA_OUTPUT_VALUE_01_0) \
_op_(GPIO_AA_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_AA_ENABLE_CONFIG_02_0) \
_op_(GPIO_AA_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_AA_INPUT_02_0) \
_op_(GPIO_AA_OUTPUT_CONTROL_02_0) \
_op_(GPIO_AA_OUTPUT_VALUE_02_0) \
_op_(GPIO_AA_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_AA_ENABLE_CONFIG_03_0) \
_op_(GPIO_AA_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_AA_INPUT_03_0) \
_op_(GPIO_AA_OUTPUT_CONTROL_03_0) \
_op_(GPIO_AA_OUTPUT_VALUE_03_0) \
_op_(GPIO_AA_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_AA_ENABLE_CONFIG_04_0) \
_op_(GPIO_AA_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_AA_INPUT_04_0) \
_op_(GPIO_AA_OUTPUT_CONTROL_04_0) \
_op_(GPIO_AA_OUTPUT_VALUE_04_0) \
_op_(GPIO_AA_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_AA_ENABLE_CONFIG_05_0) \
_op_(GPIO_AA_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_AA_INPUT_05_0) \
_op_(GPIO_AA_OUTPUT_CONTROL_05_0) \
_op_(GPIO_AA_OUTPUT_VALUE_05_0) \
_op_(GPIO_AA_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_AA_ENABLE_CONFIG_06_0) \
_op_(GPIO_AA_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_AA_INPUT_06_0) \
_op_(GPIO_AA_OUTPUT_CONTROL_06_0) \
_op_(GPIO_AA_OUTPUT_VALUE_06_0) \
_op_(GPIO_AA_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_AA_ENABLE_CONFIG_07_0) \
_op_(GPIO_AA_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_AA_INPUT_07_0) \
_op_(GPIO_AA_OUTPUT_CONTROL_07_0) \
_op_(GPIO_AA_OUTPUT_VALUE_07_0) \
_op_(GPIO_AA_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_AA_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_AA_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_AA_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_AA_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_AA_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_AA_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_AA_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_AA_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_BB_ENABLE_CONFIG_00_0) \
_op_(GPIO_BB_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_BB_INPUT_00_0) \
_op_(GPIO_BB_OUTPUT_CONTROL_00_0) \
_op_(GPIO_BB_OUTPUT_VALUE_00_0) \
_op_(GPIO_BB_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_BB_ENABLE_CONFIG_01_0) \
_op_(GPIO_BB_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_BB_INPUT_01_0) \
_op_(GPIO_BB_OUTPUT_CONTROL_01_0) \
_op_(GPIO_BB_OUTPUT_VALUE_01_0) \
_op_(GPIO_BB_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_BB_ENABLE_CONFIG_02_0) \
_op_(GPIO_BB_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_BB_INPUT_02_0) \
_op_(GPIO_BB_OUTPUT_CONTROL_02_0) \
_op_(GPIO_BB_OUTPUT_VALUE_02_0) \
_op_(GPIO_BB_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_BB_ENABLE_CONFIG_03_0) \
_op_(GPIO_BB_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_BB_INPUT_03_0) \
_op_(GPIO_BB_OUTPUT_CONTROL_03_0) \
_op_(GPIO_BB_OUTPUT_VALUE_03_0) \
_op_(GPIO_BB_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_BB_INTERRUPT_STATUS_G7_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_GPIO       0x00001000

//
// ARGPIO_AON REGISTER BANKS
//

#define GPIO0_FIRST_REG 0x1000 // GPIO_EE_ENABLE_CONFIG_00_0
#define GPIO0_LAST_REG 0x1014 // GPIO_EE_INTERRUPT_CLEAR_00_0
#define GPIO1_FIRST_REG 0x1020 // GPIO_EE_ENABLE_CONFIG_01_0
#define GPIO1_LAST_REG 0x1034 // GPIO_EE_INTERRUPT_CLEAR_01_0
#define GPIO2_FIRST_REG 0x1040 // GPIO_EE_ENABLE_CONFIG_02_0
#define GPIO2_LAST_REG 0x1054 // GPIO_EE_INTERRUPT_CLEAR_02_0
#define GPIO3_FIRST_REG 0x1060 // GPIO_EE_ENABLE_CONFIG_03_0
#define GPIO3_LAST_REG 0x1074 // GPIO_EE_INTERRUPT_CLEAR_03_0
#define GPIO4_FIRST_REG 0x1080 // GPIO_EE_ENABLE_CONFIG_04_0
#define GPIO4_LAST_REG 0x1094 // GPIO_EE_INTERRUPT_CLEAR_04_0
#define GPIO5_FIRST_REG 0x10a0 // GPIO_EE_ENABLE_CONFIG_05_0
#define GPIO5_LAST_REG 0x10b4 // GPIO_EE_INTERRUPT_CLEAR_05_0
#define GPIO6_FIRST_REG 0x10c0 // GPIO_EE_ENABLE_CONFIG_06_0
#define GPIO6_LAST_REG 0x10d4 // GPIO_EE_INTERRUPT_CLEAR_06_0
#define GPIO7_FIRST_REG 0x10e0 // GPIO_EE_ENABLE_CONFIG_07_0
#define GPIO7_LAST_REG 0x10f4 // GPIO_EE_INTERRUPT_CLEAR_07_0
#define GPIO8_FIRST_REG 0x1100 // GPIO_EE_INTERRUPT_STATUS_G0_0
#define GPIO8_LAST_REG 0x111c // GPIO_EE_INTERRUPT_STATUS_G7_0
#define GPIO9_FIRST_REG 0x1200 // GPIO_GG_ENABLE_CONFIG_00_0
#define GPIO9_LAST_REG 0x1214 // GPIO_GG_INTERRUPT_CLEAR_00_0
#define GPIO10_FIRST_REG 0x1300 // GPIO_GG_INTERRUPT_STATUS_G0_0
#define GPIO10_LAST_REG 0x131c // GPIO_GG_INTERRUPT_STATUS_G7_0
#define GPIO11_FIRST_REG 0x1400 // GPIO_CC_ENABLE_CONFIG_00_0
#define GPIO11_LAST_REG 0x1414 // GPIO_CC_INTERRUPT_CLEAR_00_0
#define GPIO12_FIRST_REG 0x1420 // GPIO_CC_ENABLE_CONFIG_01_0
#define GPIO12_LAST_REG 0x1434 // GPIO_CC_INTERRUPT_CLEAR_01_0
#define GPIO13_FIRST_REG 0x1440 // GPIO_CC_ENABLE_CONFIG_02_0
#define GPIO13_LAST_REG 0x1454 // GPIO_CC_INTERRUPT_CLEAR_02_0
#define GPIO14_FIRST_REG 0x1460 // GPIO_CC_ENABLE_CONFIG_03_0
#define GPIO14_LAST_REG 0x1474 // GPIO_CC_INTERRUPT_CLEAR_03_0
#define GPIO15_FIRST_REG 0x1480 // GPIO_CC_ENABLE_CONFIG_04_0
#define GPIO15_LAST_REG 0x1494 // GPIO_CC_INTERRUPT_CLEAR_04_0
#define GPIO16_FIRST_REG 0x14a0 // GPIO_CC_ENABLE_CONFIG_05_0
#define GPIO16_LAST_REG 0x14b4 // GPIO_CC_INTERRUPT_CLEAR_05_0
#define GPIO17_FIRST_REG 0x14c0 // GPIO_CC_ENABLE_CONFIG_06_0
#define GPIO17_LAST_REG 0x14d4 // GPIO_CC_INTERRUPT_CLEAR_06_0
#define GPIO18_FIRST_REG 0x14e0 // GPIO_CC_ENABLE_CONFIG_07_0
#define GPIO18_LAST_REG 0x14f4 // GPIO_CC_INTERRUPT_CLEAR_07_0
#define GPIO19_FIRST_REG 0x1500 // GPIO_CC_INTERRUPT_STATUS_G0_0
#define GPIO19_LAST_REG 0x151c // GPIO_CC_INTERRUPT_STATUS_G7_0
#define GPIO20_FIRST_REG 0x1600 // GPIO_DD_ENABLE_CONFIG_00_0
#define GPIO20_LAST_REG 0x1614 // GPIO_DD_INTERRUPT_CLEAR_00_0
#define GPIO21_FIRST_REG 0x1620 // GPIO_DD_ENABLE_CONFIG_01_0
#define GPIO21_LAST_REG 0x1634 // GPIO_DD_INTERRUPT_CLEAR_01_0
#define GPIO22_FIRST_REG 0x1640 // GPIO_DD_ENABLE_CONFIG_02_0
#define GPIO22_LAST_REG 0x1654 // GPIO_DD_INTERRUPT_CLEAR_02_0
#define GPIO23_FIRST_REG 0x1700 // GPIO_DD_INTERRUPT_STATUS_G0_0
#define GPIO23_LAST_REG 0x171c // GPIO_DD_INTERRUPT_STATUS_G7_0
#define GPIO24_FIRST_REG 0x1800 // GPIO_AA_ENABLE_CONFIG_00_0
#define GPIO24_LAST_REG 0x1814 // GPIO_AA_INTERRUPT_CLEAR_00_0
#define GPIO25_FIRST_REG 0x1820 // GPIO_AA_ENABLE_CONFIG_01_0
#define GPIO25_LAST_REG 0x1834 // GPIO_AA_INTERRUPT_CLEAR_01_0
#define GPIO26_FIRST_REG 0x1840 // GPIO_AA_ENABLE_CONFIG_02_0
#define GPIO26_LAST_REG 0x1854 // GPIO_AA_INTERRUPT_CLEAR_02_0
#define GPIO27_FIRST_REG 0x1860 // GPIO_AA_ENABLE_CONFIG_03_0
#define GPIO27_LAST_REG 0x1874 // GPIO_AA_INTERRUPT_CLEAR_03_0
#define GPIO28_FIRST_REG 0x1880 // GPIO_AA_ENABLE_CONFIG_04_0
#define GPIO28_LAST_REG 0x1894 // GPIO_AA_INTERRUPT_CLEAR_04_0
#define GPIO29_FIRST_REG 0x18a0 // GPIO_AA_ENABLE_CONFIG_05_0
#define GPIO29_LAST_REG 0x18b4 // GPIO_AA_INTERRUPT_CLEAR_05_0
#define GPIO30_FIRST_REG 0x18c0 // GPIO_AA_ENABLE_CONFIG_06_0
#define GPIO30_LAST_REG 0x18d4 // GPIO_AA_INTERRUPT_CLEAR_06_0
#define GPIO31_FIRST_REG 0x18e0 // GPIO_AA_ENABLE_CONFIG_07_0
#define GPIO31_LAST_REG 0x18f4 // GPIO_AA_INTERRUPT_CLEAR_07_0
#define GPIO32_FIRST_REG 0x1900 // GPIO_AA_INTERRUPT_STATUS_G0_0
#define GPIO32_LAST_REG 0x191c // GPIO_AA_INTERRUPT_STATUS_G7_0
#define GPIO33_FIRST_REG 0x1a00 // GPIO_BB_ENABLE_CONFIG_00_0
#define GPIO33_LAST_REG 0x1a14 // GPIO_BB_INTERRUPT_CLEAR_00_0
#define GPIO34_FIRST_REG 0x1a20 // GPIO_BB_ENABLE_CONFIG_01_0
#define GPIO34_LAST_REG 0x1a34 // GPIO_BB_INTERRUPT_CLEAR_01_0
#define GPIO35_FIRST_REG 0x1a40 // GPIO_BB_ENABLE_CONFIG_02_0
#define GPIO35_LAST_REG 0x1a54 // GPIO_BB_INTERRUPT_CLEAR_02_0
#define GPIO36_FIRST_REG 0x1a60 // GPIO_BB_ENABLE_CONFIG_03_0
#define GPIO36_LAST_REG 0x1a74 // GPIO_BB_INTERRUPT_CLEAR_03_0
#define GPIO37_FIRST_REG 0x1b00 // GPIO_BB_INTERRUPT_STATUS_G0_0
#define GPIO37_LAST_REG 0x1b1c // GPIO_BB_INTERRUPT_STATUS_G7_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARGPIO_AON_H_INC
