/*
 * SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */

#ifndef PROCESSOR__TKE_TEGRA_HW_H
#define PROCESSOR__TKE_TEGRA_HW_H
#define FSP__PROCESSOR__TKE_TEGRA_HW_H                  1

extern struct tegra_tke_id tegra_tke_id_timer0;
extern struct tegra_tke_id tegra_tke_id_timer1;
extern struct tegra_tke_id tegra_tke_id_timer2;
extern struct tegra_tke_id tegra_tke_id_timer3;

#define TEGRA_TKE_TIMER_CLK_SRC_USECCNT         0
#define TEGRA_TKE_TIMER_CLK_SRC_OSCCNT          1
#define TEGRA_TKE_TIMER_CLK_SRC_TSC_BIT0        2
#define TEGRA_TKE_TIMER_CLK_SRC_TSC_BIT12       3

#endif  /* FSP_SOC_T234_DCE_PROCESSOR_TKE_TEGRA_HW_H */
