/*
* Copyright (c) 2023 NVIDIA CORPORATION.  All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto.  Any use, reproduction, disclosure or
* distribution of this software and related documentation without an express
* license agreement from NVIDIA CORPORATION is strictly prohibited.
*/

/**
 * @file irqs-hw.h
 * @brief BPMP IRQ Configuration Header for T26x
 */

#ifndef PROCESSOR__IRQS_HW_H
#define PROCESSOR__IRQS_HW_H
#define FSP__PROCESSOR__IRQS_HW_H                       1

#include <arproc_interrupts.h>

#define MAX_VIC_CONTROLLER       4

/* VIC0 interrupts */
#define NV_BPMP_INTERRUPT_HSP0_SI_0			    (NV_PROC_COMMON_VIC0_HSP0_SI_0)
#define NV_BPMP_INTERRUPT_HSP0_SI_1			    (NV_PROC_COMMON_VIC0_HSP0_SI_1)
#define NV_BPMP_INTERRUPT_HSP0_SI_2			    (NV_PROC_COMMON_VIC0_HSP0_SI_2)
#define NV_BPMP_INTERRUPT_HSP0_SI_3			    (NV_PROC_COMMON_VIC0_HSP0_SI_3)
#define NV_BPMP_INTERRUPT_HSP0_SI_4			    (NV_PROC_COMMON_VIC0_HSP0_SI_4)
#define NV_BPMP_INTERRUPT_HSP0_SI_5			    (NV_PROC_COMMON_VIC0_HSP0_SI_5)
#define NV_BPMP_INTERRUPT_HSP0_SI_6			    (NV_PROC_COMMON_VIC0_HSP0_SI_6)
#define NV_BPMP_INTERRUPT_HSP0_SI_7			    (NV_PROC_COMMON_VIC0_HSP0_SI_7)
#define NV_BPMP_INTERRUPT_HSP0_SI_8			    (NV_PROC_COMMON_VIC0_HSP0_SI_8)
#define NV_BPMP_INTERRUPT_HSP0_SI_9			    (NV_PROC_COMMON_VIC0_HSP0_SI_9)
#define NV_BPMP_INTERRUPT_HSP0_SI_10		    (NV_PROC_COMMON_VIC0_HSP0_SI_10)
#define NV_BPMP_INTERRUPT_HSP0_SI_11		    (NV_PROC_COMMON_VIC0_HSP0_SI_11)
#define NV_BPMP_INTERRUPT_HSP0_SI_12		    (NV_PROC_COMMON_VIC0_HSP0_SI_12)
#define NV_BPMP_INTERRUPT_HSP0_SI_13		    (NV_PROC_COMMON_VIC0_HSP0_SI_13)
#define NV_BPMP_INTERRUPT_HSP0_SI_14		    (NV_PROC_COMMON_VIC0_HSP0_SI_14)
#define NV_BPMP_INTERRUPT_HSP0_SI_15		    (NV_PROC_COMMON_VIC0_HSP0_SI_15)
#define NV_BPMP_INTERRUPT_HSP1_SI_0			    (NV_PROC_COMMON_VIC0_HSP1_SI_0)
#define NV_BPMP_INTERRUPT_HSP1_SI_1			    (NV_PROC_COMMON_VIC0_HSP1_SI_1)
#define NV_BPMP_INTERRUPT_HSP1_SI_2			    (NV_PROC_COMMON_VIC0_HSP1_SI_2)
#define NV_BPMP_INTERRUPT_HSP1_SI_3			    (NV_PROC_COMMON_VIC0_HSP1_SI_3)
#define NV_BPMP_INTERRUPT_HSP1_SI_4			    (NV_PROC_COMMON_VIC0_HSP1_SI_4)
#define NV_BPMP_INTERRUPT_HSP1_SI_5			    (NV_PROC_COMMON_VIC0_HSP1_SI_5)
#define NV_BPMP_INTERRUPT_HSP1_SI_6			    (NV_PROC_COMMON_VIC0_HSP1_SI_6)
#define NV_BPMP_INTERRUPT_HSP1_SI_7			    (NV_PROC_COMMON_VIC0_HSP1_SI_7)
#define NV_BPMP_INTERRUPT_HSP1_SI_8			    (NV_PROC_COMMON_VIC0_HSP1_SI_8)
#define NV_BPMP_INTERRUPT_HSP1_SI_9			    (NV_PROC_COMMON_VIC0_HSP1_SI_9)
#define NV_BPMP_INTERRUPT_HSP1_SI_10		    (NV_PROC_COMMON_VIC0_HSP1_SI_10)
#define NV_BPMP_INTERRUPT_HSP1_SI_11		    (NV_PROC_COMMON_VIC0_HSP1_SI_11)
#define NV_BPMP_INTERRUPT_HSP1_SI_12		    (NV_PROC_COMMON_VIC0_HSP1_SI_12)
#define NV_BPMP_INTERRUPT_HSP1_SI_13		    (NV_PROC_COMMON_VIC0_HSP1_SI_13)
#define NV_BPMP_INTERRUPT_HSP1_SI_14		    (NV_PROC_COMMON_VIC0_HSP1_SI_14)
#define NV_BPMP_INTERRUPT_HSP1_SI_15		    (NV_PROC_COMMON_VIC0_HSP1_SI_15)

/* VIC1 interrupts */
#define NV_BPMP_INTERRUPT_TKE_WDTIRQ		    (NV_PROC_COMMON_VIC1_TKE_WDTIRQ)
#define NV_BPMP_INTERRUPT_TKE_WDTFIQ		    (NV_PROC_COMMON_VIC1_TKE_WDTFIQ)
#define NV_BPMP_INTERRUPT_TKE_TIMER_INTR0		(NV_PROC_COMMON_VIC1_TKE_TIMER_INTR0)
#define NV_BPMP_INTERRUPT_TKE_TIMER_INTR1		(NV_PROC_COMMON_VIC1_TKE_TIMER_INTR1)
#define NV_BPMP_INTERRUPT_TKE_TIMER_INTR2		(NV_PROC_COMMON_VIC1_TKE_TIMER_INTR2)
#define NV_BPMP_INTERRUPT_TKE_TIMER_INTR3		(NV_PROC_COMMON_VIC1_TKE_TIMER_INTR3)
#define NV_BPMP_INTERRUPT_DMA_INTR0			    (NV_PROC_COMMON_VIC1_DMA_INTR0)
#define NV_BPMP_INTERRUPT_DMA_INTR1			    (NV_PROC_COMMON_VIC1_DMA_INTR1)
#define NV_BPMP_INTERRUPT_DMA_INTR2			    (NV_PROC_COMMON_VIC1_DMA_INTR2)
#define NV_BPMP_INTERRUPT_DMA_INTR3			    (NV_PROC_COMMON_VIC1_DMA_INTR3)
#define NV_BPMP_INTERRUPT_DMA_INTR4			    (NV_PROC_COMMON_VIC1_DMA_INTR4)
#define NV_BPMP_INTERRUPT_DMA_INTR5			    (NV_PROC_COMMON_VIC1_DMA_INTR5)
#define NV_BPMP_INTERRUPT_DMA_INTR6			    (NV_PROC_COMMON_VIC1_DMA_INTR6)
#define NV_BPMP_INTERRUPT_DMA_INTR7			    (NV_PROC_COMMON_VIC1_DMA_INTR7)
#define NV_BPMP_INTERRUPT_CPU_PMUIRQ		    (NV_PROC_COMMON_VIC1_CPU_PMUIRQ)
#define NV_BPMP_INTERRUPT_CPU_FPUINT		    (NV_PROC_COMMON_VIC1_CPU_FPUINT)
#define NV_BPMP_INTERRUPT_CPU_CTIIRQ		    (NV_PROC_COMMON_VIC1_CPU_CTIIRQ)
#define NV_BPMP_INTERRUPT_NIC_SECURE_INTR		(NV_PROC_COMMON_VIC1_NIC_SECURE_INTR)
#define NV_BPMP_INTERRUPT_CENTRAL_ACTMON_INTR	(NV_PROC_COMMON_VIC1_CENTRAL_ACTMON_INTR)
#define NV_BPMP_INTERRUPT_GTE_INTR			    (NV_PROC_COMMON_VIC1_GTE_INTR)
#define NV_BPMP_INTERRUPT_MISC_IRQ0_INTR		(NV_PROC_COMMON_VIC1_MISC_IRQ0_INTR)
#define NV_BPMP_INTERRUPT_MISC_IRQ1_INTR		(NV_PROC_COMMON_VIC1_MISC_IRQ1_INTR)
#define NV_BPMP_INTERRUPT_RSVD22			    (NV_PROC_COMMON_VIC1_RSVD22)
#define NV_BPMP_INTERRUPT_RSVD23			    (NV_PROC_COMMON_VIC1_RSVD23)
#define NV_BPMP_INTERRUPT_RSVD24			    (NV_PROC_COMMON_VIC1_RSVD24)
#define NV_BPMP_INTERRUPT_RSVD25			    (NV_PROC_COMMON_VIC1_RSVD25)
#define NV_BPMP_INTERRUPT_RSVD26			    (NV_PROC_COMMON_VIC1_RSVD26)
#define NV_BPMP_INTERRUPT_RSVD27			    (NV_PROC_COMMON_VIC1_RSVD27)
#define NV_BPMP_INTERRUPT_RSVD28			    (NV_PROC_COMMON_VIC1_RSVD28)
#define NV_BPMP_INTERRUPT_RSVD29			    (NV_PROC_COMMON_VIC1_RSVD29)
#define NV_BPMP_INTERRUPT_RSVD30			    (NV_PROC_COMMON_VIC1_RSVD30)
#define NV_BPMP_INTERRUPT_RSVD31			    (NV_PROC_COMMON_VIC1_RSVD31)

/* VIC2 interrupts */
#define NV_BPMP_INTERRUPT_TOP0_HSP_DB_INTR		(NV_PROC_BPMP_VIC2_TOP0_HSP_DB_INTR)
#define NV_BPMP_INTERRUPT_WAKE_TIER0_INTR		(NV_PROC_BPMP_VIC2_WAKE_TIER0_INTR)
#define NV_BPMP_INTERRUPT_WAKE_TIER1_INTR		(NV_PROC_BPMP_VIC2_WAKE_TIER1_INTR)
#define NV_BPMP_INTERRUPT_WAKE_TIER2_INTR		(NV_PROC_BPMP_VIC2_WAKE_TIER2_INTR)
#define NV_BPMP_INTERRUPT_LIC_IRQ0			    (NV_PROC_BPMP_VIC2_LIC_IRQ0)
#define NV_BPMP_INTERRUPT_LIC_FIQ0			    (NV_PROC_BPMP_VIC2_LIC_FIQ0)
#define NV_BPMP_INTERRUPT_PSC_INTR			    (NV_PROC_BPMP_VIC2_PSC_INTR)
#define NV_BPMP_INTERRUPT_OESP_INTR			    (NV_PROC_BPMP_VIC2_OESP_INTR)
#define NV_BPMP_INTERRUPT_SB_INTR			    (NV_PROC_BPMP_VIC2_SB_INTR)
#define NV_BPMP_INTERRUPT_GPMU_INTR			    (NV_PROC_BPMP_VIC2_GPMU_INTR)
#define NV_BPMP_INTERRUPT_CPU_PCSM_ASSIST_INTR	(NV_PROC_BPMP_VIC2_CPU_PCSM_ASSIST_INTR)
#define NV_BPMP_INTERRUPT_CPU_RGC_ASSIST_INTR	(NV_PROC_BPMP_VIC2_CPU_RGC_ASSIST_INTR)
#define NV_BPMP_INTERRUPT_CPU_NDIV_INTR		    (NV_PROC_BPMP_VIC2_CPU_NDIV_INTR)
#define NV_BPMP_INTERRUPT_H1XSNC_INTR		    (NV_PROC_BPMP_VIC2_H1XSNC_INTR)
#define NV_BPMP_INTERRUPT_DFD_0_INTR		    (NV_PROC_BPMP_VIC2_DFD_0_INTR)
#define NV_BPMP_INTERRUPT_I2C5_INTR			    (NV_PROC_BPMP_VIC2_I2C5_INTR)
#define NV_BPMP_INTERRUPT_UART0_INTR		    (NV_PROC_BPMP_VIC2_UART0_INTR)
#define NV_BPMP_INTERRUPT_UART4_INTR		    (NV_PROC_BPMP_VIC2_UART4_INTR)
#define NV_BPMP_INTERRUPT_UART5_INTR		    (NV_PROC_BPMP_VIC2_UART5_INTR)
#define NV_BPMP_INTERRUPT_UART8_INTR		    (NV_PROC_BPMP_VIC2_UART8_INTR)
#define NV_BPMP_INTERRUPT_UART9_INTR		    (NV_PROC_BPMP_VIC2_UART9_INTR)
#define NV_BPMP_INTERRUPT_UART10_INTR		    (NV_PROC_BPMP_VIC2_UART10_INTR)
#define NV_BPMP_INTERRUPT_QSPI0_INTR		    (NV_PROC_BPMP_VIC2_QSPI0_INTR)
#define NV_BPMP_INTERRUPT_QSPI2_INTR		    (NV_PROC_BPMP_VIC2_QSPI2_INTR)
#define NV_BPMP_INTERRUPT_QSPI3_INTR		    (NV_PROC_BPMP_VIC2_QSPI3_INTR)
#define NV_BPMP_INTERRUPT_QSPI5_INTR		    (NV_PROC_BPMP_VIC2_QSPI5_INTR)
#define NV_BPMP_INTERRUPT_NVTHERM_INTR		    (NV_PROC_BPMP_VIC2_NVTHERM_INTR)
#define NV_BPMP_INTERRUPT_MSS_SEQ_INTR		    (NV_PROC_BPMP_VIC2_MSS_SEQ_INTR)
#define NV_BPMP_INTERRUPT_SDMMC1_INTR		    (NV_PROC_BPMP_VIC2_SDMMC1_INTR)
#define NV_BPMP_INTERRUPT_SDMMC1_SYS_INTR		(NV_PROC_BPMP_VIC2_SDMMC1_SYS_INTR)
#define NV_BPMP_INTERRUPT_BME_INTR			    (NV_PROC_BPMP_VIC2_BME_INTR)
#define NV_BPMP_INTERRUPT_UFS_INTR			    (NV_PROC_BPMP_VIC2_UFS_INTR)

/* VIC3 interrupts */
#define NV_BPMP_INTERRUPT_CAR_INTR			    (NV_PROC_BPMP_VIC3_CAR_INTR)
#define NV_BPMP_INTERRUPT_IH2BPMP_ERR_INTR		(NV_PROC_BPMP_VIC3_IH2BPMP_ERR_INTR)


#endif /* PROCESSOR__IRQS_HW_H */
