/*
 * Copyright (c) 2018-2023 NVIDIA CORPORATION.  All rights reserved.
 *
 * NVIDIA CORPORATION and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA CORPORATION is strictly prohibited.
 */

#ifndef HW_CONFIG__VIC_IRQS_H
#define HW_CONFIG__VIC_IRQS_H
#define FSP__HW_CONFIG__VIC_IRQS_H                      1

/* Compiler headers */

/* Early FSP headers */

/* Hardware headers */

/* Late FSP headers */
#include <processor/irqs-hw.h>

#define NUM_VICS                MAX_VIC_CONTROLLER

/*
 * VIC0 Interrupts
 */
#define INTERRUPT_HSP0_SI_0    NV_DCE_IRQ_HSP0_SI_0
#define INTERRUPT_HSP0_SI_1    NV_DCE_IRQ_HSP0_SI_1
#define INTERRUPT_HSP0_SI_2    NV_DCE_IRQ_HSP0_SI_2
#define INTERRUPT_HSP0_SI_3    NV_DCE_IRQ_HSP0_SI_3
#define INTERRUPT_HSP0_SI_4    NV_DCE_IRQ_HSP0_SI_4
#define INTERRUPT_HSP0_SI_5    NV_DCE_IRQ_HSP0_SI_5
#define INTERRUPT_HSP0_SI_6    NV_DCE_IRQ_HSP0_SI_6
#define INTERRUPT_HSP0_SI_7    NV_DCE_IRQ_HSP0_SI_7
#define INTERRUPT_HSP0_SI_8    NV_DCE_IRQ_HSP0_SI_8
#define INTERRUPT_HSP0_SI_9    NV_DCE_IRQ_HSP0_SI_9
#define INTERRUPT_HSP0_SI_10   NV_DCE_IRQ_HSP0_SI_10
#define INTERRUPT_HSP0_SI_11   NV_DCE_IRQ_HSP0_SI_11
#define INTERRUPT_HSP0_SI_12   NV_DCE_IRQ_HSP0_SI_12
#define INTERRUPT_HSP0_SI_13   NV_DCE_IRQ_HSP0_SI_13
#define INTERRUPT_HSP0_SI_14   NV_DCE_IRQ_HSP0_SI_14
#define INTERRUPT_HSP0_SI_15   NV_DCE_IRQ_HSP0_SI_15
#define INTERRUPT_HSP1_SI_0    NV_DCE_IRQ_HSP1_SI_0
#define INTERRUPT_HSP1_SI_1    NV_DCE_IRQ_HSP1_SI_1
#define INTERRUPT_HSP1_SI_2    NV_DCE_IRQ_HSP1_SI_2
#define INTERRUPT_HSP1_SI_3    NV_DCE_IRQ_HSP1_SI_3
#define INTERRUPT_HSP1_SI_4    NV_DCE_IRQ_HSP1_SI_4
#define INTERRUPT_HSP1_SI_5    NV_DCE_IRQ_HSP1_SI_5
#define INTERRUPT_HSP1_SI_6    NV_DCE_IRQ_HSP1_SI_6
#define INTERRUPT_HSP1_SI_7    NV_DCE_IRQ_HSP1_SI_7
#define INTERRUPT_HSP1_SI_8    NV_DCE_IRQ_HSP1_SI_8
#define INTERRUPT_HSP1_SI_9    NV_DCE_IRQ_HSP1_SI_9
#define INTERRUPT_HSP1_SI_10   NV_DCE_IRQ_HSP1_SI_10
#define INTERRUPT_HSP1_SI_11   NV_DCE_IRQ_HSP1_SI_11
#define INTERRUPT_HSP1_SI_12   NV_DCE_IRQ_HSP1_SI_12
#define INTERRUPT_HSP1_SI_13   NV_DCE_IRQ_HSP1_SI_13
#define INTERRUPT_HSP1_SI_14   NV_DCE_IRQ_HSP1_SI_14
#define INTERRUPT_HSP1_SI_15   NV_DCE_IRQ_HSP1_SI_15

/*
 * VIC1 interrupts
 */
#define INTERRUPT_WDTIRQ        NV_DCE_IRQ_WDTIRQ
#define INTERRUPT_WDTFIQ        NV_DCE_IRQ_WDTFIQ
#define INTERRUPT_TIMER0        NV_DCE_IRQ_TIMER0
#define INTERRUPT_TIMER1        NV_DCE_IRQ_TIMER1
#define INTERRUPT_TIMER2        NV_DCE_IRQ_TIMER2
#define INTERRUPT_TIMER3        NV_DCE_IRQ_TIMER3
#define INTERRUPT_DMA0          NV_DCE_IRQ_DMA0
#define INTERRUPT_DMA1          NV_DCE_IRQ_DMA1
#define INTERRUPT_DMA2          NV_DCE_IRQ_DMA2
#define INTERRUPT_DMA3          NV_DCE_IRQ_DMA3
#define INTERRUPT_DMA4          NV_DCE_IRQ_DMA4
#define INTERRUPT_DMA5          NV_DCE_IRQ_DMA5
#define INTERRUPT_DMA6          NV_DCE_IRQ_DMA6
#define INTERRUPT_DMA7          NV_DCE_IRQ_DMA7
#define INTERRUPT_PMU           NV_DCE_IRQ_PMU
#define INTERRUPT_FPUINT        NV_DCE_IRQ_FPUINT
#define INTERRUPT_CTIIRQ        NV_DCE_IRQ_CTIIRQ
#define INTERRUPT_NOC_SECURE    NV_DCE_IRQ_NOC_SECURE
#define INTERRUPT_ACTMON        NV_DCE_IRQ_ACTMON
#define INTERRUPT_GTE           NV_DCE_IRQ_GTE
#define INTERRUPT_MISC0         NV_DCE_IRQ_MISC0
#define INTERRUPT_MISC1         NV_DCE_IRQ_MISC1
#define INTERRUPT_RSVD22        NV_DCE_IRQ_RSVD22
#define INTERRUPT_RSVD23        NV_DCE_IRQ_RSVD23
#define INTERRUPT_RSVD24        NV_DCE_IRQ_RSVD24
#define INTERRUPT_RSVD25        NV_DCE_IRQ_RSVD25
#define INTERRUPT_RSVD26        NV_DCE_IRQ_RSVD26
#define INTERRUPT_RSVD27        NV_DCE_IRQ_RSVD27
#define INTERRUPT_RSVD28        NV_DCE_IRQ_RSVD28
#define INTERRUPT_RSVD29        NV_DCE_IRQ_RSVD29
#define INTERRUPT_RSVD30        NV_DCE_IRQ_RSVD30
#define INTERRUPT_RSVD31        NV_DCE_IRQ_RSVD31

/*
 * VIC2 Interrupts
 */
#define INTERRUPT_TOP0_HSP_DB   NV_DCE_IRQ_TOP0_HSP_DB
#define INTERRUPT_LIC_IRQ0      NV_DCE_IRQ_LIC_IRQ0
#define INTERRUPT_LIC_FIQ0      NV_DCE_IRQ_LIC_FIQ0
#define INTERRUPT_I2C0          NV_DCE_IRQ_I2C0
#define INTERRUPT_I2C1          NV_DCE_IRQ_I2C1
#define INTERRUPT_I2C3          NV_DCE_IRQ_I2C3
#define INTERRUPT_I2C4          NV_DCE_IRQ_I2C4
#define INTERRUPT_I2C6          NV_DCE_IRQ_I2C6
#define INTERRUPT_I2C7          NV_DCE_IRQ_I2C7
#define INTERRUPT_I2C8          NV_DCE_IRQ_I2C8
#define INTERRUPT_I2C9          NV_DCE_IRQ_I2C9
#define INTERRUPT_I2C10         NV_DCE_IRQ_I2C10
#define INTERRUPT_I2C11         NV_DCE_IRQ_I2C11
#define INTERRUPT_I2C12         NV_DCE_IRQ_I2C12
#define INTERRUPT_I2C14         NV_DCE_IRQ_I2C14
#define INTERRUPT_I2C15         NV_DCE_IRQ_I2C15
#define INTERRUPT_I2C16         NV_DCE_IRQ_I2C16
#define INTERRUPT_NVDISPLAY     NV_DCE_IRQ_NVDISPLAY
#define INTERRUPT_DPAUX0        NV_DCE_IRQ_DPAUX0
#define INTERRUPT_DPAUX1        NV_DCE_IRQ_DPAUX1
#define INTERRUPT_DPAUX2        NV_DCE_IRQ_DPAUX2
#define INTERRUPT_DPAUX3        NV_DCE_IRQ_DPAUX3

#endif
