/*
 * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */
#ifndef AST_DEFS_H
#define AST_DEFS_H
#define FSP__SOC_COMMON__AST_DEFS_H     1

/* Compiler headers */
#include <stdint.h>                 // for uint32_t, uint8_t, uint64_t

/* Early FSP headers */
#include <soc-common/hw-const.h>    // Must appear before any hwinc files

/* Hardware headers */
#include <araps_ast.h>              // for APS_AST_CONTROL_0, APS_AST_REGION...

/* Late FSP headers */

/* Module-specific FSP headers */

/**
 * @brief Number of regions each AST provides
 */
#define AST_NUM_REGIONS         32U

static inline uint32_t
tegra_ast_get_num_regions(void)
{
    return AST_NUM_REGIONS;
}

/**
 * @brief Slave base of the DM region that contains the enable bit
 */
#define AST_DM_REGION_SLAVE_BASE_LO     APS_AST_DM_REGION_SLAVE_BASE_LO_0

#endif
