diff --git a/overlay/tegra234-base-overlay.dtsi b/overlay/tegra234-base-overlay.dtsi
index 904947a..411a08a 100644
--- a/overlay/tegra234-base-overlay.dtsi
+++ b/overlay/tegra234-base-overlay.dtsi
@@ -349,28 +349,6 @@
 						     "nvidia,tegra194-pwm";
 				};
 
-				pmc@c360000 {
-					sdmmc1_3v3: sdmmc1-3v3 {
-						pins = "sdmmc1-hv";
-						power-source = <1>;
-					};
-
-					sdmmc1_1v8: sdmmc1-1v8 {
-						pins = "sdmmc1-hv";
-						power-source = <0>;
-					};
-
-					sdmmc3_3v3: sdmmc3-3v3 {
-						pins = "sdmmc3-hv";
-						power-source = <1>;
-					};
-
-					sdmmc3_1v8: sdmmc3-1v8 {
-						pins = "sdmmc3-hv";
-						power-source = <0>;
-					};
-				};
-
 				phy@3e00000 {
 					interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L0_P2U IRQ_TYPE_LEVEL_HIGH>;
 					interrupt-names = "intr";
diff --git a/overlay/tegra234-soc-overlay.dtsi b/overlay/tegra234-soc-overlay.dtsi
index de236ca..3bad27c 100644
--- a/overlay/tegra234-soc-overlay.dtsi
+++ b/overlay/tegra234-soc-overlay.dtsi
@@ -153,56 +153,6 @@
 					status = "disabled";
 				};
 
-				serial@31d0000 {
-					compatible = "arm,sbsa-uart";
-					reg = <0x31d0000 0x10000>;
-					interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
-					current-speed = <115200>;
-					status = "disabled";
-				};
-
-				mmc@3400000 {
-					compatible = "nvidia,tegra234-sdhci", "nvidia,tegra194-sdhci";
-					reg = <0x03400000 0x20000>;
-					interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-					clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
-						 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
-					clock-names = "sdhci", "tmclk";
-					assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
-							 <&bpmp TEGRA234_CLK_PLLC4_MUXED>;
-					assigned-clock-parents =
-								<&bpmp TEGRA234_CLK_PLLC4_MUXED>,
-								<&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
-					resets = <&bpmp TEGRA234_RESET_SDMMC1>;
-					reset-names = "sdhci";
-					interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>,
-					<&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>;
-					interconnect-names = "dma-mem", "write";
-					iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>;
-					pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
-					pinctrl-0 = <&sdmmc1_3v3>;
-					pinctrl-1 = <&sdmmc1_1v8>;
-					nvidia,pad-autocal-pull-up-offset-3v3-timeout =
-											<0x07>;
-					nvidia,pad-autocal-pull-down-offset-3v3-timeout =
-											<0x07>;
-					nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
-					nvidia,pad-autocal-pull-down-offset-1v8-timeout =
-											<0x07>;
-					nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
-					nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
-					nvidia,default-tap = <14>;
-					nvidia,default-trim = <0x8>;
-					sd-uhs-sdr25;
-					sd-uhs-sdr50;
-					sd-uhs-ddr50;
-					sd-uhs-sdr104;
-					bus-width = <4>;
-					cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
-					disable-wp;
-					status = "disabled";
-				};
-
 				tachometer@39c0000 {
 					compatible = "nvidia,pwm-tegra234-tachometer";
 					reg = <0x039c0000 0x10>;
@@ -477,90 +427,6 @@
 					status = "disabled";
 				};
 
-				pwm2: pwm@3290000 {
-					compatible = "nvidia,tegra234-pwm",
-						     "nvidia,tegra194-pwm";
-					reg = <0x3290000 0x10000>;
-					clocks = <&bpmp TEGRA234_CLK_PWM2>;
-					clock-names = "pwm";
-					resets = <&bpmp TEGRA234_RESET_PWM2>;
-					reset-names = "pwm";
-					status = "disabled";
-					#pwm-cells = <2>;
-				};
-
-				pwm3: pwm@32a0000 {
-					compatible = "nvidia,tegra234-pwm",
-						     "nvidia,tegra194-pwm";
-					reg = <0x32a0000 0x10000>;
-					clocks = <&bpmp TEGRA234_CLK_PWM3>;
-					clock-names = "pwm";
-					resets = <&bpmp TEGRA234_RESET_PWM3>;
-					reset-names = "pwm";
-					status = "disabled";
-					#pwm-cells = <2>;
-				};
-
-				pwm4: pwm@c340000 {
-					compatible = "nvidia,tegra234-pwm",
-						     "nvidia,tegra194-pwm";
-					reg = <0xc340000 0x10000>;
-					clocks = <&bpmp TEGRA234_CLK_PWM4>;
-					clock-names = "pwm";
-					resets = <&bpmp TEGRA234_RESET_PWM4>;
-					reset-names = "pwm";
-					status = "disabled";
-					#pwm-cells = <2>;
-				};
-
-				pwm5: pwm@32c0000 {
-					compatible = "nvidia,tegra234-pwm",
-						     "nvidia,tegra194-pwm";
-					reg = <0x32c0000 0x10000>;
-					clocks = <&bpmp TEGRA234_CLK_PWM5>;
-					clock-names = "pwm";
-					resets = <&bpmp TEGRA234_RESET_PWM5>;
-					reset-names = "pwm";
-					status = "disabled";
-					#pwm-cells = <2>;
-				};
-
-				pwm6: pwm@32d0000 {
-					compatible = "nvidia,tegra234-pwm",
-						     "nvidia,tegra194-pwm";
-					reg = <0x32d0000 0x10000>;
-					clocks = <&bpmp TEGRA234_CLK_PWM6>;
-					clock-names = "pwm";
-					resets = <&bpmp TEGRA234_RESET_PWM6>;
-					reset-names = "pwm";
-					status = "disabled";
-					#pwm-cells = <2>;
-				};
-
-				pwm7: pwm@32e0000 {
-					compatible = "nvidia,tegra234-pwm",
-						     "nvidia,tegra194-pwm";
-					reg = <0x32e0000 0x10000>;
-					clocks = <&bpmp TEGRA234_CLK_PWM7>;
-					clock-names = "pwm";
-					resets = <&bpmp TEGRA234_RESET_PWM7>;
-					reset-names = "pwm";
-					status = "disabled";
-					#pwm-cells = <2>;
-				};
-
-				pwm8: pwm@32f0000 {
-					compatible = "nvidia,tegra234-pwm",
-						     "nvidia,tegra194-pwm";
-					reg = <0x32f0000 0x10000>;
-					clocks = <&bpmp TEGRA234_CLK_PWM8>;
-					clock-names = "pwm";
-					resets = <&bpmp TEGRA234_RESET_PWM8>;
-					reset-names = "pwm";
-					status = "disabled";
-					#pwm-cells = <2>;
-				};
-
 				host1x@13e00000 {
 					dma-coherent;
 
@@ -583,26 +449,6 @@
 						status = "disabled";
 					};
 
-					nvdec@15480000 {
-						compatible = "nvidia,tegra234-nvdec";
-						reg = <0x15480000 0x00040000>;
-						clocks = <&bpmp TEGRA234_CLK_NVDEC>,
-							 <&bpmp TEGRA234_CLK_FUSE>,
-							 <&bpmp TEGRA234_CLK_TSEC_PKA>;
-						clock-names = "nvdec", "fuse", "tsec_pka";
-						resets = <&bpmp TEGRA234_RESET_NVDEC>;
-						reset-names = "nvdec";
-						power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
-						interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
-								<&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
-						interconnect-names = "dma-mem", "write";
-						iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
-						dma-coherent;
-
-						nvidia,memory-controller = <&mc>;
-						status = "disabled";
-					};
-
 					nvenc@154c0000 {
 						compatible = "nvidia,tegra234-nvenc";
 						reg = <0x154c0000 0x00040000>;
@@ -1017,174 +863,6 @@
 					status = "disabled";
 				};
 
-				xusb_padctl: padctl@3520000 {
-					compatible = "nvidia,tegra234-xusb-padctl";
-					reg = <0x03520000 0x20000>,
-					      <0x03540000 0x10000>;
-					reg-names = "padctl", "ao";
-					interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-
-					resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>;
-					reset-names = "padctl";
-
-					status = "disabled";
-
-					pads {
-						usb2 {
-							clocks = <&bpmp TEGRA234_CLK_USB2_TRK>;
-							clock-names = "trk";
-
-							lanes {
-								xpads_usb2_lanes_usb2_0: usb2-0 {
-									nvidia,function = "xusb";
-									status = "disabled";
-									#phy-cells = <0>;
-								};
-
-								xpads_usb2_lanes_usb2_1: usb2-1 {
-									nvidia,function = "xusb";
-									status = "disabled";
-									#phy-cells = <0>;
-								};
-
-								xpads_usb2_lanes_usb2_2: usb2-2 {
-									nvidia,function = "xusb";
-									status = "disabled";
-									#phy-cells = <0>;
-								};
-
-								xpads_usb2_lanes_usb2_3: usb2-3 {
-									nvidia,function = "xusb";
-									status = "disabled";
-									#phy-cells = <0>;
-								};
-							};
-						};
-
-						usb3 {
-							lanes {
-								xpads_usb3_lanes_usb3_0: usb3-0 {
-									nvidia,function = "xusb";
-									status = "disabled";
-									#phy-cells = <0>;
-								};
-
-								xpads_usb3_lanes_usb3_1: usb3-1 {
-									nvidia,function = "xusb";
-									status = "disabled";
-									#phy-cells = <0>;
-								};
-
-								xpads_usb3_lanes_usb3_2: usb3-2 {
-									nvidia,function = "xusb";
-									status = "disabled";
-									#phy-cells = <0>;
-								};
-
-								xpads_usb3_lanes_usb3_3: usb3-3 {
-									nvidia,function = "xusb";
-									status = "disabled";
-									#phy-cells = <0>;
-								};
-							};
-						};
-					};
-
-					ports {
-						usb2-0 {
-							status = "disabled";
-						};
-
-						usb2-1 {
-							status = "disabled";
-						};
-
-						usb2-2 {
-							status = "disabled";
-						};
-
-						usb2-3 {
-							status = "disabled";
-						};
-
-						usb3-0 {
-							status = "disabled";
-						};
-
-						usb3-1 {
-							status = "disabled";
-						};
-
-						usb3-2 {
-							status = "disabled";
-						};
-
-						usb3-3 {
-							status = "disabled";
-						};
-					};
-				};
-
-				usb@3550000 {
-					compatible = "nvidia,tegra234-xudc";
-					reg = <0x03550000 0x8000>,
-					      <0x03558000 0x8000>;
-					reg-names = "base", "fpci";
-					interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
-					clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>,
-						 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
-						 <&bpmp TEGRA234_CLK_XUSB_SS>,
-						 <&bpmp TEGRA234_CLK_XUSB_FS>;
-					clock-names = "dev", "ss", "ss_src", "fs_src";
-					interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>,
-							<&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>;
-					interconnect-names = "dma-mem", "write";
-					iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>;
-					power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>,
-							<&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
-					power-domain-names = "dev", "ss";
-					nvidia,xusb-padctl = <&xusb_padctl>;
-					dma-coherent;
-					status = "disabled";
-				};
-
-				usb@3610000 {
-					compatible = "nvidia,tegra234-xusb";
-					reg = <0x03610000 0x40000>,
-					      <0x03600000 0x10000>,
-					      <0x03650000 0x10000>;
-					reg-names = "hcd", "fpci", "bar2";
-
-					interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
-						     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
-
-					clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
-						 <&bpmp TEGRA234_CLK_XUSB_FALCON>,
-						 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
-						 <&bpmp TEGRA234_CLK_XUSB_SS>,
-						 <&bpmp TEGRA234_CLK_CLK_M>,
-						 <&bpmp TEGRA234_CLK_XUSB_FS>,
-						 <&bpmp TEGRA234_CLK_UTMIP_PLL>,
-						 <&bpmp TEGRA234_CLK_CLK_M>,
-						 <&bpmp TEGRA234_CLK_PLLE>;
-					clock-names = "xusb_host", "xusb_falcon_src",
-						      "xusb_ss", "xusb_ss_src", "xusb_hs_src",
-						      "xusb_fs_src", "pll_u_480m", "clk_m",
-						      "pll_e";
-					interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>,
-							<&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>;
-					interconnect-names = "dma-mem", "write";
-					iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>;
-
-					power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
-							<&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
-					power-domain-names = "xusb_host", "xusb_ss";
-
-					nvidia,xusb-padctl = <&xusb_padctl>;
-					dma-coherent;
-					status = "disabled";
-				};
-
 				hsp_top2: hsp@1600000 {
 					compatible = "nvidia,tegra234-hsp";
 					reg = <0x1600000 0x90000>;
diff --git a/tegra234.dtsi b/tegra234.dtsi
index 2674878..bb3de06 100644
--- a/tegra234.dtsi
+++ b/tegra234.dtsi
@@ -5,6 +5,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/tegra186-hsp.h>
 #include <dt-bindings/memory/tegra234-mc.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
 #include <dt-bindings/power/tegra234-powergate.h>
 #include <dt-bindings/reset/tegra234-reset.h>
 
@@ -784,6 +785,13 @@
 			dma-names = "rx", "tx";
 		};
 
+		uarti: serial@31d0000 {
+			compatible = "arm,sbsa-uart";
+			reg = <0x31d0000 0x10000>;
+			interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
 		dp_aux_ch3_i2c: i2c@31e0000 {
 			compatible = "nvidia,tegra194-i2c";
 			reg = <0x31e0000 0x100>;
@@ -831,6 +839,65 @@
 			#pwm-cells = <2>;
 		};
 
+		pwm2: pwm@3290000 {
+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+			reg = <0x3290000 0x10000>;
+			clocks = <&bpmp TEGRA234_CLK_PWM2>;
+			resets = <&bpmp TEGRA234_RESET_PWM2>;
+			reset-names = "pwm";
+			status = "disabled";
+			#pwm-cells = <2>;
+		};
+
+		pwm3: pwm@32a0000 {
+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+			reg = <0x32a0000 0x10000>;
+			clocks = <&bpmp TEGRA234_CLK_PWM3>;
+			resets = <&bpmp TEGRA234_RESET_PWM3>;
+			reset-names = "pwm";
+			status = "disabled";
+			#pwm-cells = <2>;
+		};
+
+		pwm5: pwm@32c0000 {
+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+			reg = <0x32c0000 0x10000>;
+			clocks = <&bpmp TEGRA234_CLK_PWM5>;
+			resets = <&bpmp TEGRA234_RESET_PWM5>;
+			reset-names = "pwm";
+			status = "disabled";
+			#pwm-cells = <2>;
+		};
+
+		pwm6: pwm@32d0000 {
+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+			reg = <0x32d0000 0x10000>;
+			clocks = <&bpmp TEGRA234_CLK_PWM6>;
+			resets = <&bpmp TEGRA234_RESET_PWM6>;
+			reset-names = "pwm";
+			status = "disabled";
+			#pwm-cells = <2>;
+		};
+
+		pwm7: pwm@32e0000 {
+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+			reg = <0x32e0000 0x10000>;
+			clocks = <&bpmp TEGRA234_CLK_PWM7>;
+			resets = <&bpmp TEGRA234_RESET_PWM7>;
+			reset-names = "pwm";
+			status = "disabled";
+			#pwm-cells = <2>;
+		};
+
+		pwm8: pwm@32f0000 {
+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+			reg = <0x32f0000 0x10000>;
+			clocks = <&bpmp TEGRA234_CLK_PWM8>;
+			resets = <&bpmp TEGRA234_RESET_PWM8>;
+			reset-names = "pwm";
+			status = "disabled";
+			#pwm-cells = <2>;
+		};
 
 		spi@3300000 {
 			compatible = "nvidia,tegra234-qspi";
@@ -846,6 +913,41 @@
 			status = "disabled";
 		};
 
+		mmc@3400000 {
+			compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
+			reg = <0x03400000 0x20000>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
+				 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
+			clock-names = "sdhci", "tmclk";
+			assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
+					  <&bpmp TEGRA234_CLK_PLLC4_MUXED>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
+						 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
+			resets = <&bpmp TEGRA234_RESET_SDMMC1>;
+			reset-names = "sdhci";
+			interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>,
+					<&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>;
+			interconnect-names = "dma-mem", "write";
+			iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>;
+			pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+			pinctrl-0 = <&sdmmc1_3v3>;
+			pinctrl-1 = <&sdmmc1_1v8>;
+			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
+			nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
+			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
+			nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
+			nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
+			nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
+			nvidia,default-tap = <14>;
+			nvidia,default-trim = <0x8>;
+			sd-uhs-sdr25;
+			sd-uhs-sdr50;
+			sd-uhs-ddr50;
+			sd-uhs-sdr104;
+			status = "disabled";
+		};
+
 		mmc@3460000 {
 			compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
 			reg = <0x03460000 0x20000>;
@@ -893,6 +995,174 @@
 			status = "disabled";
 		};
 
+		xusb_padctl: padctl@3520000 {
+			compatible = "nvidia,tegra234-xusb-padctl";
+			reg = <0x03520000 0x20000>,
+			      <0x03540000 0x10000>;
+			reg-names = "padctl", "ao";
+			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+
+			resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>;
+			reset-names = "padctl";
+
+			status = "disabled";
+
+			pads {
+				usb2 {
+					clocks = <&bpmp TEGRA234_CLK_USB2_TRK>;
+					clock-names = "trk";
+
+					lanes {
+						xpads_usb2_lanes_usb2_0: usb2-0 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+
+						xpads_usb2_lanes_usb2_1: usb2-1 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+
+						xpads_usb2_lanes_usb2_2: usb2-2 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+
+						xpads_usb2_lanes_usb2_3: usb2-3 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+					};
+				};
+
+				usb3 {
+					lanes {
+						xpads_usb3_lanes_usb3_0: usb3-0 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+
+						xpads_usb3_lanes_usb3_1: usb3-1 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+
+						xpads_usb3_lanes_usb3_2: usb3-2 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+
+						xpads_usb3_lanes_usb3_3: usb3-3 {
+							nvidia,function = "xusb";
+							status = "disabled";
+							#phy-cells = <0>;
+						};
+					};
+				};
+			};
+
+			ports {
+				usb2-0 {
+					status = "disabled";
+				};
+
+				usb2-1 {
+					status = "disabled";
+				};
+
+				usb2-2 {
+					status = "disabled";
+				};
+
+				usb2-3 {
+					status = "disabled";
+				};
+
+				usb3-0 {
+					status = "disabled";
+				};
+
+				usb3-1 {
+					status = "disabled";
+				};
+
+				usb3-2 {
+					status = "disabled";
+				};
+
+				usb3-3 {
+					status = "disabled";
+				};
+			};
+		};
+
+		usb@3550000 {
+			compatible = "nvidia,tegra234-xudc";
+			reg = <0x03550000 0x8000>,
+			      <0x03558000 0x8000>;
+			reg-names = "base", "fpci";
+			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>,
+				 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
+				 <&bpmp TEGRA234_CLK_XUSB_SS>,
+				 <&bpmp TEGRA234_CLK_XUSB_FS>;
+			clock-names = "dev", "ss", "ss_src", "fs_src";
+			interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>,
+					<&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>;
+			interconnect-names = "dma-mem", "write";
+			iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>;
+			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>,
+					<&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
+			power-domain-names = "dev", "ss";
+			nvidia,xusb-padctl = <&xusb_padctl>;
+			dma-coherent;
+			status = "disabled";
+		};
+
+		usb@3610000 {
+			compatible = "nvidia,tegra234-xusb";
+			reg = <0x03610000 0x40000>,
+			      <0x03600000 0x10000>,
+			      <0x03650000 0x10000>;
+			reg-names = "hcd", "fpci", "bar2";
+
+			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
+				 <&bpmp TEGRA234_CLK_XUSB_FALCON>,
+				 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
+				 <&bpmp TEGRA234_CLK_XUSB_SS>,
+				 <&bpmp TEGRA234_CLK_CLK_M>,
+				 <&bpmp TEGRA234_CLK_XUSB_FS>,
+				 <&bpmp TEGRA234_CLK_UTMIP_PLL>,
+				 <&bpmp TEGRA234_CLK_CLK_M>,
+				 <&bpmp TEGRA234_CLK_PLLE>;
+			clock-names = "xusb_host", "xusb_falcon_src",
+				      "xusb_ss", "xusb_ss_src", "xusb_hs_src",
+				      "xusb_fs_src", "pll_u_480m", "clk_m",
+				      "pll_e";
+			interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>,
+					<&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>;
+			interconnect-names = "dma-mem", "write";
+			iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>;
+
+			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
+					<&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
+			power-domain-names = "xusb_host", "xusb_ss";
+
+			nvidia,xusb-padctl = <&xusb_padctl>;
+			dma-coherent;
+			status = "disabled";
+		};
+
 		fuse@3810000 {
 			compatible = "nvidia,tegra234-efuse";
 			reg = <0x03810000 0x10000>;
@@ -1496,6 +1766,16 @@
 			gpio-controller;
 		};
 
+		pwm4: pwm@c340000 {
+			compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
+			reg = <0xc340000 0x10000>;
+			clocks = <&bpmp TEGRA234_CLK_PWM4>;
+			resets = <&bpmp TEGRA234_RESET_PWM4>;
+			reset-names = "pwm";
+			status = "disabled";
+			#pwm-cells = <2>;
+		};
+
 		pmc: pmc@c360000 {
 			compatible = "nvidia,tegra234-pmc";
 			reg = <0x0c360000 0x10000>,
@@ -1507,6 +1787,26 @@
 
 			#interrupt-cells = <2>;
 			interrupt-controller;
+
+			sdmmc1_1v8: sdmmc1-1v8 {
+				pins = "sdmmc1-hv";
+				power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+			};
+
+			sdmmc1_3v3: sdmmc1-3v3 {
+				pins = "sdmmc1-hv";
+				power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+			};
+
+			sdmmc3_1v8: sdmmc3-1v8 {
+				pins = "sdmmc3-hv";
+				power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+			};
+
+			sdmmc3_3v3: sdmmc3-3v3 {
+				pins = "sdmmc3-hv";
+				power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+			};
 		};
 
 		aon-fabric@c600000 {
@@ -1900,6 +2200,42 @@
 				iommus = <&smmu_niso1 TEGRA234_SID_VIC>;
 				dma-coherent;
 			};
+
+			nvdec@15480000 {
+				compatible = "nvidia,tegra234-nvdec";
+				reg = <0x15480000 0x00040000>;
+				clocks = <&bpmp TEGRA234_CLK_NVDEC>,
+					 <&bpmp TEGRA234_CLK_FUSE>,
+					 <&bpmp TEGRA234_CLK_TSEC_PKA>;
+				clock-names = "nvdec", "fuse", "tsec_pka";
+				resets = <&bpmp TEGRA234_RESET_NVDEC>;
+				reset-names = "nvdec";
+				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
+				interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
+						<&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
+				interconnect-names = "dma-mem", "write";
+				iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
+				dma-coherent;
+
+				nvidia,memory-controller = <&mc>;
+
+				/*
+				 * Placeholder values that firmware needs to update with the real
+				 * offsets parsed from the microcode headers.
+				 */
+				nvidia,bl-manifest-offset = <0>;
+				nvidia,bl-data-offset = <0>;
+				nvidia,bl-code-offset = <0>;
+				nvidia,os-manifest-offset = <0>;
+				nvidia,os-data-offset = <0>;
+				nvidia,os-code-offset = <0>;
+
+				/*
+				 * Firmware needs to set this to "okay" once the above values have
+				 * been updated.
+				 */
+				status = "disabled";
+			};
 		};
 	};