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overlay: refactor fragments for main overlays

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Use 1 fragment with target '/'. This makes it easier to migrate code
from an overlay to a base dtb.

Bug 4290389

Change-Id: I8427d9bb1b42d9cd7923a72a3ab026b4db4b6924
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2992246
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Gautham Srinivasan <gauthams@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Brad Griffis
2023-10-05 22:58:04 +00:00
committed by mobile promotions
parent 2b8131ec80
commit 10775b443a
2 changed files with 93 additions and 107 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
overlay/tegra234-p3740-0002+p3701-0008-safety.dts
View File

@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/dts-v1/;
/plugin/;
@@ -75,18 +74,16 @@
*/
nvidia,tegra-joint_xpu_rail;
};
};
};
fragment-t234-p3740-p3701-safety@1 {
target-path = "/";
__overlay__ {
fsicom_client {
status = "okay";
cpus {
idle-states {
c7 {
status = "disabled";
};
};
};
safetyservices_epl_client {
/* userspace app uses this driver to send error code */
fsicom_client {
status = "okay";
};
@@ -107,18 +104,10 @@
mbox-names = "hsierrrptinj-tx";
status = "okay";
};
};
};
fragment-t234-p3740-p3701-safety@2 {
target-path = "/";
__overlay__ {
cpus {
idle-states {
c7 {
status = "disabled";
};
};
safetyservices_epl_client {
/* userspace app uses this driver to send error code */
status = "okay";
};
thermal-zones {

169
overlay/tegra234-soc-camera.dtsi
View File

@@ -20,6 +20,89 @@
tegra-camera-rtcpu = "/rtcpu@bc00000";
};
bus@0 {
host1x@13e00000 {
vi0: vi0@15c00000 {
compatible = "nvidia,tegra234-vi";
clocks = <&bpmp TEGRA234_CLK_VI>;
clock-names = "vi";
nvidia,vi-falcon-device = <&vi0_thi>;
resets = <&bpmp TEGRA234_RESET_VI>;
reset-names = "vi0";
iommus = <&smmu_iso TEGRA234_SID_ISO_VI>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIW &emc>;
interconnect-names = "write";
non-coherent;
status = "okay";
};
vi0_thi: vi0-thi@15f00000 {
compatible = "nvidia,tegra234-vi-thi";
resets = <&bpmp TEGRA234_RESET_VI>;
reset-names = "vi0_thi";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2FALR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_VI2FALW &emc>;
interconnect-names = "dma-mem", "write";
status = "okay";
};
vi1: vi1@14c00000 {
compatible = "nvidia,tegra234-vi";
clocks = <&bpmp TEGRA234_CLK_VI>;
clock-names = "vi";
nvidia,vi-falcon-device = <&vi1_thi>;
resets = <&bpmp TEGRA234_RESET_VI2>;
reset-names = "vi1";
iommus = <&smmu_iso TEGRA234_SID_ISO_VI2>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2W &emc>;
interconnect-names = "write";
non-coherent;
status = "okay";
};
vi1_thi: vi1-thi@14f00000 {
compatible = "nvidia,tegra234-vi-thi";
resets = <&bpmp TEGRA234_RESET_VI2>;
reset-names = "vi1_thi";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIFALR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_VIFALW &emc>;
interconnect-names = "dma-mem", "write";
status = "okay";
};
isp: isp@14800000 {
compatible = "nvidia,tegra194-isp";
reg = <0x0 0x14800000 0x0 0x00010000>;
resets = <&bpmp TEGRA234_RESET_ISP>;
reset-names = "isp";
clocks = <&bpmp TEGRA234_CLK_ISP>;
clock-names = "isp";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_ISPA>;
nvidia,isp-falcon-device = <&isp_thi>;
iommus = <&smmu_niso1 TEGRA234_SID_ISP>;
dma-coherent;
status = "okay";
};
isp_thi: isp-thi@14b00000 {
compatible = "nvidia,tegra194-isp-thi";
resets = <&bpmp TEGRA234_RESET_ISP>;
status = "okay";
};
nvcsi: nvcsi@15a00000 {
compatible = "nvidia,tegra194-nvcsi";
resets = <&bpmp TEGRA234_RESET_NVCSI>;
reset-names = "nvcsi";
clocks = <&bpmp TEGRA234_CLK_NVCSI>;
clock-names = "nvcsi";
status = "okay";
};
};
};
tegra_rce: rtcpu@bc00000 {
compatible = "nvidia,tegra194-rce";
@@ -184,90 +267,4 @@
};
};
};
fragment-camera@1 {
target-path = "/bus@0";
__overlay__ {
host1x@13e00000 {
vi0: vi0@15c00000 {
compatible = "nvidia,tegra234-vi";
clocks = <&bpmp TEGRA234_CLK_VI>;
clock-names = "vi";
nvidia,vi-falcon-device = <&vi0_thi>;
resets = <&bpmp TEGRA234_RESET_VI>;
reset-names = "vi0";
iommus = <&smmu_iso TEGRA234_SID_ISO_VI>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIW &emc>;
interconnect-names = "write";
non-coherent;
status = "okay";
};
vi0_thi: vi0-thi@15f00000 {
compatible = "nvidia,tegra234-vi-thi";
resets = <&bpmp TEGRA234_RESET_VI>;
reset-names = "vi0_thi";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2FALR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_VI2FALW &emc>;
interconnect-names = "dma-mem", "write";
status = "okay";
};
vi1: vi1@14c00000 {
compatible = "nvidia,tegra234-vi";
clocks = <&bpmp TEGRA234_CLK_VI>;
clock-names = "vi";
nvidia,vi-falcon-device = <&vi1_thi>;
resets = <&bpmp TEGRA234_RESET_VI2>;
reset-names = "vi1";
iommus = <&smmu_iso TEGRA234_SID_ISO_VI2>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2W &emc>;
interconnect-names = "write";
non-coherent;
status = "okay";
};
vi1_thi: vi1-thi@14f00000 {
compatible = "nvidia,tegra234-vi-thi";
resets = <&bpmp TEGRA234_RESET_VI2>;
reset-names = "vi1_thi";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIFALR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_VIFALW &emc>;
interconnect-names = "dma-mem", "write";
status = "okay";
};
isp: isp@14800000 {
compatible = "nvidia,tegra194-isp";
reg = <0x0 0x14800000 0x0 0x00010000>;
resets = <&bpmp TEGRA234_RESET_ISP>;
reset-names = "isp";
clocks = <&bpmp TEGRA234_CLK_ISP>;
clock-names = "isp";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_ISPA>;
nvidia,isp-falcon-device = <&isp_thi>;
iommus = <&smmu_niso1 TEGRA234_SID_ISP>;
dma-coherent;
status = "okay";
};
isp_thi: isp-thi@14b00000 {
compatible = "nvidia,tegra194-isp-thi";
resets = <&bpmp TEGRA234_RESET_ISP>;
status = "okay";
};
nvcsi: nvcsi@15a00000 {
compatible = "nvidia,tegra194-nvcsi";
resets = <&bpmp TEGRA234_RESET_NVCSI>;
reset-names = "nvcsi";
clocks = <&bpmp TEGRA234_CLK_NVCSI>;
clock-names = "nvcsi";
status = "okay";
};
};
};
};
};