diff --git a/overlay/Makefile b/overlay/Makefile
index b3b0638..50a7a0b 100644
--- a/overlay/Makefile
+++ b/overlay/Makefile
@@ -41,6 +41,7 @@ dtbo-y += tegra234-p3767-0000+p3768-0000-csi.dtbo
 dtbo-y += tegra234-p3740-0002+p3701-0008-hdr20.dtbo
 dtbo-y += tegra234-p3740-0002+p3701-0008-m2ke.dtbo
 dtbo-y += tegra234-p3740-0002+p3701-0008-m2kb.dtbo
+dtbo-y += tegra234-p3740-0002-p3701-0008-csi.dtbo
 dtbo-y += tegra234-p3737-camera-dual-imx274-overlay.dtbo
 dtbo-y += tegra234-p3737-camera-e3331-overlay.dtbo
 dtbo-y += tegra234-p3737-camera-e3333-overlay.dtbo
diff --git a/overlay/tegra234-p3740-0002-p3701-0008-csi.dts b/overlay/tegra234-p3740-0002-p3701-0008-csi.dts
new file mode 100644
index 0000000..4cf7c3a
--- /dev/null
+++ b/overlay/tegra234-p3740-0002-p3701-0008-csi.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+/*
+ * Device-tree overlay for tegra234-p3740-0002-p3701-0008 CSI Camera Connector.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
+#include <dt-bindings/tegra234-p3740-0002-p3701-0008.h>
+
+/ {
+	overlay-name = "Jetson 122pin CSI Connector";
+	compatible = JETSON_COMPATIBLE;
+
+	p3740-0002_p3701-0008-csi@0 {
+		target = <&pinmux>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&jetson_io_pinmux>;
+			jetson_io_pinmux: exp-header-pinmux {
+				csi-pin75 {
+					nvidia,pins = "cam_i2c_scl_pp2";
+				};
+				csi-pin76a {
+					nvidia,pins = "spi5_cs0_pac3";
+					nvidia,function = "i2s3";
+					nvidia,pin-label = "i2s3_fs";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				csi-pin76b {
+					nvidia,pins = "spi5_cs0_pac3";
+					nvidia,function = "dmic2";
+					nvidia,pin-label = "dmic2_clk";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				csi-pin77 {
+					nvidia,pins = "cam_i2c_sda_pp3";
+				};
+				csi-pin90a{
+					nvidia,pins = "spi5_sck_pac0";
+					nvidia,function = "i2s3";
+					nvidia,pin-label = "i2s3_sclk";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				csi-pin90b {
+					nvidia,pins = "spi5_sck_pac0";
+					nvidia,function = "dspk0";
+					nvidia,pin-label = "dspk0_dat";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				csi-pin92a {
+					nvidia,pins = "spi5_miso_pac1";
+					nvidia,function = "i2s3";
+					nvidia,pin-label = "i2s3_dout";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				csi-pin92b {
+					nvidia,pins = "spi5_miso_pac1";
+					nvidia,function = "dspk0";
+					nvidia,pin-label = "dspk0_clk";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				csi-pin96a {
+					nvidia,pins = "spi5_mosi_pac2";
+					nvidia,function = "i2s3";
+					nvidia,pin-label="i2s3_din";
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				csi-pin96b {
+					nvidia,pins = "spi5_mosi_pac2";
+					nvidia,function = "dmic2";
+					nvidia,pin-label="dmic2_dat";
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				csi-pin105 {
+					nvidia,pins = "dp_aux_ch3_p_pn7";
+				};
+				csi-pin107 {
+					nvidia,pins = "dp_aux_ch3_n_pn0";
+				};
+			};
+		};
+	};
+	fragment@1 {
+		target = <&pinmux_aon>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&jetson_io_pinmux_aon>;
+			jetson_io_pinmux_aon: exp-header-pinmux {
+				csi-pin87 {
+					nvidia,pins = "gen2_i2c_scl_pcc7";
+				};
+				csi-pin89 {
+					nvidia,pins = "gen2_i2c_sda_pdd0";
+				};
+			};
+		};
+	};
+};