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p3701: Move INA from base DTSI to overlay DTSI

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The instance of the INA devices on P3701 is not available in mainline.
Hence, move the node of INA devices to the overlay file to make base
DTSI files sync to mainline version.

Bug 4037899

Change-Id: I10e7567e2d6f3e671d436610a3a4bb4dd3a5a084
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/platform/t23x/concord-generic-dts/+/2873253
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Laxman Dewangan
2023-03-18 17:12:32 +00:00
parent ddca643ebc
commit 1b14f4edd5
2 changed files with 49 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
overlay/tegra234-p3701-0000.dtsi
View File

@@ -4,5 +4,54 @@
#include "tegra234-p3737-0000-camera-imx274-dual.dtsi" #include "tegra234-p3737-0000-camera-imx274-dual.dtsi"
#include "tegra234-p3737-0000-camera-imx185-a00.dtsi" #include "tegra234-p3737-0000-camera-imx185-a00.dtsi"
/ { / {
fragment-t234-p3701-0001@0 {
target-path = "/bus@0/i2c@c240000";
__overlay__ {
status = "okay";
ina3221@40 {
compatible = "ti,ina3221";
reg = <0x40>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <0x0>;
label = "VDD_GPU_SOC";
shunt-resistor-micro-ohms = <2000>;
};
channel@1 {
reg = <0x1>;
label = "VDD_CPU_CV";
shunt-resistor-micro-ohms = <2000>;
};
channel@2 {
reg = <0x2>;
label = "VIN_SYS_5V0";
shunt-resistor-micro-ohms = <2000>;
};
};
ina3221@41 {
compatible = "ti,ina3221";
reg = <0x41>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <0x0>;
label = "NC";
};
channel@1 {
reg = <0x1>;
label = "VDDQ_VDD2_1V8AO";
shunt-resistor-micro-ohms = <2000>;
};
channel@2 {
reg = <0x2>;
label = "NC";
};
};
};
};
}; };

47
tegra234-p3701-0000.dtsi
View File

@@ -93,53 +93,6 @@
nvidia,invert-interrupt; nvidia,invert-interrupt;
}; };
i2c@c240000 {
status = "okay";
ina32211_1_40: ina3221@40 {
compatible = "ti,ina3221";
reg = <0x40>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <0x0>;
label = "VDD_GPU_SOC";
shunt-resistor-micro-ohms = <2000>;
};
channel@1 {
reg = <0x1>;
label = "VDD_CPU_CV";
shunt-resistor-micro-ohms = <2000>;
};
channel@2 {
reg = <0x2>;
label = "VIN_SYS_5V0";
shunt-resistor-micro-ohms = <2000>;
};
};
ina3221_1_41: ina3221@41 {
compatible = "ti,ina3221";
reg = <0x41>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <0x0>;
label = "NC";
};
channel@1 {
reg = <0x1>;
label = "VDDQ_VDD2_1V8AO";
shunt-resistor-micro-ohms = <2000>;
};
channel@2 {
reg = <0x2>;
label = "NC";
};
};
};
}; };
vdd_5v0_sys: regulator@0 { vdd_5v0_sys: regulator@0 {