From 1c4dfd0cc1f4d24f18fe445ce29f9eed3ae84bd4 Mon Sep 17 00:00:00 2001
From: Hiteshkumar Patel <hiteshkumarg@nvidia.com>
Date: Thu, 19 Dec 2024 05:51:25 +0000
Subject: [PATCH] t23x: dts: Add IGX500 to public repo

Add IGX500 dts support to nv-public

Bug 5018940

Change-Id: Ida4a7de3d060dc660acbbdbf9b5020ba198dc5d3
Signed-off-by: Hiteshkumar Patel <hiteshkumarg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3271404
(cherry picked from commit 34a5de4f2c74b55499ba00634dcbaca7cebc6e3e)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3275750
Reviewed-by: Dipen Patel <dipenp@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
---
 nv-platform/Makefile                          |   3 +
 .../tegra234-dcb-p3971-0000+p3701-0000.dtsi   | 534 ++++++++++++++++++
 .../tegra234-p3971-0000+p3701-0000-nv.dts     |  13 +
 ...gra234-p3971-0000+p3701-0008-nv-safety.dts |  10 +
 .../tegra234-p3971-0000+p3701-0008-nv.dts     |  13 +
 ...ra234-p3971-0000+p3701-xxxx-nv-common.dtsi | 356 ++++++++++++
 nv-platform/tegra234-p3971-0000.dtsi          | 387 +++++++++++++
 overlay/Makefile                              |   2 +
 ...+p3701-0008-camera-dual-imx274-overlay.dts | 344 +++++++++++
 ...00+p3701-0008-camera-p3762-a00-overlay.dts | 305 ++++++++++
 ...egra234-p3971-0000-camera-imx274-dual.dtsi |  66 +++
 11 files changed, 2033 insertions(+)
 create mode 100644 nv-platform/tegra234-dcb-p3971-0000+p3701-0000.dtsi
 create mode 100644 nv-platform/tegra234-p3971-0000+p3701-0000-nv.dts
 create mode 100644 nv-platform/tegra234-p3971-0000+p3701-0008-nv-safety.dts
 create mode 100644 nv-platform/tegra234-p3971-0000+p3701-0008-nv.dts
 create mode 100644 nv-platform/tegra234-p3971-0000+p3701-xxxx-nv-common.dtsi
 create mode 100644 nv-platform/tegra234-p3971-0000.dtsi
 create mode 100644 overlay/tegra234-p3971-0000+p3701-0008-camera-dual-imx274-overlay.dts
 create mode 100644 overlay/tegra234-p3971-0000+p3701-0008-camera-p3762-a00-overlay.dts
 create mode 100644 overlay/tegra234-p3971-0000-camera-imx274-dual.dtsi

diff --git a/nv-platform/Makefile b/nv-platform/Makefile
index b1f47dc..4e561e4 100644
--- a/nv-platform/Makefile
+++ b/nv-platform/Makefile
@@ -28,6 +28,9 @@ dtb-y += tegra234-p3768-0000+p3767-0004-nv.dtb
 dtb-y += tegra234-p3768-0000+p3767-0004-nv-super.dtb
 dtb-y += tegra234-p3768-0000+p3767-0005-nv.dtb
 dtb-y += tegra234-p3768-0000+p3767-0005-nv-super.dtb
+dtb-y += tegra234-p3971-0000+p3701-0000-nv.dtb
+dtb-y += tegra234-p3971-0000+p3701-0008-nv.dtb
+dtb-y += tegra234-p3971-0000+p3701-0008-nv-safety.dtb
 
 ifneq ($(dtb-y),)
 dtb-y := $(addprefix $(makefile-path)/,$(dtb-y))
diff --git a/nv-platform/tegra234-dcb-p3971-0000+p3701-0000.dtsi b/nv-platform/tegra234-dcb-p3971-0000+p3701-0000.dtsi
new file mode 100644
index 0000000..8b9f930
--- /dev/null
+++ b/nv-platform/tegra234-dcb-p3971-0000+p3701-0000.dtsi
@@ -0,0 +1,534 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+/ {
+	display@13800000 {
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+			06 0f 00 02 16 09 03 1d 0e 04 27 12 06 17 00 03
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+			00 00 00 00 01 05 05 00 40 00 00 00 00 00 30 10
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+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 10
+			00 00 00 00 03 00 01 00 50 00 00 00 00 00 00 0c
+			00 00 00 00 03 00 01 00 50 00 00 00 00 00 00 0a
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 09
+			00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 08
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+			08 00 00 00 10 08 00 1e 00 00 00 00 00 05 05 00
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+			00 00 00 00 00 00 00 10 00 00 00 00 03 00 01 00
+			50 00 00 00 00 00 00 0c 00 00 00 00 03 00 01 00
+			50 00 00 00 00 00 00 0a 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 09 00 00 00 00 03 00 01 00
+			40 00 00 00 00 00 00 08 00 00 00 00 03 00 01 00
+			40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 10 08 00 00 00 10 08 00 1e
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 14
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 10
+			00 00 00 00 03 00 01 00 50 00 00 00 00 00 00 0c
+			00 00 00 00 03 00 01 00 50 00 00 00 00 00 00 0a
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 09
+			00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 08
+			00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 06
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 10
+			08 00 00 00 10 08 00 1e 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 14 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 10 00 00 00 00 03 00 01 00
+			50 00 00 00 00 00 00 0c 00 00 00 00 03 00 01 00
+			50 00 00 00 00 00 00 0a 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 09 00 00 00 00 03 00 01 00
+			40 00 00 00 00 00 00 08 00 00 00 00 03 00 01 00
+			40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 ];
+	};
+};
diff --git a/nv-platform/tegra234-p3971-0000+p3701-0000-nv.dts b/nv-platform/tegra234-p3971-0000+p3701-0000-nv.dts
new file mode 100644
index 0000000..abc194f
--- /dev/null
+++ b/nv-platform/tegra234-p3971-0000+p3701-0000-nv.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+#include "../tegra234-p3701-0000.dtsi"
+#include "tegra234-p3701-0000.dtsi"
+#include "tegra234-p3971-0000+p3701-xxxx-nv-common.dtsi"
+
+/ {
+        model = "NVIDIA p3971-0000+p3701-0000";
+        compatible = "nvidia,p3971-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";
+
+};
diff --git a/nv-platform/tegra234-p3971-0000+p3701-0008-nv-safety.dts b/nv-platform/tegra234-p3971-0000+p3701-0008-nv-safety.dts
new file mode 100644
index 0000000..b31c9a8
--- /dev/null
+++ b/nv-platform/tegra234-p3971-0000+p3701-0008-nv-safety.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "tegra234-p3971-0000+p3701-0008-nv.dts"
+#include "tegra234-p3740-0002+p3701-0008-safety.dtsi"
+
+/ {
+	compatible = "nvidia,p3971-0000+p3701-0008", "safety", "nvidia,p3701-0008", "nvidia,tegra234";
+
+};
diff --git a/nv-platform/tegra234-p3971-0000+p3701-0008-nv.dts b/nv-platform/tegra234-p3971-0000+p3701-0008-nv.dts
new file mode 100644
index 0000000..cc5375d
--- /dev/null
+++ b/nv-platform/tegra234-p3971-0000+p3701-0008-nv.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+#include "../tegra234-p3701-0008.dtsi"
+#include "tegra234-p3701-0008.dtsi"
+#include "tegra234-p3971-0000+p3701-xxxx-nv-common.dtsi"
+
+/ {
+        model = "NVIDIA p3971-0000+p3701-0008";
+        compatible = "nvidia,p3971-0000+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234";
+
+};
diff --git a/nv-platform/tegra234-p3971-0000+p3701-xxxx-nv-common.dtsi b/nv-platform/tegra234-p3971-0000+p3701-xxxx-nv-common.dtsi
new file mode 100644
index 0000000..7f48114
--- /dev/null
+++ b/nv-platform/tegra234-p3971-0000+p3701-xxxx-nv-common.dtsi
@@ -0,0 +1,356 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "nv-soc/tegra234-overlay.dtsi"
+#include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
+#include "nv-soc/tegra234-soc-camera.dtsi"
+
+#include "tegra234-p3971-0000.dtsi"
+
+/ {
+	aliases {
+		serial0 = &tcu;
+		serial1 = &uarta;
+	};
+
+	serial {
+		status = "okay";
+	};
+
+	bus@0 {
+		mc-hwpm@2c10000 {
+			status = "okay";
+		};
+
+		serial@3100000 {
+			compatible = "nvidia,tegra194-hsuart";
+			reset-names = "serial";
+			status = "okay";
+		};
+
+		i2c@3160000 {
+			status = "okay";
+		};
+
+		i2c@3180000 {
+			status = "okay";
+		};
+
+		i2c@3190000 {
+			status = "okay";
+		};
+
+		i2c@31b0000 {
+			status = "okay";
+		};
+
+		i2c@31c0000 {
+			status = "okay";
+
+		};
+
+		i2c@31e0000 {
+			status = "okay";
+		};
+
+		padctl@3520000 {
+			status = "okay";
+
+			pads {
+				usb2 {
+					lanes {
+						usb2-0 {
+							status = "okay";
+						};
+
+						usb2-1 {
+							status = "okay";
+						};
+
+						usb2-2 {
+							status = "okay";
+						};
+
+						usb2-3 {
+							status = "okay";
+						};
+					};
+				};
+
+				usb3 {
+					lanes {
+						usb3-0 {
+							status = "okay";
+						};
+
+						usb3-1 {
+							status = "okay";
+						};
+
+						usb3-2 {
+							status = "okay";
+						};
+					};
+				};
+			};
+
+			ports {
+				usb2-0 {
+					mode = "otg";
+					vbus-supply = <&vdd_5v0_sys>;
+					usb-role-switch;
+					role-switch-default-mode = "peripheral";
+					status = "okay";
+				};
+
+				usb2-1 {
+					mode = "host";
+					vbus-supply = <&vdd_5v0_sys>;
+					status = "okay";
+				};
+
+				usb2-2 {
+					mode = "host";
+					vbus-supply = <&vdd_5v0_sys>;
+					status = "okay";
+				};
+
+				usb2-3 {
+					mode = "host";
+					vbus-supply = <&vdd_5v0_sys>;
+					status = "okay";
+				};
+
+				usb3-0 {
+					nvidia,usb2-companion = <0>;
+					status = "okay";
+				};
+
+				usb3-1 {
+					nvidia,usb2-companion = <3>;
+					status = "okay";
+				};
+
+				usb3-2 {
+					nvidia,usb2-companion = <1>;
+					status = "okay";
+				};
+			};
+		};
+
+		usb@3550000 {
+			status = "okay";
+			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+			     <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>;
+			phy-names = "usb2-0", "usb3-0";
+		};
+
+		usb@3610000 {
+			status = "okay";
+			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+			     <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
+			     <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
+			     <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
+			     <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
+			     <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>,
+			     <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
+			phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0", "usb3-1", "usb3-2";
+		};
+
+		hardware-timestamp@3aa0000 {
+			status = "okay";
+		};
+
+		hsp@3c00000 {
+			status = "okay";
+		};
+
+		hsp@c150000 {
+			status = "okay";
+		};
+
+		hardware-timestamp@c1e0000 {
+			status = "okay";
+		};
+
+		i2c@c240000 {
+			status = "okay";
+		};
+
+		i2c@c250000 {
+			status = "okay";
+		};
+
+		mttcan@c310000 {
+			status = "okay";
+		};
+
+		mttcan@c320000 {
+			status = "okay";
+		};
+
+		actmon@d230000 {
+			status = "okay";
+		};
+
+		hwpm@f100000 {
+			status = "okay";
+		};
+
+		host1x@13e00000 {
+			nvjpg@15380000 {
+				status = "okay";
+			};
+
+			nvdec@15480000 {
+				status = "okay";
+			};
+
+			nvenc@154c0000 {
+				status = "okay";
+			};
+
+			tsec@15500000 {
+				status = "okay";
+			};
+
+			nvjpg@15540000 {
+				status = "okay";
+			};
+
+			se@15810000 {
+				status = "okay";
+			};
+
+			se@15820000 {
+				status = "okay";
+			};
+
+			se@15840000 {
+				status = "okay";
+			};
+
+			nvdla0@15880000 {
+				status = "okay";
+			};
+
+			nvdla1@158c0000 {
+				status = "okay";
+			};
+
+			ofa@15a50000 {
+				status = "okay";
+			};
+
+			pva0@16000000 {
+				status = "okay";
+
+				pva0_niso1_ctx0 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx1 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx2 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx3 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx4 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx5 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx6 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx7 {
+					status = "okay";
+				};
+			};
+		};
+
+		gpu@17000000 {
+			status = "okay";
+		};
+	};
+
+	tegra-hsp@b950000 {
+		status = "okay";
+	};
+
+	dce@d800000 {
+		status = "okay";
+	};
+
+	tegra_mce@e100000 {
+		status = "okay";
+	};
+
+	display@13800000 {
+		status = "okay";
+	};
+
+	cpus {
+		idle-states {
+			c7 {
+				status = "okay";
+			};
+		};
+	};
+
+	nvpmodel {
+		status = "okay";
+	};
+
+	soctherm-oc-event {
+		status = "okay";
+	};
+
+	sound {
+		status = "okay";
+		compatible = "nvidia,tegra186-audio-graph-card",
+			   "nvidia,tegra186-ape";
+		clocks = <&bpmp TEGRA234_CLK_PLLA>,
+		       <&bpmp TEGRA234_CLK_PLLA_OUT0>,
+		       <&bpmp TEGRA234_CLK_AUD_MCLK>;
+		clock-names = "pll_a", "plla_out0", "extern1";
+		assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
+		assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+
+		nvidia-audio-card,name = "NVIDIA IGX500 Orin APE";
+
+		nvidia-audio-card,mclk-fs = <256>;
+
+		nvidia-audio-card,widgets =
+			"Headphone",    "CVB-RT Headphone Jack",
+			"Microphone",   "CVB-RT Mic Jack",
+			"Microphone",   "CVB-RT Int Mic";
+
+		nvidia-audio-card,routing =
+			"CVB-RT Headphone Jack",     "CVB-RT HPOL",
+			"CVB-RT Headphone Jack",     "CVB-RT HPOR",
+			"CVB-RT IN1P",               "CVB-RT Mic Jack",
+			"CVB-RT IN2P",               "CVB-RT Mic Jack",
+			"CVB-RT DMIC1",              "CVB-RT Int Mic",
+			"CVB-RT DMIC2",              "CVB-RT Int Mic";
+
+		/* I2S4 dai node */
+		nvidia-audio-card,dai-link@79 {
+			link-name = "rt5640-playback";
+			codec {
+				sound-dai = <&rt5640 0>;
+				prefix = "CVB-RT";
+			};
+		};
+	};
+};
diff --git a/nv-platform/tegra234-p3971-0000.dtsi b/nv-platform/tegra234-p3971-0000.dtsi
new file mode 100644
index 0000000..759a220
--- /dev/null
+++ b/nv-platform/tegra234-p3971-0000.dtsi
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include "tegra234-dcb-p3971-0000+p3701-0000.dtsi"
+#include <dt-bindings/sound/rt5640.h>
+
+/ {
+	bus@0 {
+		aconnect@2900000 {
+			ahub@2900800 {
+				i2s@2901300 {
+					ports {
+						port@1 {
+							endpoint {
+								dai-format = "i2s";
+								remote-endpoint = <&rt5640_ep>;
+							};
+						};
+					};
+				};
+			};
+		};
+
+		hda@3510000 {
+			nvidia,model = "NVIDIA IGX500 Orin HDA";
+			status = "okay";
+		};
+
+		i2c@3160000 {
+			status = "okay";
+
+			eeprom@56 {
+				compatible = "atmel,24c02";
+				reg = <0x56>;
+
+				label = "system";
+				vcc-supply = <&vdd_1v8_cvb>;
+				address-width = <8>;
+				pagesize = <8>;
+				size = <256>;
+				read-only;
+			};
+		};
+
+		i2c@31b0000 {
+			status = "okay";
+		};
+
+		host1x@13e00000 {
+			tsec@15500000 {
+				status = "okay";
+			};
+		};
+
+		i2c@31c0000 {
+			status = "okay";
+
+			rt5640: audio-codec@1c {
+				compatible = "realtek,rt5640";
+				reg = <0x1c>;
+
+				clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
+				clock-names = "mclk";
+
+				realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
+				realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
+				realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
+
+				/* Codec IRQ output */
+				interrupt-parent = <&gpio>;
+				interrupts = <TEGRA234_MAIN_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+
+				#sound-dai-cells = <1>;
+				sound-name-prefix = "CVB-RT";
+
+				status = "okay";
+
+				port {
+					rt5640_ep: endpoint {
+						remote-endpoint = <&i2s4_dap>;
+						mclk-fs = <256>;
+					};
+				};
+			};
+		};
+
+		/* SPI1 in 40 pin conn */
+		spi@3210000 {
+			status = "okay";
+			spi@0 { /* chip select 0 */
+				compatible = "tegra-spidev";
+				reg = <0x0>;
+				spi-max-frequency = <50000000>;
+			};
+
+			spi@1 { /* chips select 1 */
+				compatible = "tegra-spidev";
+				reg = <0x1>;
+				spi-max-frequency = <50000000>;
+			};
+		};
+
+		/* SPI3 is connected to Aurix */
+		spi@3230000 {
+			status = "disabled";
+		};
+
+		pwm@3280000 {
+			status = "okay";
+		};
+
+
+		pwm@32f0000 {
+			status = "okay";
+		};
+
+		/* Enable fan PWM */
+		pwm@32a0000 {
+			status = "okay";
+		};
+
+		/*
+		 * This is on 40-pin header (pin-18)
+		 * On Orin, the pad control configures it as GPIO/SDMMC.
+		 * No pwm support.
+		 */
+		pwm@32c0000 {
+			status = "disabled";
+		};
+
+		tachometer@39c0000 {
+			status = "okay";
+		};
+
+		pcie@14100000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_3v3_ao_cvb>;
+
+			phys = <&p2u_hsio_3>;
+			phy-names = "p2u-0";
+		};
+
+		pcie@14160000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_3v3_ao_cvb>;
+
+			phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+			     <&p2u_hsio_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+		};
+
+		pcie@141a0000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_3v3_ao_cvb>;
+
+			phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+			     <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+			     <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+				"p2u-5", "p2u-6", "p2u-7";
+		};
+
+		pcie@141e0000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_3v3_ao_cvb>;
+
+			phys = <&p2u_gbe_0>, <&p2u_gbe_1>, <&p2u_gbe_2>, <&p2u_gbe_3>,
+			     <&p2u_gbe_4>, <&p2u_gbe_5>, <&p2u_gbe_6>, <&p2u_gbe_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+				"p2u-5", "p2u-6", "p2u-7";
+		};
+
+		ufshci@2500000 {
+			status = "okay";
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyTCU0,115200n8";
+		stdout-path = "serial0:115200n8";
+	};
+
+        display@13800000 {
+                status = "okay";
+        };
+
+	eeprom-manager {
+		data-size = <0x100>;
+		bus@0 {
+			i2c-bus = <&gen1_i2c>;
+			eeprom@1 {
+				slave-address = <0x56>;
+				label = "cvb";
+			};
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		pwms = <&pwm3 0 45334>;
+		#cooling-cells = <2>;
+	};
+
+	/* fan_nvme is no-stuff, same PWM instance is routed to 40-pin header */
+	fan_nvme: pwm-fan-nvme {
+		compatible = "pwm-fan";
+		pwms = <&pwm8 0 45334>;
+		#cooling-cells = <2>;
+		status = "disabled";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		key-force-recovery {
+			label = "Force Recovery";
+			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <BTN_1>;
+		};
+
+		key-power {
+			label = "Power";
+			gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_POWER>;
+			wakeup-event-action = <EV_ACT_ASSERTED>;
+			wakeup-source;
+		};
+	};
+
+	vcc_src_20v_cvb: regulator-vcc-src-fet {
+		compatible = "regulator-fixed";
+		reg = <1>;
+		regulator-name = "VCC_SRC_FET";
+		regulator-min-microvolt = <20000000>;
+		regulator-max-microvolt = <20000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_5v_cvb: vdd_5v_ao_cvb: regulator-vdd-5v-ao {
+		compatible = "regulator-fixed";
+		reg = <2>;
+		regulator-name = "VDD_5V_AO";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
+	vdd_3v3_cbv: regulator-vdd-3v3 {
+		compatible = "regulator-fixed";
+		reg = <3>;
+		regulator-name = "VDD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vdd_3v3_ao_cvb: regulator-vdd-3v3-ao {
+		compatible = "regulator-fixed";
+		reg = <4>;
+		regulator-name = "VDD_3V3_AO";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	vdd_1v8_cvb: regulator-vdd-1v8 {
+		compatible = "regulator-fixed";
+		reg = <5>;
+		regulator-name = "VDD_1V8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vdd_12v_cvb: regulator-vdd-12v {
+		compatible = "regulator-fixed";
+		reg = <6>;
+		regulator-name = "VDD_12V";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
+		regulator-always-on;
+	};
+
+	vdd_3v3_dp_en: regulator-vdd-3v3-dp-en {
+		compatible = "regulator-fixed";
+		reg = <7>;
+		regulator-name = "VDD_3V3_DP_EN";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		enable-active-high;
+	};
+
+	sound {
+		status = "okay";
+
+		compatible = "nvidia,tegra186-audio-graph-card";
+
+		dais = /* ADMAIF (FE) Ports */
+		       <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
+		       <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
+		       <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
+		       <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
+		       <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
+		       /* XBAR Ports */
+		       <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>,
+		       <&xbar_i2s6_port>, <&xbar_dmic3_port>,
+		       <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
+		       <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
+		       <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
+		       <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
+		       <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
+		       <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
+		       <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
+		       <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
+		       <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
+		       <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
+		       <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
+		       <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
+		       <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
+		       <&xbar_mix_in1_port>, <&xbar_mix_in2_port>,
+		       <&xbar_mix_in3_port>, <&xbar_mix_in4_port>,
+		       <&xbar_mix_in5_port>, <&xbar_mix_in6_port>,
+		       <&xbar_mix_in7_port>, <&xbar_mix_in8_port>,
+		       <&xbar_mix_in9_port>, <&xbar_mix_in10_port>,
+		       <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
+		       <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
+		       <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
+		       <&xbar_asrc_in7_port>,
+		       <&xbar_ope1_in_port>,
+		       /* HW accelerators */
+		       <&sfc1_out_port>, <&sfc2_out_port>,
+		       <&sfc3_out_port>, <&sfc4_out_port>,
+		       <&mvc1_out_port>, <&mvc2_out_port>,
+		       <&amx1_out_port>, <&amx2_out_port>,
+		       <&amx3_out_port>, <&amx4_out_port>,
+		       <&adx1_out1_port>, <&adx1_out2_port>,
+		       <&adx1_out3_port>, <&adx1_out4_port>,
+		       <&adx2_out1_port>, <&adx2_out2_port>,
+		       <&adx2_out3_port>, <&adx2_out4_port>,
+		       <&adx3_out1_port>, <&adx3_out2_port>,
+		       <&adx3_out3_port>, <&adx3_out4_port>,
+		       <&adx4_out1_port>, <&adx4_out2_port>,
+		       <&adx4_out3_port>, <&adx4_out4_port>,
+		       <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>,
+		       <&mix_out4_port>, <&mix_out5_port>,
+		       <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
+		       <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+		       <&ope1_out_port>,
+		       /* BE I/O Ports */
+		       <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
+		       <&dmic3_port>;
+
+		label = "NVIDIA IGX500 Orin APE";
+
+		widgets = "Microphone",	"CVB-RT MIC Jack",
+			  "Microphone",	"CVB-RT MIC",
+			  "Headphone",	"CVB-RT HP Jack",
+			  "Speaker",	"CVB-RT SPK";
+
+		routing = /* I2S4 <-> RT5640 */
+			  "CVB-RT AIF1 Playback",	"I2S4 DAP-Playback",
+			  "I2S4 DAP-Capture",		"CVB-RT AIF1 Capture",
+			  /* RT5640 codec controls */
+			  "CVB-RT HP Jack",		"CVB-RT HPOL",
+			  "CVB-RT HP Jack",		"CVB-RT HPOR",
+			  "CVB-RT IN1P",		"CVB-RT MIC Jack",
+			  "CVB-RT IN2P",		"CVB-RT MIC Jack",
+			  "CVB-RT IN2N",		"CVB-RT MIC Jack",
+			  "CVB-RT IN3P",		"CVB-RT MIC Jack",
+			  "CVB-RT SPK",			"CVB-RT SPOLP",
+			  "CVB-RT SPK",			"CVB-RT SPORP",
+			  "CVB-RT SPK",			"CVB-RT LOUTL",
+			  "CVB-RT SPK",			"CVB-RT LOUTR",
+			  "CVB-RT DMIC1",		"CVB-RT MIC",
+			  "CVB-RT DMIC2",		"CVB-RT MIC";
+	};
+};
diff --git a/overlay/Makefile b/overlay/Makefile
index 33aaf51..90e8f81 100644
--- a/overlay/Makefile
+++ b/overlay/Makefile
@@ -44,6 +44,8 @@ dtbo-y += tegra234-p3767-0000+p3509-a02-csi.dtbo
 dtbo-y += tegra234-p3767-0000+p3509-a02-hdr40.dtbo
 dtbo-y += tegra234-p3767-0000+p3509-a02-m2ke.dtbo
 dtbo-y += tegra234-p3767-0000+p3768-0000-csi.dtbo
+dtbo-y += tegra234-p3971-0000+p3701-0008-camera-dual-imx274-overlay.dtbo
+dtbo-y += tegra234-p3971-0000+p3701-0008-camera-p3762-a00-overlay.dtbo
 dtbo-y += tegra234-p3737-camera-dual-imx274-overlay.dtbo
 dtbo-y += tegra234-p3737-camera-e3331-overlay.dtbo
 dtbo-y += tegra234-p3737-camera-e3333-overlay.dtbo
diff --git a/overlay/tegra234-p3971-0000+p3701-0008-camera-dual-imx274-overlay.dts b/overlay/tegra234-p3971-0000+p3701-0008-camera-dual-imx274-overlay.dts
new file mode 100644
index 0000000..b01bf64
--- /dev/null
+++ b/overlay/tegra234-p3971-0000+p3701-0008-camera-dual-imx274-overlay.dts
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+/*
+ * Jetson Device-tree overlay for Camera Dual-IMX274 on t23x + p3971 platforms
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "dt-bindings/gpio/tegra234-gpio.h"
+#include "dt-bindings/clock/tegra234-clock.h"
+#include "tegra234-p3971-0000-camera-imx274-dual.dtsi"
+
+
+/ {
+	overlay-name = "Jetson Camera Dual-IMX274";
+	jetson-header-name = "Jetson AGX CSI Connector";
+	compatible = "nvidia,p3971-0000+p3701-0008";
+
+	fragment@0 {
+		target-path = "/bus@0/i2c@3180000/tca9546@70/i2c@0/imx274_a@1a";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@1 {
+		target-path = "/bus@0/i2c@3180000/tca9546@70/i2c@0/imx274_a@1a/ports/port@0/endpoint";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			remote-endpoint = <&liimx274_csi_in0>;
+		};
+	};
+	fragment@2 {
+		target-path = "/tegra-camera-platform/modules/module0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			badge = "imx274_bottom_A6V26";
+			position = "bottom";
+			orientation = "0";
+		};
+	};
+	fragment@3 {
+		target-path = "/tegra-camera-platform/modules/module0/drivernode0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			pcl_id = "v4l2_sensor";
+			sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9546@70/i2c@0/imx274_a@1a";
+		};
+	};
+	fragment@4 {
+		target-path = "/tegra-camera-platform/modules/module0/drivernode1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			pcl_id = "v4l2_lens";
+			sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/lens_imx274@A6V26/";
+		};
+	};
+	fragment@5 {
+		target-path = "/bus@0/i2c@3180000/tca9546@70/i2c@1/imx274_c@1a";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@6 {
+		target-path = "/bus@0/i2c@3180000/tca9546@70/i2c@1/imx274_c@1a/ports/port@0/endpoint";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			remote-endpoint = <&liimx274_csi_in1>;
+		};
+	};
+	fragment@7 {
+		target-path = "/tegra-camera-platform/modules/module1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			badge = "imx274_top_A6V26";
+			position = "top";
+			orientation = "0";
+		};
+	};
+	fragment@8 {
+		target-path = "/tegra-camera-platform/modules/module1/drivernode0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			pcl_id = "v4l2_sensor";
+			sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9546@70/i2c@1/imx274_c@1a";
+		};
+	};
+	fragment@9 {
+		target-path = "/tegra-camera-platform/modules/module1/drivernode1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			pcl_id = "v4l2_lens";
+			sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/lens_imx274@A6V26/";
+		};
+	};
+	/* Enable VI ports - capture_vi_base, */
+	fragment@10 {
+		target-path = "/tegra-capture-vi";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			num-channels=<2>;
+		};
+	};
+	fragment@11 {
+		target-path = "/tegra-capture-vi/ports/port@0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@12 {
+		target-path = "/tegra-capture-vi/ports/port@1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@13 {
+		target-path = "/tegra-capture-vi/ports/port@0/endpoint";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			port-index = <0>;
+			bus-width = <4>;
+			remote-endpoint = <&liimx274_csi_out0>;
+
+		};
+	};
+	fragment@14 {
+		target-path = "/tegra-capture-vi/ports/port@1/endpoint";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			port-index = <2>;
+			bus-width = <4>;
+			remote-endpoint = <&liimx274_csi_out1>;
+		};
+	};
+	/* Enable CSI ports */
+	fragment@15 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			num-channels=<2>;
+		};
+	};
+	fragment@16 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@17 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@0/ports/port@0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@18 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@0/ports/port@0/endpoint@0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			port-index = <0>;
+			bus-width = <4>;
+			remote-endpoint = <&liimx274_imx274_out0>;
+		};
+	};
+	fragment@19 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@0/ports/port@1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@20 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@0/ports/port@1/endpoint@1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			remote-endpoint = <&liimx274_vi_in0>;
+		};
+	};
+	fragment@21 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@22 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@1/ports/port@0";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@23 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@1/ports/port@0/endpoint@2";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			port-index = <2>;
+			bus-width = <4>;
+			remote-endpoint = <&liimx274_imx274_out1>;
+		};
+	};
+	fragment@24 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@1/ports/port@1";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+	fragment@25 {
+		target-path = "/bus@0/host1x@13e00000/nvcsi@15a00000/channel@1/ports/port@1/endpoint@3";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+			remote-endpoint = <&liimx274_vi_in1>;
+		};
+	};
+	/* tegra-camera-platform settings */
+	fragment@26 {
+		target-path = "/tegra-camera-platform";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			num_csi_lanes = <8>;
+			max_lane_speed = <1500000>;
+			min_bits_per_pixel = <10>;
+			vi_peak_byte_per_pixel = <2>;
+			vi_bw_margin_pct = <25>;
+			isp_peak_byte_per_pixel = <5>;
+			isp_bw_margin_pct = <25>;
+		};
+	};
+	/* pca9646 i2c mux */
+	fragment@27 {
+		target-path = "/bus@0/i2c@3180000/tca9546@70";
+		board_config {
+			ids = "LPRD-dual-imx274-002";
+			sw-modules = "kernel";
+		};
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+};
diff --git a/overlay/tegra234-p3971-0000+p3701-0008-camera-p3762-a00-overlay.dts b/overlay/tegra234-p3971-0000+p3701-0008-camera-p3762-a00-overlay.dts
new file mode 100644
index 0000000..605e2f0
--- /dev/null
+++ b/overlay/tegra234-p3971-0000+p3701-0008-camera-p3762-a00-overlay.dts
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+/dts-v1/;
+/plugin/;
+
+#include "dt-bindings/gpio/tegra234-gpio.h"
+#include "dt-bindings/clock/tegra234-clock.h"
+#include "tegra234-camera-p3762-a00.dtsi"
+
+/* camera control gpio definitions */
+#define CAM0_RST_L      TEGRA234_MAIN_GPIO(H, 3)
+#define CAM0_PWDN       TEGRA234_MAIN_GPIO(E, 6)
+#define CAM1_RST_L      TEGRA234_MAIN_GPIO(AC, 1)
+#define CAM1_PWDN       TEGRA234_MAIN_GPIO(AC, 0)
+#define PWR_EN      	TEGRA234_MAIN_GPIO(AC, 7)
+#define GYRO1_IRQ_GPIO  TEGRA234_AON_GPIO(CC, 1)
+#define ACCE1_IRQ_GPIO  TEGRA234_AON_GPIO(CC, 0)
+
+/ {
+	overlay-name = "Jetson Camera Hawk-Owl p3762 module";
+	jetson-header-name = "Jetson AGX CSI Connector";
+	compatible = "nvidia,p3971-0000+p3701-0008";
+
+	fragment-camera-hawk-owl@0 {
+		target-path = "/";
+		__overlay__ {
+			bus@0 {
+				/* set camera gpio direction to output */
+				gpio@2200000 {
+					camera-control-output-low {
+						gpio-hog;
+						output-low;
+						gpios = <CAM0_RST_L 0 CAM0_PWDN 0
+								CAM1_RST_L 0 CAM1_PWDN 0>;
+						label = "cam0-rst", "cam0-pwdn",
+								"cam1-rst", "cam1-pwdn";
+					};
+				};
+				i2c@3180000 {
+					max96712_b@62 {
+						compatible = "nvidia,max96712";
+						reg = <0x62>;
+						channel = "b";
+						pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
+						status = "okay";
+					};
+					ar0234_i@30 {
+						status = "okay";
+						def-addr = <0x18>;
+						/* Define any required hw resources needed by driver */
+						/* ie. clocks, io pins, power sources */
+						clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+								<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+						clock-names = "extperiph1", "pllp_grtba";
+						mclk = "extperiph1";
+						channel = "b";
+						has-eeprom;
+						eeprom-addr = <0x38>;
+						reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
+						pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
+						pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+					};
+					ar0234_j@32 {
+						status = "okay";
+						def-addr = <0x18>;
+						/* Define any required hw resources needed by driver */
+						/* ie. clocks, io pins, power sources */
+						clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+								<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+						clock-names = "extperiph1", "pllp_grtba";
+						mclk = "extperiph1";
+						channel = "b";
+						has-eeprom;
+						eeprom-addr = <0x3a>;
+						reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
+						pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
+						pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+					};
+					ar0234_k@34 {
+						status = "okay";
+						def-addr = <0x18>;
+						/* Define any required hw resources needed by driver */
+						/* ie. clocks, io pins, power sources */
+						clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+								<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+						clock-names = "extperiph1", "pllp_grtba";
+						mclk = "extperiph1";
+						channel = "b";
+						has-eeprom;
+						eeprom-addr = <0x3c>;
+						reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
+						pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
+						pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+					};
+					ar0234_l@36 {
+						status = "okay";
+						def-addr = <0x18>;
+						/* Define any required hw resources needed by driver */
+						/* ie. clocks, io pins, power sources */
+						clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+								<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+						clock-names = "extperiph1", "pllp_grtba";
+						mclk = "extperiph1";
+						channel = "b";
+						has-eeprom;
+						eeprom-addr = <0x3e>;
+						reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
+						pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
+						pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+					};
+				};
+				i2c@31e0000 {
+					max96712_a@62 {
+						compatible = "nvidia,max96712";
+						reg = <0x62>;
+						channel = "a";
+						pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+						status = "okay";
+					};
+					virtual_i2c_mux@50 {
+						reg = <0x50>;
+						compatible = "nvidia,virtual-i2c-mux";
+						#address-cells = <1>;
+						#size-cells = <0>;
+						i2c-parent = <&dp_aux_ch3_i2c>;
+						status = "okay";
+
+						i2c@0 {
+							reg = <0>;
+							i2c-mux,deselect-on-exit;
+							#address-cells = <1>;
+							#size-cells = <0>;
+
+							bmi088_a@69 {
+								compatible = "bmi,bmi088";
+								reg = <0x69>;
+								accel_i2c_addr = <0x19>;
+								/* Old BMI088 driver uses *_gpio property and the latest
+								 * BMI088 driver uses *-gpios property. Have both versions
+								 * to maintain backward compatibility.
+								 */
+								accel_irq_gpio = <&gpio_aon ACCE1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
+								gyro_irq_gpio = <&gpio_aon GYRO1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
+								accel_irq-gpios = <&gpio_aon ACCE1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
+								gyro_irq-gpios = <&gpio_aon GYRO1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
+								accel_matrix = [01 00 00 00 01 00 00 00 01];
+								gyro_matrix = [01 00 00 00 01 00 00 00 01];
+								gyro_reg_0x18 = <0x81>;
+								timestamps = <&hte_aon ACCE1_IRQ_GPIO>, <&hte_aon GYRO1_IRQ_GPIO>;
+								timestamp-names = "accelerometer", "gyroscope";
+								status = "okay";
+							};
+							ar0234_a@30 {
+								status = "okay";
+								def-addr = <0x10>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x40>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+							ar0234_b@31 {
+								status = "okay";
+								def-addr = <0x18>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x40>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+						};
+						i2c@1 {
+							reg = <1>;
+							i2c-mux,deselect-on-exit;
+							#address-cells = <1>;
+							#size-cells = <0>;
+							ar0234_c@32 {
+								status = "okay";
+								def-addr = <0x10>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x15>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+							ar0234_d@33 {
+								status = "okay";
+								def-addr = <0x18>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x15>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+							ar0234_e@34 {
+								status = "okay";
+								def-addr = <0x10>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x44>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+							ar0234_f@35 {
+								status = "okay";
+								def-addr = <0x18>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x44>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+							ar0234_g@36 {
+								status = "okay";
+								def-addr = <0x10>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x46>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+							ar0234_h@37 {
+								status = "okay";
+								def-addr = <0x18>;
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
+								clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+										<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+								clock-names = "extperiph1", "pllp_grtba";
+								mclk = "extperiph1";
+								channel = "a";
+								has-eeprom;
+								eeprom-addr = <0x46>;
+								reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+								pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+								pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
+							};
+						};
+					};
+				};
+			};
+		};
+	};
+	fragment-cam-cdi-tsc@0 {
+		target-path = "/";
+		__overlay__ {
+			tsc_sig_gen@c6a0000 {
+				status = "okay";
+				generator@380 {
+					status = "okay";
+				};
+			};
+		};
+	};
+};
diff --git a/overlay/tegra234-p3971-0000-camera-imx274-dual.dtsi b/overlay/tegra234-p3971-0000-camera-imx274-dual.dtsi
new file mode 100644
index 0000000..73ce072
--- /dev/null
+++ b/overlay/tegra234-p3971-0000-camera-imx274-dual.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+#include <dt-bindings/clock/tegra234-clock.h>
+#include <dt-bindings/gpio/tegra234-gpio.h>
+#include "tegra234-camera-imx274-dual.dtsi"
+
+#define CAM0_RST_L	TEGRA234_MAIN_GPIO(H, 3)
+#define CAM0_PWDN	TEGRA234_MAIN_GPIO(E, 6)
+
+/* camera control gpio definitions */
+/ {
+	fragment-camera-dual-imx274@0 {
+		target-path = "/bus@0";
+		__overlay__ {
+			gpio@2200000 {
+				camera-control-output-low {
+					gpio-hog;
+					output-low;
+					gpios = <CAM0_RST_L GPIO_ACTIVE_HIGH CAM0_PWDN GPIO_ACTIVE_HIGH>;
+					label = "cam0-rst", "cam0-pwdn";
+				};
+			};
+			i2c@3180000 {
+				tca9546@70 {
+					compatible = "nxp,pca9546";
+					reg = <0x70>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					skip_mux_detect = "yes";
+					vcc-supply = <&vdd_1v8_ls>;
+					i2c@0 {
+						reg = <0>;
+						i2c-mux,deselect-on-exit;
+						#address-cells = <1>;
+						#size-cells = <0>;
+						imx274_a@1a {
+							/* Define any required hw resources needed by driver */
+							/* ie. clocks, io pins, power sources */
+							clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+									<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+							clock-names = "extperiph1", "pllp_grtba";
+							mclk = "extperiph1";
+							reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
+						};
+					};
+					i2c@1 {
+						reg = <1>;
+						i2c-mux,deselect-on-exit;
+						#address-cells = <1>;
+						#size-cells = <0>;
+						imx274_c@1a {
+							/* Define any required hw resources needed by driver */
+							/* ie. clocks, io pins, power sources */
+							clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+									<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+							clock-names = "extperiph1", "pllp_grtba";
+							mclk = "extperiph1";
+							reset-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
+						};
+					};
+				};
+			};
+		};
+	};
+};