From 1dd7612d8ac9cb48ab47cf6c48c80ea53ee0402d Mon Sep 17 00:00:00 2001 From: Vishwaroop A Date: Wed, 2 Oct 2024 16:40:28 +0000 Subject: [PATCH] dts: qspi: update parent clock and bus width Add assigned clock parent and rate properties in device tree for qspi and update the p3701 bus width for qspi to 4 instead of 1. Bug 4739710 Bug 4535595 Change-Id: I32cdc917af9ed6c4bbeb94e27d8b007ba704ca8b Signed-off-by: Vishwaroop A Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3174161 GVS: buildbot_gerritrpt Reviewed-by: Bitan Biswas Reviewed-by: svcacv --- nv-platform/tegra234-p3701-0000.dtsi | 10 ---------- nv-soc/tegra234-base-overlay.dtsi | 4 ++++ 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/nv-platform/tegra234-p3701-0000.dtsi b/nv-platform/tegra234-p3701-0000.dtsi index 6ab9abf..86e785e 100644 --- a/nv-platform/tegra234-p3701-0000.dtsi +++ b/nv-platform/tegra234-p3701-0000.dtsi @@ -4,16 +4,6 @@ #include "tegra234-p3701-0000-prod-overlay.dtsi" / { - bus@0 { - spi@3270000 { - flash@0 { - spi-max-frequency = <51000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - }; - }; - }; - bpmp { i2c { vrs@3c { diff --git a/nv-soc/tegra234-base-overlay.dtsi b/nv-soc/tegra234-base-overlay.dtsi index bd32c8e..560a7f1 100644 --- a/nv-soc/tegra234-base-overlay.dtsi +++ b/nv-soc/tegra234-base-overlay.dtsi @@ -440,6 +440,10 @@ dma-names = "rx", "tx"; dma-coherent; iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>; + assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, + <&bpmp TEGRA234_CLK_QSPI0_PM>; + assigned-clock-rates = <199999999 99999999>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; }; hardware-timestamp@3aa0000 {