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t234: soc: add missing cells parms to intc

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DTB spec says:
"A DTSpec-compliant boot program shall supply #address-cells and
 #size-cells on all nodes that have children"

This adds the required cells to the interrupt-controller node.

It also fixes up pcie interrupt-map values to
use the correct number of #address-cells. They
appeared to be using 0 before.

JIRA TEGRAUEFI-3252

Signed-off-by: Jeshua Smith <jeshuas@nvidia.com>
ChangeId: Iaa30ab7a1612aa8927a6de239fb201c66049ab0f
Change-Id: Iaa30ab7a1612aa8927a6de239fb201c66049ab0f
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3231095
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Jeshua Smith
2024-10-08 17:55:54 +00:00
committed by mobile promotions
parent 0c0a471654
commit 1df507ec3f
1 changed files with 16 additions and 0 deletions
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16
nv-soc/tegra234-base-overlay.dtsi
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@@ -57,47 +57,63 @@
"wake4", "wake5", "wake6"; "wake4", "wake5", "wake6";
}; };
gic: interrupt-controller@f400000 {
#address-cells = <2>;
#size-cells = <2>;
};
pcie@140a0000 { pcie@140a0000 {
interrupt-map = <0 0 0 0 &gic 0 0 GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_niso1 TEGRA234_SID_PCIE8>; iommus = <&smmu_niso1 TEGRA234_SID_PCIE8>;
}; };
pcie@140c0000 { pcie@140c0000 {
interrupt-map = <0 0 0 0 &gic 0 0 GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_niso0 TEGRA234_SID_PCIE9>; iommus = <&smmu_niso0 TEGRA234_SID_PCIE9>;
}; };
pcie@140e0000 { pcie@140e0000 {
interrupt-map = <0 0 0 0 &gic 0 0 GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_niso1 TEGRA234_SID_PCIE10>; iommus = <&smmu_niso1 TEGRA234_SID_PCIE10>;
}; };
pcie@14100000 { pcie@14100000 {
interrupt-map = <0 0 0 0 &gic 0 0 GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_niso1 TEGRA234_SID_PCIE1>; iommus = <&smmu_niso1 TEGRA234_SID_PCIE1>;
}; };
pcie@14120000 { pcie@14120000 {
interrupt-map = <0 0 0 0 &gic 0 0 GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_niso1 TEGRA234_SID_PCIE2>; iommus = <&smmu_niso1 TEGRA234_SID_PCIE2>;
}; };
pcie@14140000 { pcie@14140000 {
interrupt-map = <0 0 0 0 &gic 0 0 GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_niso1 TEGRA234_SID_PCIE3>; iommus = <&smmu_niso1 TEGRA234_SID_PCIE3>;
}; };
pcie@14160000 { pcie@14160000 {
interrupt-map = <0 0 0 0 &gic 0 0 GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>; iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>;
}; };
pcie@14180000 { pcie@14180000 {
interrupt-map = <0 0 0 0 &gic 0 0 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_niso0 TEGRA234_SID_PCIE0>; iommus = <&smmu_niso0 TEGRA234_SID_PCIE0>;
}; };
pcie@141a0000 { pcie@141a0000 {
interrupt-map = <0 0 0 0 &gic 0 0 GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_niso0 TEGRA234_SID_PCIE5>; iommus = <&smmu_niso0 TEGRA234_SID_PCIE5>;
}; };
pcie@141c0000 { pcie@141c0000 {
interrupt-map = <0 0 0 0 &gic 0 0 GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_niso0 TEGRA234_SID_PCIE6>; iommus = <&smmu_niso0 TEGRA234_SID_PCIE6>;
}; };
pcie@141e0000 { pcie@141e0000 {
interrupt-map = <0 0 0 0 &gic 0 0 GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&smmu_niso1 TEGRA234_SID_PCIE7>; iommus = <&smmu_niso1 TEGRA234_SID_PCIE7>;
}; };