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t234: overlay: add interconnect property to gpu

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Add interconnects property with NVLINK MC client ID and
path info to the node representing NVGPU.

Bug 3997304

Signed-off-by: Johnny Liu <johnliu@nvidia.com>
Change-Id: I17ac18fdd6149720369f207c2336d96989f226a6
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2941869
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sumit Gupta <sumitg@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Johnny Liu
2023-07-25 05:16:25 +00:00
committed by mobile promotions
parent c306a04573
commit 2f86965a1a
2 changed files with 6 additions and 0 deletions
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3
overlay/tegra234-jetson.dts
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@@ -257,6 +257,9 @@
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall0", "stall1", "stall2", "nonstall"; interrupt-names = "stall0", "stall1", "stall2", "nonstall";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_GPU>; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_GPU>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVL1R &emc>,
<&mc TEGRA234_MEMORY_CLIENT_NVL1W &emc>;
interconnect-names = "dma-mem", "write";
clocks = <&bpmp TEGRA234_CLK_GPUSYS>, clocks = <&bpmp TEGRA234_CLK_GPUSYS>,
<&bpmp TEGRA234_CLK_GPC0CLK>, <&bpmp TEGRA234_CLK_GPC0CLK>,
<&bpmp TEGRA234_CLK_GPC1CLK>; <&bpmp TEGRA234_CLK_GPC1CLK>;

3
overlay/tegra234-soc-overlay.dtsi
View File

@@ -244,6 +244,9 @@
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall0", "stall1", "stall2", "nonstall"; interrupt-names = "stall0", "stall1", "stall2", "nonstall";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_GPU>; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_GPU>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVL1R &emc>,
<&mc TEGRA234_MEMORY_CLIENT_NVL1W &emc>;
interconnect-names = "dma-mem", "write";
clocks = <&bpmp TEGRA234_CLK_GPUSYS>, clocks = <&bpmp TEGRA234_CLK_GPUSYS>,
<&bpmp TEGRA234_CLK_GPC0CLK>, <&bpmp TEGRA234_CLK_GPC0CLK>,
<&bpmp TEGRA234_CLK_GPC1CLK>; <&bpmp TEGRA234_CLK_GPC1CLK>;