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t23x: overlay: display pin state for i2c and uart

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In Jetson-IO, I2C and UART pins are configured by default,
and there is no option to disable or display them as enabled.
By adding the appropriate "nvidia,function" value, Jetson-IO
updates the "Configure header pins manually" section to show
the pin state, allowing the user to enable or disable these pins.

Also, add the input and tristate values so that the pin can be
enabled back to the right configuration.

Bug 3866629

Change-Id: I2c01ac7355259e4a3e0a10905699b5dfbbbaf177
Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3219025
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Sheetal . <sheetal@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Gautham Srinivasan
2024-09-25 21:35:45 +00:00
committed by mobile promotions
parent 354519a4a5
commit 332e56ee15
2 changed files with 38 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
overlay/tegra234-p3737-0000+p3701-0000-hdr40.dts
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2021-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/* /*
* Device-tree overlay for tegra234-p3737-0000-p3701-0000 40-pin * Device-tree overlay for tegra234-p3737-0000-p3701-0000 40-pin
* Expansion Header. * Expansion Header.
@@ -30,9 +30,15 @@
}; };
hdr40-pin8 { hdr40-pin8 {
nvidia,pins = "uart1_tx_pr2"; nvidia,pins = "uart1_tx_pr2";
nvidia,function = "uarta";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
}; };
hdr40-pin10 { hdr40-pin10 {
nvidia,pins = "uart1_rx_pr3"; nvidia,pins = "uart1_rx_pr3";
nvidia,function = "uarta";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
}; };
hdr40-pin11 { hdr40-pin11 {
nvidia,pins = "uart1_rts_pr4"; nvidia,pins = "uart1_rts_pr4";
@@ -145,10 +151,16 @@
hdr40-pin3 { hdr40-pin3 {
nvidia,pins = "gen8_i2c_scl_pdd1"; nvidia,pins = "gen8_i2c_scl_pdd1";
nvidia,pin-label = "i2c8"; nvidia,pin-label = "i2c8";
nvidia,function = "i2c8";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
}; };
hdr40-pin5 { hdr40-pin5 {
nvidia,pins = "gen8_i2c_sda_pdd2"; nvidia,pins = "gen8_i2c_sda_pdd2";
nvidia,pin-label = "i2c8"; nvidia,pin-label = "i2c8";
nvidia,function = "i2c8";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
}; };
hdr40-pin16a { hdr40-pin16a {
nvidia,pins = "can1_en_pbb1"; nvidia,pins = "can1_en_pbb1";
@@ -166,9 +178,15 @@
}; };
hdr40-pin27 { hdr40-pin27 {
nvidia,pins = "gen2_i2c_sda_pdd0"; nvidia,pins = "gen2_i2c_sda_pdd0";
nvidia,function = "i2c2";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
}; };
hdr40-pin28 { hdr40-pin28 {
nvidia,pins = "gen2_i2c_scl_pcc7"; nvidia,pins = "gen2_i2c_scl_pcc7";
nvidia,function = "i2c2";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
}; };
hdr40-pin29 { hdr40-pin29 {
nvidia,pins = "can0_din_paa1"; nvidia,pins = "can0_din_paa1";

20
overlay/tegra234-p3767-0000-common-hdr40.dtsi
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2021-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/* /*
* Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* *
@@ -36,9 +36,15 @@
}; };
hdr40-pin8 { hdr40-pin8 {
nvidia,pins = "uart1_tx_pr2"; nvidia,pins = "uart1_tx_pr2";
nvidia,function = "uarta";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
}; };
hdr40-pin10 { hdr40-pin10 {
nvidia,pins = "uart1_rx_pr3"; nvidia,pins = "uart1_rx_pr3";
nvidia,function = "uarta";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
}; };
hdr40-pin11 { hdr40-pin11 {
nvidia,pins = "uart1_rts_pr4"; nvidia,pins = "uart1_rts_pr4";
@@ -206,16 +212,28 @@
hdr40-pin3 { hdr40-pin3 {
nvidia,pins = "gen8_i2c_sda_pdd2"; nvidia,pins = "gen8_i2c_sda_pdd2";
nvidia,pin-label = "i2c8"; nvidia,pin-label = "i2c8";
nvidia,function = "i2c8";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
}; };
hdr40-pin5 { hdr40-pin5 {
nvidia,pins = "gen8_i2c_scl_pdd1"; nvidia,pins = "gen8_i2c_scl_pdd1";
nvidia,pin-label = "i2c8"; nvidia,pin-label = "i2c8";
nvidia,function = "i2c8";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
}; };
hdr40-pin27 { hdr40-pin27 {
nvidia,pins = "gen2_i2c_sda_pdd0"; nvidia,pins = "gen2_i2c_sda_pdd0";
nvidia,function = "i2c2";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
}; };
hdr40-pin28 { hdr40-pin28 {
nvidia,pins = "gen2_i2c_scl_pcc7"; nvidia,pins = "gen2_i2c_scl_pcc7";
nvidia,function = "i2c2";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
}; };
}; };
}; };