nv-tegra-mirror/t23x-public-dts
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git synced 2025-12-22 17:30:17 +03:00
Code Issues Packages Projects Releases Wiki Activity

overlay: p3768: Reduce pcie link speed for Orin Nano

Browse Source 
Orin Nano SKUs (3, 4, 5) have a POR to support PCIe Gen3. By default,
all Orin SKUs support PCIe Gen4. Add overlay to update link speed to
Gen3 for Orin Nano SKUs.

Bug 3998955

Change-Id: I2fcd6ff930dd31251b8023f4a15abf5cea2a1c80
Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2918315
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Gautham Srinivasan
2023-06-09 02:07:45 +00:00
committed by mobile promotions
parent 6c91a6b646
commit 36d06e7082
1 changed files with 39 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
overlay/tegra234-p3767-sku-handling.dtsi
View File

@@ -61,4 +61,43 @@
};
};
};
/* For Orin Nano SKUs, reduce PCIe speed to Gen3 */
p3767-sku-handling-fragment@5 {
target-path = "/bus@0";
board_config {
ids = "3767-0003-*", "3767-0004-*", "3767-0005-*";
};
__overlay__ {
/* C1 */
pcie@14100000 {
max-link-speed = <0x3>;
};
/* C4 */
pcie@14160000 {
max-link-speed = <0x3>;
};
/* C4 End Point */
pcie_ep@14160000 {
max-link-speed = <0x3>;
};
/* C7 */
pcie@141e0000 {
max-link-speed = <0x3>;
};
/* C8 */
pcie@140a0000 {
max-link-speed = <0x3>;
};
/* C9 */
pcie@140c0000 {
max-link-speed = <0x3>;
};
};
};
};