mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
t23x: overlay: Remove legacy Sidecar overlay
The overlay tegra234-jetson.dtbo was added for Sidecar and is no longer needed or used and so remove this. Bug 4164621 Change-Id: I2dc56d69ac4320c4dae1379445367b2d6dee7e1f Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3130861 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
This commit is contained in:
Jon Hunter
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39a40385a8
@@ -14,7 +14,6 @@ dtbo-y += tegra234-android.dtbo
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dtbo-y += tegra234-audio-overlay.dtbo
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dtbo-y += tegra234-carveouts.dtbo
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dtbo-y += tegra234-dcb-p3767-0000-hdmi.dtbo
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dtbo-y += tegra234-jetson.dtbo
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dtbo-y += tegra234-p3737-0000+p3701-0000-pcie-no-tra.dtbo
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dtbo-y += tegra234-p3737-0000+p3701-0000-as-p3701-0004.dtbo
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dtbo-y += tegra234-p3737-0000+p3701-0000-as-p3767-0000.dtbo
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@@ -1,481 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/clock/tegra234-clock.h>
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#include <dt-bindings/gpio/tegra234-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/memory/tegra234-mc.h>
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#include <dt-bindings/power/tegra234-powergate.h>
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#include <dt-bindings/reset/tegra234-reset.h>
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/ {
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overlay-name = "Tegra234 Jetson Overlay";
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compatible = "nvidia,tegra234";
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fragment@0 {
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target-path = "/bus@0/host1x@13e00000";
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__overlay__ {
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#address-cells = <2>;
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#size-cells = <2>;
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reg = <0x0 0x13e00000 0x0 0x10000>,
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<0x0 0x13e10000 0x0 0x10000>,
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<0x0 0x13e40000 0x0 0x10000>,
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<0x0 0x13ef0000 0x0 0x60000>;
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reg-names = "common", "hypervisor", "vm", "actmon";
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clocks = <&bpmp TEGRA234_CLK_HOST1X>,
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<&bpmp TEGRA234_CLK_ACTMON>;
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clock-names = "host1x", "actmon";
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interrupt-parent = <&gic>;
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ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>,
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<0x0 0x24700000 0x0 0x24700000 0x0 0x00080000>;
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nvjpg@15380000 {
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compatible = "nvidia,tegra234-nvjpg";
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reg = <0x0 0x15380000 0x0 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_NVJPG>;
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clock-names = "nvjpg";
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resets = <&bpmp TEGRA234_RESET_NVJPG>;
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reset-names = "nvjpg";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVJPGA>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVJPGSRD &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVJPGSWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso1 TEGRA234_SID_NVJPG>;
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dma-coherent;
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nvidia,host1x-class = <0xc0>;
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};
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nvdec@15480000 {
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compatible = "nvidia,tegra234-nvdec";
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reg = <0x0 0x15480000 0x0 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_NVDEC>,
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<&bpmp TEGRA234_CLK_FUSE>,
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<&bpmp TEGRA234_CLK_TSEC_PKA>;
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clock-names = "nvdec", "fuse", "tsec_pka";
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resets = <&bpmp TEGRA234_RESET_NVDEC>;
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reset-names = "nvdec";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
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dma-coherent;
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nvidia,memory-controller = <&mc>;
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status = "okay";
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};
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nvenc@154c0000 {
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compatible = "nvidia,tegra234-nvenc";
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reg = <0x0 0x154c0000 0x0 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_NVENC>;
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clock-names = "nvenc";
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resets = <&bpmp TEGRA234_RESET_NVENC>;
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reset-names = "nvenc";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVENC>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVENCSRD &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVENCSWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso0 TEGRA234_SID_NVENC>;
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dma-coherent;
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};
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nvjpg@15540000 {
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compatible = "nvidia,tegra234-nvjpg";
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reg = <0x0 0x15540000 0x0 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_NVJPG1>;
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clock-names = "nvjpg";
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resets = <&bpmp TEGRA234_RESET_NVJPG1>;
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reset-names = "nvjpg";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVJPGB>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVJPG1SRD &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVJPG1SWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso0 TEGRA234_SID_NVJPG1>;
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dma-coherent;
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nvidia,host1x-class = <0x07>;
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};
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nvdla0: nvdla0@15880000 {
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compatible = "nvidia,tegra234-nvdla";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAA>;
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reg = <0x0 0x15880000 0x0 0x00040000>;
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interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&bpmp TEGRA234_RESET_DLA0>;
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clocks = <&bpmp TEGRA234_CLK_DLA0_CORE>,
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<&bpmp TEGRA234_CLK_DLA0_FALCON>;
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clock-names = "nvdla0", "nvdla0_flcn";
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_DLA0RDA &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA0FALRDB &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA0WRA &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA0FALWRB &emc>;
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interconnect-names = "dma-mem", "read-1", "write", "write-1";
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iommus = <&smmu_niso1 TEGRA234_SID_NVDLA0>;
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dma-coherent;
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status = "okay";
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};
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nvdla1: nvdla1@158c0000 {
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compatible = "nvidia,tegra234-nvdla";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAB>;
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reg = <0x0 0x158c0000 0x0 0x00040000>;
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interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&bpmp TEGRA234_RESET_DLA1>;
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clocks = <&bpmp TEGRA234_CLK_DLA1_CORE>,
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<&bpmp TEGRA234_CLK_DLA1_FALCON>;
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clock-names = "nvdla1", "nvdla1_flcn";
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_DLA1RDA &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA1FALRDB &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA1WRA &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA1FALWRB &emc>;
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interconnect-names = "dma-mem", "read-1", "write", "write-1";
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iommus = <&smmu_niso0 TEGRA234_SID_NVDLA1>;
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dma-coherent;
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status = "okay";
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};
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ofa@15a50000 {
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compatible = "nvidia,tegra234-ofa";
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reg = <0x0 0x15a50000 0x0 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_OFA>;
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clock-names = "ofa";
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resets = <&bpmp TEGRA234_RESET_OFA>;
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reset-names = "ofa";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_OFA>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_OFAR &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_OFAW &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso0 TEGRA234_SID_OFA>;
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dma-coherent;
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};
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pva0: pva0@16000000 {
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compatible = "nvidia,tegra234-pva";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PVA>;
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reg = <0x0 0x16000000 0x0 0x800000>,
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<0x0 0x24700000 0x0 0x080000>;
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interrupts = <0 234 0x04>,
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<0 432 0x04>,
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<0 433 0x04>,
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<0 434 0x04>,
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<0 435 0x04>,
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<0 436 0x04>,
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<0 437 0x04>,
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<0 438 0x04>,
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<0 439 0x04>;
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resets = <&bpmp TEGRA234_RESET_PVA0_ALL>;
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clocks = <&bpmp TEGRA234_CLK_PVA0_CPU_AXI>,
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<&bpmp TEGRA234_CLK_NAFLL_PVA0_VPS>,
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<&bpmp TEGRA234_CLK_PVA0_VPS>;
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clock-names = "axi", "vps0", "vps1";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0>;
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dma-coherent;
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status = "okay";
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pva0_ctx0n1: pva0_niso1_ctx0 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM0>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx1n1: pva0_niso1_ctx1 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM1>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx2n1: pva0_niso1_ctx2 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM2>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx3n1: pva0_niso1_ctx3 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM3>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx4n1: pva0_niso1_ctx4 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM4>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx5n1: pva0_niso1_ctx5 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM5>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx6n1: pva0_niso1_ctx6 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM6>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx7n1: pva0_niso1_ctx7 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM7>;
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dma-coherent;
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status = "okay";
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};
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};
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};
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};
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fragment@1 {
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target-path = "/bus@0";
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__overlay__ {
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gpu@17000000 {
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compatible = "nvidia,ga10b";
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reg = <0x0 0x17000000 0x0 0x01000000>,
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<0x0 0x18000000 0x0 0x01000000>,
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<0x0 0x03b41000 0x0 0x00001000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "stall0", "stall1", "stall2", "nonstall";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_GPU>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVL1R &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVL1W &emc>;
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interconnect-names = "dma-mem", "write";
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clocks = <&bpmp TEGRA234_CLK_GPUSYS>,
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<&bpmp TEGRA234_CLK_GPC0CLK>,
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<&bpmp TEGRA234_CLK_GPC1CLK>;
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clock-names = "sysclk", "gpc0clk", "gpc1clk";
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resets = <&bpmp TEGRA234_RESET_GPU>;
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dma-coherent;
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nvidia,bpmp = <&bpmp>;
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status = "okay";
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};
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tachometer@39c0000 {
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compatible = "nvidia,pwm-tegra234-tachometer";
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reg = <0x0 0x039c0000 0x0 0x10>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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#pwm-cells = <2>;
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clocks = <&bpmp TEGRA234_CLK_TACH0>;
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clock-names = "tach";
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resets = <&bpmp TEGRA234_RESET_TACH0>;
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reset-names = "tach";
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pulse-per-rev = <2>;
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capture-window-length = <2>;
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upper-threshold = <0xfffff>;
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lower-threshold = <0x0>;
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status = "okay";
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};
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ethernet@6800000 {
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reg = <0x0 0x06800000 0x0 0x10000>, /* HV base */
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<0x0 0x06810000 0x0 0x10000>, /* MGBE base */
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<0x0 0x068a0000 0x0 0x10000>, /* XPCS base */
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<0x0 0x068d0000 0x0 0x10000>; /* MACsec RM base */
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reg-names = "hypervisor", "mac", "xpcs", "macsec-base";
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interrupts = <0 384 0x4>, /* common */
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<0 385 0x4>, /* vm0 */
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<0 386 0x4>, /* vm1 */
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<0 387 0x4>, /* vm2 */
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<0 388 0x4>, /* vm3 */
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<0 389 0x4>, /* vm4 */
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<0 390 0x4>, /* MACsec non-secure intr */
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<0 391 0x4>; /* MACsec secure intr */
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interrupt-names = "common", "vm0", "vm1", "vm2", "vm3", "vm4",
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"macsec-ns-irq", "macsec-s-irq";
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resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
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<&bpmp TEGRA234_RESET_MGBE0_PCS>,
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<&bpmp TEGRA234_RESET_MGBE0_MACSEC>; /* MACsec non-secure reset */
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reset-names = "mac", "pcs", "macsec_ns_rst";
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clocks = <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
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<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
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<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
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<&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
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<&bpmp TEGRA234_CLK_MGBE0_TX>,
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<&bpmp TEGRA234_CLK_MGBE0_TX_PCS>,
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<&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
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<&bpmp TEGRA234_CLK_MGBE0_MAC>,
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<&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
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<&bpmp TEGRA234_CLK_MGBE0_APP>,
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<&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
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<&bpmp TEGRA234_CLK_MGBE0_MACSEC>,
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<&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>;
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clock-names = "rx-input-m", "rx-pcs-m", "rx-pcs-input",
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"rx-pcs", "tx", "tx-pcs", "mac-divider",
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"mac", "eee-pcs", "mgbe", "ptp-ref",
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"mgbe_macsec", "rx-input";
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nvidia,num-dma-chans = <10>;
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nvidia,dma-chans = <0 1 2 3 4 5 6 7 8 9>;
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nvidia,num-mtl-queues = <10>;
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nvidia,mtl-queues = <0 1 2 3 4 5 6 7 8 9>;
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nvidia,tc-mapping = <0 1 2 3 4 5 6 7 0 1>;
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/* Residual Queue can be any valid queue except RxQ0 */
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nvidia,residual-queue = <1>;
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nvidia,rxq_enable_ctrl = <2 2 2 2 2 2 2 2 2 2>;
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nvidia,tx-queue-prio = <0 1 2 3 4 5 6 7 0 0>;
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nvidia,rx-queue-prio = <0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80 0x0 0x0>;
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nvidia,dcs-enable = <0x1>;
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nvidia,macsec-enable = <0x1>;
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nvidia,rx_riwt = <512>;
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nvidia,rx_frames = <64>;
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nvidia,tx_usecs = <256>;
|
||||
nvidia,tx_frames = <16>;
|
||||
nvidia,promisc_mode = <1>;
|
||||
nvidia,slot_num_check = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
nvidia,slot_intvl_vals = <0x0 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D>;
|
||||
nvidia,ptp_ref_clock_speed = <312500000>;
|
||||
nvidia,instance_id = <0>; /* MGBE0 instance */
|
||||
nvidia,ptp-rx-queue = <3>;
|
||||
nvidia,dma_rx_ring_sz = <4096>;
|
||||
nvidia,dma_tx_ring_sz = <4096>;
|
||||
dma-coherent;
|
||||
nvidia,mac-addr-idx = <0>;
|
||||
nvidia,max-platform-mtu = <16383>;
|
||||
/* 1=enable, 0=disable */
|
||||
nvidia,pause_frames = <1>;
|
||||
phy-mode = "10gbase-r";
|
||||
/* 0:XFI 10G, 1:XFI 5G, 2:USXGMII 10G, 3:USXGMII 5G */
|
||||
nvidia,phy-iface-mode = <0>;
|
||||
nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(Y, 1) 0>;
|
||||
nvidia,mdio_addr = <0>;
|
||||
nvidia,vm-irq-config = <&mgbe_vm_irq_config>;
|
||||
|
||||
mdio {
|
||||
compatible = "nvidia,eqos-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy@0 {
|
||||
nvidia,phy-rst-pdelay-msec = <150>; /* msec */
|
||||
nvidia,phy-rst-duration-usec = <221000>; /* usec */
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <TEGRA234_MAIN_GPIO(Y, 3) IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target-path = "/";
|
||||
__overlay__ {
|
||||
mgbe_vm_irq_config: mgbe-vm-irq-config {
|
||||
nvidia,num-vm-irqs = <5>;
|
||||
vm_irq1 {
|
||||
nvidia,num-vm-channels = <2>;
|
||||
nvidia,vm-channels = <0 1>;
|
||||
nvidia,vm-num = <0>;
|
||||
nvidia,vm-irq-id = <0>;
|
||||
};
|
||||
vm_irq2 {
|
||||
nvidia,num-vm-channels = <2>;
|
||||
nvidia,vm-channels = <2 3>;
|
||||
nvidia,vm-num = <1>;
|
||||
nvidia,vm-irq-id = <1>;
|
||||
};
|
||||
vm_irq3 {
|
||||
nvidia,num-vm-channels = <2>;
|
||||
nvidia,vm-channels = <4 5>;
|
||||
nvidia,vm-num = <2>;
|
||||
nvidia,vm-irq-id = <2>;
|
||||
};
|
||||
vm_irq4 {
|
||||
nvidia,num-vm-channels = <2>;
|
||||
nvidia,vm-channels = <6 7>;
|
||||
nvidia,vm-num = <3>;
|
||||
nvidia,vm-irq-id = <3>;
|
||||
};
|
||||
vm_irq5 {
|
||||
nvidia,num-vm-channels = <2>;
|
||||
nvidia,vm-channels = <8 9>;
|
||||
nvidia,vm-num = <4>;
|
||||
nvidia,vm-irq-id = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
nvpmodel {
|
||||
compatible = "nvidia,nvpmodel";
|
||||
nvidia,bpmp = <&bpmp>;
|
||||
clocks = <&bpmp TEGRA234_CLK_EMC>;
|
||||
clock-names = "emc";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
linux,cma { /* Needed for nvgpu comptags */
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0x10000000>; /* 256MB */
|
||||
alignment = <0x0 0x10000>;
|
||||
linux,cma-default;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
dce@d800000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
display@13800000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@3 {
|
||||
target-path = "/bus@0";
|
||||
board_config {
|
||||
ids = "3737-0000-TS1","3737-0000-TS2","3737-0000-TS3","3737-0000-EB1","3737-0000-EB2","3737-0000-EB3","3737-0000-000","3737-0000-100","3737-0000-200";
|
||||
};
|
||||
__overlay__ {
|
||||
i2c@c240000 {
|
||||
ucsi_ccg@8 {
|
||||
interrupt-parent = <&gpio_aon>;
|
||||
interrupts = <TEGRA234_AON_GPIO(BB, 2) IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@5 {
|
||||
target-path = "/";
|
||||
__overlay__ {
|
||||
aliases {
|
||||
nvdla0 = "/bus@0/host1x@13e00000/nvdla0@15880000";
|
||||
nvdla1 = "/bus@0/host1x@13e00000/nvdla1@158c0000";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user