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arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller

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Fix the starting address of the non-prefetchable aperture of PCIe C3
controller.

Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")

Cherry picked from 47a2f35d9ea76d92aa2385671f527b75aa9dfe45

Change-Id: I77dd2e744c11ab657719e2ec6c8357883967e6bc
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2947578
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Vidya Sagar
2023-08-03 08:20:48 +00:00
committed by mobile promotions
parent 377744a854
commit 3a45ac52bd
1 changed files with 1 additions and 1 deletions
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tegra234.dtsi
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@@ -2586,7 +2586,7 @@
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
<0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
<0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,