diff --git a/include/platforms/dt-bindings/tegra234-p3740-0002-p3701-0008.h b/include/platforms/dt-bindings/tegra234-p3740-0002-p3701-0008.h
new file mode 100644
index 0000000..437bbc1
--- /dev/null
+++ b/include/platforms/dt-bindings/tegra234-p3740-0002-p3701-0008.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Definitions for Jetson tegra234-p3740-0002-p3701-0008 board.
+ */
+
+#include <dt-bindings/gpio/tegra234-gpio.h>
+
+#define JETSON_COMPATIBLE	"nvidia,p3740-0002+p3701-0008"
diff --git a/overlay/Makefile b/overlay/Makefile
index 2cf60ea..3eb8643 100644
--- a/overlay/Makefile
+++ b/overlay/Makefile
@@ -35,6 +35,9 @@ dtbo-y += tegra234-p3767-0000+p3509-a02-csi.dtbo
 dtbo-y += tegra234-p3767-0000+p3509-a02-hdr40.dtbo
 dtbo-y += tegra234-p3767-0000+p3509-a02-m2ke.dtbo
 dtbo-y += tegra234-p3767-0000+p3768-0000-csi.dtbo
+dtbo-y += tegra234-p3740-0002+p3701-0008-hdr20.dtbo
+dtbo-y += tegra234-p3740-0002+p3701-0008-m2ke.dtbo
+dtbo-y += tegra234-p3740-0002+p3701-0008-m2kb.dtbo
 
 ifneq ($(dtb-y),)
 dtb-y := $(addprefix $(makefile-path)/,$(dtb-y))
diff --git a/overlay/tegra234-p3740-0002+p3701-0008-hdr20.dts b/overlay/tegra234-p3740-0002+p3701-0008-hdr20.dts
new file mode 100644
index 0000000..f0579be
--- /dev/null
+++ b/overlay/tegra234-p3740-0002+p3701-0008-hdr20.dts
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+//Device-tree overlay for tegra234-p3740-0002-p3701-0008 20 pin header.
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
+#include <dt-bindings/tegra234-p3740-0002-p3701-0008.h>
+
+/ {
+	overlay-name = "Jetson 20pin Header";
+	compatible = JETSON_COMPATIBLE;
+
+	fragment@0 {
+		target = <&pinmux>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&jetson_io_pinmux>;
+			jetson_io_pinmux: exp-header-pinmux {
+				hdr20-pin8 {
+					nvidia,pins = "gen1_i2c_scl_pi3";
+				};
+				hdr20-pin10 {
+					nvidia,pins = "gen1_i2c_sda_pi4";
+				};
+			};
+		};
+	};
+	fragment@1 {
+		target = <&pinmux_aon>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&jetson_io_pinmux_aon>;
+			jetson_io_pinmux_aon: exp-header-pinmux {
+				hdr20-pin4 {
+					nvidia,pins = "can1_stb_pbb0";
+					nvidia,function = "dmic3";
+					nvidia,pin-label = "dmic3_clk";
+					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				hdr20-pin6 {
+					nvidia,pins = "can1_en_pbb1";
+					nvidia,function = "dmic3";
+					nvidia,pin-label = "dmic3_dat";
+					nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+			};
+		};
+	};
+};
diff --git a/overlay/tegra234-p3740-0002+p3701-0008-m2kb.dts b/overlay/tegra234-p3740-0002+p3701-0008-m2kb.dts
new file mode 100644
index 0000000..9fccd98
--- /dev/null
+++ b/overlay/tegra234-p3740-0002+p3701-0008-m2kb.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+//Device-tree overlay for tegra234-p3740-0002-p3701-0008 M.2 Key B Slot.
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
+#include <dt-bindings/tegra234-p3740-0002-p3701-0008.h>
+
+/ {
+	overlay-name = "Jetson M.2 Key B Slot";
+	compatible = JETSON_COMPATIBLE;
+
+	fragment@0 {
+		target = <&pinmux>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&jetson_io_pinmux>;
+			jetson_io_pinmux: exp-header-pinmux {
+				m2kb-pin20 {
+					nvidia,pins = "soc_gpio41_ph7";
+					nvidia,function = "i2s2";
+					nvidia,pin-label = "i2s2_sclk";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				m2kb-pin22 {
+					nvidia,pins = "soc_gpio42_pi0";
+					nvidia,function = "i2s2";
+					nvidia,pin-label = "i2s2_dout";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				m2kb-pin24 {
+					nvidia,pins = "soc_gpio43_pi1";
+					nvidia,function = "i2s2";
+					nvidia,pin-label = "i2s2_din";
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				m2kb-pin28 {
+					nvidia,pins = "soc_gpio44_pi2";
+					nvidia,function = "i2s2";
+					nvidia,pin-label = "i2s2_fs";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&pinmux_aon>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&jetson_io_pinmux_aon>;
+			jetson_io_pinmux_aon: exp-header-pinmux {
+				m2kb-pin40 {
+					nvidia,pins = "gen2_i2c_sda_pdd0";
+				};
+				m2kb-pin42 {
+					nvidia,pins = "gen2_i2c_scl_pcc7";
+				};
+			};
+		};
+	};
+};
diff --git a/overlay/tegra234-p3740-0002+p3701-0008-m2ke.dts b/overlay/tegra234-p3740-0002+p3701-0008-m2ke.dts
new file mode 100644
index 0000000..d0925fa
--- /dev/null
+++ b/overlay/tegra234-p3740-0002+p3701-0008-m2ke.dts
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+//Device-tree overlay for tegra234-p3740-0002-p3701-0008 M.2 Key E Slot.
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
+#include <dt-bindings/tegra234-p3740-0002-p3701-0008.h>
+
+/ {
+	overlay-name = "Jetson M.2 Key E Slot";
+	compatible = JETSON_COMPATIBLE;
+
+	p3740-0000_p3701-0000-m2ke@0 {
+		target = <&pinmux>;
+		__overlay__ {
+			pinctrl-names = "default";
+			pinctrl-0 = <&jetson_io_pinmux>;
+			jetson_io_pinmux: exp-header-pinmux {
+				m2ke-pin8 {
+					nvidia,pins = "soc_gpio45_pad0";
+					nvidia,function = "i2s1";
+					nvidia,pin-label = "i2s1_sclk";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				m2ke-pin10 {
+					nvidia,pins = "soc_gpio48_pad3";
+					nvidia,function = "i2s1";
+					nvidia,pin-label = "i2s1_fs";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				m2ke-pin12 {
+					nvidia,pins = "soc_gpio47_pad2";
+					nvidia,function = "i2s1";
+					nvidia,pin-label = "i2s1_din";
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				};
+				m2ke-pin14 {
+					nvidia,pins = "soc_gpio46_pad1";
+					nvidia,function = "i2s1";
+					nvidia,pin-label = "i2s1_dout";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				m2ke-pin22 {
+					nvidia,pins = "uart2_rx_px5";
+				};
+				m2ke-pin32 {
+					nvidia,pins = "uart2_tx_px4";
+				};
+				m2ke-pin34 {
+					nvidia,pins = "uart2_cts_px7";
+				};
+				m2ke-pin36 {
+					nvidia,pins = "uart2_rts_px6";
+				};
+				m2ke-pin58 {
+					nvidia,pins = "dp_aux_ch2_n_pn6";
+				};
+				m2ke-pin60 {
+					nvidia,pins = "dp_aux_ch2_p_pn5";
+				};
+			};
+		};
+	};
+};