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t23x: dts: enable only few display clocks in simplefb

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- earlier all display partition clocks were enabled
in simplefb driver to prevent Kernel CCF from disabling
clocks as it could result in display going blank
depending on which head/SOR and display clocks were
enabled by UEFI driver.
- But this unconditional enabling of clocks results in
higher refcounts for few clocks which isn't required and
this results in clocks not actually getting disabled when
display driver tries to disable them. For example, vpll0
clock doesn't get disabled due to higher refcount and
results in failure to set rate.
- So, keep only few clocks required to prevent the display
partition from getting clock gated.
- This will result in display blank just around kernel booting
to shell and need to be fixed in another set of changes to
enable full glitchless boot.

Bug 4167760

Change-Id: I03adbf238e8ffcecd5aa5c78f2cb6b929ece807b
Signed-off-by: Santosh Reddy Galma <galmar@nvidia.com>
Reviewed-on:
https://git-master.nvidia.com/r/c/device/hardware/nvidia/soc/t23x/+/2930154
(cherry picked from commit b99c771b042cf52eed5377b1b928c9a9a330a4f3)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2956935
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod Atyam
2023-08-14 08:17:37 +00:00
committed by mobile promotions
parent 46064c31c3
commit 42a05491c8
1 changed files with 1 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

56
overlay/tegra234-soc-overlay.dtsi
View File

@@ -32,66 +32,12 @@
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
clocks = <&bpmp TEGRA234_CLK_HUB>, clocks = <&bpmp TEGRA234_CLK_HUB>,
<&bpmp TEGRA234_CLK_DISP>, <&bpmp TEGRA234_CLK_DISP>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P1>,
<&bpmp TEGRA234_CLK_DPAUX>, <&bpmp TEGRA234_CLK_DPAUX>,
<&bpmp TEGRA234_CLK_FUSE>,
<&bpmp TEGRA234_CLK_DSIPLL_VCO>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTPN>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_VCO>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTB>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV10>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV25>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV27PN>,
<&bpmp TEGRA234_CLK_SPPLL1_VCO>,
<&bpmp TEGRA234_CLK_SPPLL1_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL1_DIV27PN>,
<&bpmp TEGRA234_CLK_VPLL0_REF>,
<&bpmp TEGRA234_CLK_VPLL0>,
<&bpmp TEGRA234_CLK_VPLL1>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0_REF>,
<&bpmp TEGRA234_CLK_RG0>,
<&bpmp TEGRA234_CLK_RG1>,
<&bpmp TEGRA234_CLK_DISPPLL>,
<&bpmp TEGRA234_CLK_DISPHUBPLL>,
<&bpmp TEGRA234_CLK_DSI_LP>,
<&bpmp TEGRA234_CLK_DSI_CORE>, <&bpmp TEGRA234_CLK_DSI_CORE>,
<&bpmp TEGRA234_CLK_DSI_PIXEL>,
<&bpmp TEGRA234_CLK_PRE_SOR0>,
<&bpmp TEGRA234_CLK_PRE_SOR1>,
<&bpmp TEGRA234_CLK_DP_LINK_REF>, <&bpmp TEGRA234_CLK_DP_LINK_REF>,
<&bpmp TEGRA234_CLK_SOR_LINKA_INPUT>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO_M>,
<&bpmp TEGRA234_CLK_RG0_M>,
<&bpmp TEGRA234_CLK_RG1_M>,
<&bpmp TEGRA234_CLK_SOR0_M>,
<&bpmp TEGRA234_CLK_SOR1_M>,
<&bpmp TEGRA234_CLK_PLLHUB>,
<&bpmp TEGRA234_CLK_SOR0>,
<&bpmp TEGRA234_CLK_SOR1>,
<&bpmp TEGRA234_CLK_SOR_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SF0>,
<&bpmp TEGRA234_CLK_SF0>,
<&bpmp TEGRA234_CLK_SF1>,
<&bpmp TEGRA234_CLK_DSI_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SOR0_REF>,
<&bpmp TEGRA234_CLK_PRE_SOR1_REF>,
<&bpmp TEGRA234_CLK_SOR0_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR1_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR0_REF>,
<&bpmp TEGRA234_CLK_SOR1_REF>,
<&bpmp TEGRA234_CLK_OSC>,
<&bpmp TEGRA234_CLK_DSC>,
<&bpmp TEGRA234_CLK_MAUD>, <&bpmp TEGRA234_CLK_MAUD>,
<&bpmp TEGRA234_CLK_AZA_2XBIT>, <&bpmp TEGRA234_CLK_AZA_2XBIT>,
<&bpmp TEGRA234_CLK_AZA_BIT>, <&bpmp TEGRA234_CLK_AZA_BIT>;
<&bpmp TEGRA234_CLK_MIPI_CAL>,
<&bpmp TEGRA234_CLK_UART_FST_MIPI_CAL>,
<&bpmp TEGRA234_CLK_SOR0_DIV>;
width = <0>; width = <0>;
height = <0>; height = <0>;
stride = <0>; stride = <0>;