diff --git a/nv-platform/tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi b/nv-platform/tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi
index cb2cfa5..a602b09 100644
--- a/nv-platform/tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi
+++ b/nv-platform/tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi
@@ -245,6 +245,18 @@
 			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
 		};
 
+		pcie-ep@14160000 {/* C4 - End Point */
+			phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+					<&p2u_hsio_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+			reset-gpios = <&gpio
+					TEGRA234_MAIN_GPIO(L, 1)
+					GPIO_ACTIVE_LOW>;
+			nvidia,refclk-select-gpios = <&gpio_aon
+							TEGRA234_AON_GPIO(AA, 4)
+							GPIO_ACTIVE_HIGH>;
+		};
+
 		/* C8 - Ethernet */
 		pcie@140a0000 {
 			status = "okay";
diff --git a/overlay/tegra234-p3737-0000+p3701-0000-as-p3767-0003.dts b/overlay/tegra234-p3737-0000+p3701-0000-as-p3767-0003.dts
index 672b82a..d80f192 100644
--- a/overlay/tegra234-p3737-0000+p3701-0000-as-p3767-0003.dts
+++ b/overlay/tegra234-p3737-0000+p3701-0000-as-p3767-0003.dts
@@ -39,7 +39,7 @@
 					max-link-speed = <0x3>;
 				};
 				/* C4 End Point */
-				pcie_ep@14160000 {
+				pcie-ep@14160000 {
 					max-link-speed = <0x3>;
 				};
 				/* C7 */
diff --git a/overlay/tegra234-p3737-0000+p3701-0000-as-p3767-0004.dts b/overlay/tegra234-p3737-0000+p3701-0000-as-p3767-0004.dts
index 1105baf..693ff12 100644
--- a/overlay/tegra234-p3737-0000+p3701-0000-as-p3767-0004.dts
+++ b/overlay/tegra234-p3737-0000+p3701-0000-as-p3767-0004.dts
@@ -39,7 +39,7 @@
 					max-link-speed = <0x3>;
 				};
 				/* C4 End Point */
-				pcie_ep@14160000 {
+				pcie-ep@14160000 {
 					max-link-speed = <0x3>;
 				};
 				/* C7 */
diff --git a/overlay/tegra234-p3767-sku-handling.dtsi b/overlay/tegra234-p3767-sku-handling.dtsi
index 512b4af..6510a28 100644
--- a/overlay/tegra234-p3767-sku-handling.dtsi
+++ b/overlay/tegra234-p3767-sku-handling.dtsi
@@ -80,7 +80,7 @@
 			};
 
 			/* C4 End Point */
-			pcie_ep@14160000 {
+			pcie-ep@14160000 {
 				max-link-speed = <0x3>;
 			};
 
@@ -129,4 +129,48 @@
 			};
 		};
 	};
+
+	/*
+	 * If ODMDATA contains hsio-uphy-config-40, then:
+	 * 1. Disable PCIE C4
+	 * 2. Enable PCIE C4 EP
+	 * 3. Reduce PCIE C1 to Gen2
+	 */
+	p3767-sku-handling-fragment@7 {
+		target-path = "/bus@0";
+		board_config {
+			odm-data = "hsio-uphy-config-40";
+		};
+		__overlay__ {
+			pcie@14160000 {
+				status = "disabled";
+			};
+			pcie-ep@14160000 {
+				status = "okay";
+			};
+			pcie@14100000 {
+				max-link-speed = <2>;
+			};
+		};
+	};
+
+	/*
+	 * If ODMDATA contains hsio-uphy-config-41, then:
+	 * 1. Disable PCIE C4
+	 * 2. Enable PCIE C4 EP
+	 */
+	p3767-sku-handling-fragment@8 {
+		target-path = "/bus@0";
+		board_config {
+			odm-data = "hsio-uphy-config-41";
+		};
+		__overlay__ {
+			pcie@14160000 {
+				status = "disabled";
+			};
+			pcie-ep@14160000 {
+				status = "okay";
+			};
+		};
+	};
 };