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arm64: tegra: Add Tegra234 PCIe C4 EP definition
Add PCIe C4 EP controller definition in device tree for Tegra234
devices.
Signed-off-by: Vedant Deshpande <vedantd@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Bug 4707773
Change-Id: Ib7d962389aafd2cc5eef4e5afaa2171c8009270c
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3207079
(cherry picked from commit 9551f57a77)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3216029
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
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@@ -4842,6 +4842,37 @@
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status = "disabled";
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status = "disabled";
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};
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};
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pcie-ep@14160000 {
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compatible = "nvidia,tegra234-pcie-ep";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
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reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
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0x00 0x36080000 0x0 0x00040000 /* DBI space (256K) */
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0x21 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
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reg-names = "appl", "atu_dma", "dbi", "addr_space";
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num-lanes = <4>;
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clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
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clock-names = "core";
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resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
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<&bpmp TEGRA234_RESET_PEX0_CORE_4>;
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reset-names = "apb", "core";
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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interrupt-names = "intr";
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nvidia,bpmp = <&bpmp 4>;
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nvidia,enable-ext-refclk;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>;
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dma-coherent;
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status = "disabled";
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};
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pcie@14180000 {
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pcie@14180000 {
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compatible = "nvidia,tegra234-pcie";
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compatible = "nvidia,tegra234-pcie";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
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