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t23x: overlay: fsicom: add new hsp mailbox and stream id inst

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- add top2 hsp mailbox 5 and 4 for core 1 usage
- add FSI_CPU1 stream id for core 1 memory map
- newnode created for each SMMU inst

Bug 4243457

Change-Id: Id66c060d5daa1ca6458e3cbeee81dafc88904560
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2977860
Reviewed-by: Prashant Kumar Shaw <pshaw@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Tested-by: Lovie Wang <loview@nvidia.com>
This commit is contained in:
Lovie Wang
2023-09-11 12:48:39 +08:00
committed by mobile promotions
parent 73569dc99b
commit 4e450ca886
2 changed files with 151 additions and 94 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
include/kernel/dt-bindings/memory/tegra234-mc.h
View File

@@ -114,7 +114,7 @@
#define TEGRA234_SID_XUSB_HOST 0x0e
#define TEGRA234_SID_XUSB_DEV 0x0f
#define TEGRA234_SID_BPMP 0x10
#define TEGRA234_SID_FSI 0x11
#define TEGRA234_SID_NISO1_FSI_CPU0 0x11
#define TEGRA234_SID_PVA0_VM0 0x12
#define TEGRA234_SID_PVA0_VM1 0x13
#define TEGRA234_SID_PVA0_VM2 0x14
@@ -171,6 +171,11 @@
#define TEGRA234_SID_HOST1X_CTX6 0x3b
#define TEGRA234_SID_HOST1X_CTX7 0x3c
/*FSI Stream Id*/
#define TEGRA234_SID_NISO1_FSI_CPU1 0x4BU
#define TEGRA234_SID_NISO1_FSI_CPU2 0x4CU
#define TEGRA234_SID_NISO1_FSI_CPU3 0X4DU
/*
* memory client IDs
*/

94
overlay/tegra234-soc-safetyservice-fsicom.dtsi
View File

@@ -8,29 +8,76 @@
fragment-fsicom@0 {
target-path = "/";
__overlay__ {
#if LINUX_VERSION >= 515
reserved-memory {
fsicom_resv: reservation-fsicom {
iommu-addresses = <&fsiccplex_com 0x0 0x0 0x0 0xf0000000>,
<&fsiccplex_com 0x0 0xf1000000 0xffffffff 0x0effffff>;
};
};
#address-cells = <2>;
#size-cells = <2>;
ranges;
fsiccplex_com:fsicom_client {
fsicom_resv: reservation-fsicom {
iommu-addresses = <&fsicom_client 0x0 0x0 0x0 0xf0000000>,
<&fsicom_client 0x0 0xf1000000 0xffffffff 0x0effffff>;
};
fsicom_resv_inst1: reservation-fsicom_inst1 {
iommu-addresses = <&fsicom_client_inst1 0x0 0x0 0x0 0xf0000000>,
<&fsicom_client_inst1 0x0 0xf1000000 0xffffffff 0x0effffff>;
};
};
#endif
fsicom_client: fsicom_client {
compatible = "nvidia,tegra234-fsicom-client";
#if TEGRA_HSP_DT_VERSION >= DT_VERSION_2
mboxes =
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(2)>,
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(1)>;
mbox-names = "fsi-tx", "fsi-rx";
iommus = <&smmu_niso1 TEGRA234_SID_FSI>;
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(1)>,
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(5)>,
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(4)>;
#else
mboxes =
<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_TX(2)>,
<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_RX(1)>,
<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_TX(5)>,
<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_RX(4)>;
#endif
mbox-names = "fsi-tx-cpu0", "fsi-rx-cpu0", "fsi-tx-cpu1", "fsi-rx-cpu1";
iommus = <&smmu_niso1 TEGRA234_SID_NISO1_FSI_CPU0>;
#if LINUX_VERSION < 515
iommu-resv-regions = <0x0 0x0 0x0 0xF0000000 0x0 0xF1000000 0xffffffff 0xffffffff>;
#else
memory-region = <&fsicom_resv>;
#endif
dma-coherent;
#if defined(ENABLE_FSI) && !defined(ENABLE_MODS_CONFIG)
enable-deinit-notify;
#endif
smmu_inst = <0>;
max_fsi_core=<1>; /*Value 1 <-> core 0, value 2 <-> core0,1*/
status = "disabled";
};
safetyservices_epl_client {
fsicom_client_inst1: fsicom_client_inst1 {
compatible = "nvidia,tegra234-fsicom-client";
iommus = <&smmu_niso1 TEGRA234_SID_NISO1_FSI_CPU1>;
#if LINUX_VERSION < 515
iommu-resv-regions = <0x0 0x0 0x0 0xF0000000 0x0 0xF1000000 0xffffffff 0xffffffff>;
#else
memory-region = <&fsicom_resv_inst1>;
#endif
dma-coherent;
smmu_inst = <1>;
status = "okay";
};
safetyservices_epl_client@110000 {
compatible = "nvidia,tegra234-epl-client";
mboxes = <&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(0)>;
#if TEGRA_HSP_DT_VERSION >= DT_VERSION_2
mboxes =
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(0)>;
#else
mboxes =
<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_TX(0)>;
#endif
mbox-names = "epl-tx";
reg = <0x0 0x00110000 0x0 0x4>,
<0x0 0x00110004 0x0 0x4>,
<0x0 0x00120000 0x0 0x4>,
@@ -51,9 +98,13 @@
client-misc-sw-generic-err3 = "gk20d";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR4_SW_ERR_CODE_0 */
client-misc-sw-generic-err4 = "gk20e";
status = "disabled";
};
#if defined(ENABLE_FSI) && !defined(ENABLE_MODS_CONFIG)
enable-deinit-notify;
#endif
status = "disabled";
};
FsiComIvc {
compatible = "nvidia,tegra-fsicom-channels";
status = "disabled";
@@ -61,42 +112,43 @@
channel_0{
frame-count = <4>;
frame-size = <1024>;
core-id = <0>;
NvSciCh = "nvfsicom_EPD";
};
channel_1{
frame-count = <30>;
frame-size = <64>;
core-id = <0>;
NvSciCh = "nvfsicom_CcplexApp";
};
channel_2{
frame-count = <4>;
frame-size = <64>;
core-id = <0>;
NvSciCh = "nvfsicom_CcplexApp_state_change";
};
channel_3{
frame-count = <4>;
frame-size = <64>;
core-id = <0>;
NvSciCh = "nvfsicom_app1";
};
channel_4{
frame-count = <2>;
frame-size = <512>;
frame-size = <64>;
core-id = <1>;
NvSciCh = "nvfsicom_app2";
};
channel_5{
frame-count = <4>;
frame-size = <64>;
core-id = <0>;
NvSciCh = "nvfsicom_appGR";
};
channel_6{
frame-count = <4>;
frame-size = <10240>;
core-id = <0>;
};
};