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t23x: nv-public: add support for P3737 C5 PCIe EP

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1. Add missing properties to enable C5 PCIe EP on P3737
2. Also add missing properties for some old p3737 boards

Bug 4428373

Change-Id: Ic7a6a36c6874a1d42fe903ce726b8aa075d108c4
Signed-off-by: Wayne Wang(SW-TEGRA) <waywang@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3040254
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Wayne Wang
2023-12-26 15:08:03 +08:00
committed by mobile promotions
parent ab02824e09
commit 5767db6887
3 changed files with 135 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
nv-platform/tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#include "nv-soc/tegra234-overlay.dtsi" #include "nv-soc/tegra234-overlay.dtsi"
#include "nv-soc/tegra234-soc-thermal.dtsi" #include "nv-soc/tegra234-soc-thermal.dtsi"
@@ -306,6 +306,12 @@
gpu@17000000 { gpu@17000000 {
status = "okay"; status = "okay";
}; };
pcie-ep@141a0000 {
nvidia,refclk-select-gpios = <&gpio
TEGRA234_MAIN_GPIO(Q, 4)
GPIO_ACTIVE_HIGH>;
};
}; };
tegra-hsp@b950000 { tegra-hsp@b950000 {

78
nv-soc/tegra234-soc-overlay.dtsi
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@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// //
// This file contains the DT nodes of T234 which are not in base/tegra234.dtsi // This file contains the DT nodes of T234 which are not in base/tegra234.dtsi
@@ -142,7 +142,49 @@
nvidia,lpdr = <TEGRA_PIN_DISABLE>; nvidia,lpdr = <TEGRA_PIN_DISABLE>;
}; };
}; };
pex_rst_c5_in_state: pex_rst_c5_in {
pex_rst {
nvidia,pins = "pex_l5_rst_n_paf1";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
};
pex_rst_c6_in_state: pex_rst_c6_in {
pex_rst {
nvidia,pins = "pex_l6_rst_n_paf3";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
};
pex_rst_c7_in_state: pex_rst_c7_in {
pex_rst {
nvidia,pins = "pex_l7_rst_n_pag1";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
};
pex_rst_c10_in_state: pex_rst_c10_in {
pex_rst {
nvidia,pins = "pex_l10_rst_n_pag7";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
};
eqos_mii_rx_input_state_disable: eqos_rx_disable { eqos_mii_rx_input_state_disable: eqos_rx_disable {
eqos { eqos {
nvidia,pins = "eqos_rd0_pe6","eqos_rd1_pe7", nvidia,pins = "eqos_rd0_pe6","eqos_rd1_pe7",
@@ -859,6 +901,38 @@
status = "disabled"; status = "disabled";
}; };
pcie-ep@141a0000 {
pinctrl-names = "default";
pinctrl-0 = <&pex_rst_c5_in_state>;
num-ib-windows = <2>;
num-ob-windows = <8>;
};
pcie-ep@141c0000 {
pinctrl-names = "default";
pinctrl-0 = <&pex_rst_c6_in_state>;
num-ib-windows = <2>;
num-ob-windows = <8>;
};
pcie-ep@141e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pex_rst_c7_in_state>;
num-ib-windows = <2>;
num-ob-windows = <8>;
};
pcie-ep@140e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pex_rst_c10_in_state>;
num-ib-windows = <2>;
num-ob-windows = <8>;
};
hsp_top2: hsp@1600000 { hsp_top2: hsp@1600000 {
compatible = "nvidia,tegra234-hsp"; compatible = "nvidia,tegra234-hsp";
reg = <0x0 0x1600000 0x0 0x90000>; reg = <0x0 0x1600000 0x0 0x90000>;

53
overlay/tegra234-p3737-0000+p3701-0000-dynamic.dts
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/dts-v1/; /dts-v1/;
/plugin/; /plugin/;
@@ -67,6 +67,57 @@
interrupts = <TEGRA234_AON_GPIO(BB, 2) IRQ_TYPE_LEVEL_LOW>; interrupts = <TEGRA234_AON_GPIO(BB, 2) IRQ_TYPE_LEVEL_LOW>;
}; };
}; };
pcie-ep@141a0000 {
nvidia,refclk-select-gpios = <&gpio_aon
TEGRA234_AON_GPIO(AA, 4)
GPIO_ACTIVE_HIGH>;
};
};
regulator-vdd-3v3-pcie {
gpio = <&gpio TEGRA234_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
};
};
};
/* PCIe 12V supply through NCP for TS3 */
fragment-t234-p3737-0000-p3701-0000@2 {
target-path = "/";
board_config {
ids = "3737-0000-TS3","3737-0000-200","3737-0000-300","3737-0000-EB3";
};
__overlay__ {
bus@0{
i2c@c240000 {
ncp_12v_pcie_supply: ncp81599@74 {
compatible = "nvidia,ncp81599";
reg = <0x74>;
regulator-name = "ncp81599";
ncp81599-supply = <&vdd_5v0_sys>;
status = "okay";
};
};
pcie@141a0000 {
vpcie12v-supply = <&ncp_12v_pcie_supply>;
};
pcie-ep@141a0000 {
vpcie12v-supply = <&ncp_12v_pcie_supply>;
};
};
};
};
/* PCIe C5 endpoint */
fragment-t234-p3737-0000-p3701-0000-pcie-c5-ep@0 {
target-path = "/bus@0";
board_config {
odm-data = "nvhs-uphy-config-1";
};
__overlay__ {
pcie@141a0000 {
status = "disabled";
};
pcie-ep@141a0000 {
status = "okay";
}; };
}; };
}; };