diff --git a/Makefile b/Makefile index 8ecd14b..8b9617c 100644 --- a/Makefile +++ b/Makefile @@ -5,6 +5,7 @@ dtbo-y := makefile-path := platform/t23x/concord/dts/generic-dts dtbo-y += tegra234-p3737-0000+p3701-0000-overlay.dtbo +dtbo-y += tegra234-jetson-overlay.dtbo ifneq ($(dtb-y),) dtb-y := $(addprefix $(makefile-path)/,$(dtb-y)) diff --git a/tegra234-jetson-overlay.dts b/tegra234-jetson-overlay.dts new file mode 100644 index 0000000..fa15c7a --- /dev/null +++ b/tegra234-jetson-overlay.dts @@ -0,0 +1,389 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include + +#define TEGRA234_CLK_NVJPG1 20U +#define TEGRA234_CLK_GPC0CLK 41U +#define TEGRA234_CLK_NVDEC 83U +#define TEGRA234_CLK_NVENC 89U +#define TEGRA234_CLK_NVJPG 90U +#define TEGRA234_CLK_TSEC_PKA 154U +#define TEGRA234_CLK_DLA0_FALCON 174U +#define TEGRA234_CLK_DLA0_CORE 175U +#define TEGRA234_CLK_DLA1_FALCON 176U +#define TEGRA234_CLK_DLA1_CORE 177U +#define TEGRA234_CLK_NAFLL_PVA0_CORE 211U +#define TEGRA234_CLK_NAFLL_PVA0_VPS 212U +#define TEGRA234_CLK_GPC1CLK 236U +#define TEGRA234_CLK_PVA0_CPU_AXI 295U +#define TEGRA234_CLK_PVA0_VPS 297U +#define TEGRA234_CLK_GPUSYS 304U +#define TEGRA234_CLK_OFA 334U + +#define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c +#define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b +#define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c +#define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d +#define TEGRA234_MEMORY_CLIENT_DLA0WRB 0x2e +#define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f +#define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a +#define TEGRA234_MEMORY_CLIENT_OFAR 0x5d +#define TEGRA234_MEMORY_CLIENT_OFAW 0x5e +#define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e +#define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f +#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78 +#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79 +#define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e +#define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f +#define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe +#define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf +#define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0 +#define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1 +#define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2 +#define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3 +#define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4 +#define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5 +#define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6 +#define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7 +#define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8 +#define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9 +#define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca +#define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb +#define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9 +#define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea +#define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb +#define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec +#define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0 +#define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123 +#define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124 + +#define TEGRA234_RESET_DLA0 6U +#define TEGRA234_RESET_DLA1 7U +#define TEGRA234_RESET_OFA 9U +#define TEGRA234_RESET_NVJPG1 10U +#define TEGRA234_RESET_GPU 19U +#define TEGRA234_RESET_NVDEC 44U +#define TEGRA234_RESET_NVENC 59U +#define TEGRA234_RESET_NVJPG 61U +#define TEGRA234_RESET_PVA0_ALL 66U + +#define TEGRA234_POWER_DOMAIN_OFA 1U +#define TEGRA234_POWER_DOMAIN_NVDEC 23U +#define TEGRA234_POWER_DOMAIN_NVJPGA 24U +#define TEGRA234_POWER_DOMAIN_NVENC 25U +#define TEGRA234_POWER_DOMAIN_VIC 29U +#define TEGRA234_POWER_DOMAIN_PVA 30U +#define TEGRA234_POWER_DOMAIN_DLAA 32U +#define TEGRA234_POWER_DOMAIN_DLAB 33U +#define TEGRA234_POWER_DOMAIN_GPU 35U +#define TEGRA234_POWER_DOMAIN_NVJPGB 36U + +#define TEGRA234_SID_NVDLA1 0x23 +#define TEGRA234_SID_NVENC 0x24 +#define TEGRA234_SID_NVJPG1 0x25 +#define TEGRA234_SID_OFA 0x26 + +#define TEGRA234_SID_PVA0_VM0 0x12U +#define TEGRA234_SID_PVA0_VM1 0x13U +#define TEGRA234_SID_PVA0_VM2 0x14U +#define TEGRA234_SID_PVA0_VM3 0x15U +#define TEGRA234_SID_PVA0_VM4 0x16U +#define TEGRA234_SID_PVA0_VM5 0x17U +#define TEGRA234_SID_PVA0_VM6 0x18U +#define TEGRA234_SID_PVA0_VM7 0x19U +#define TEGRA234_SID_NVDEC 0x29 +#define TEGRA234_SID_NVJPG 0x2a +#define TEGRA234_SID_NVDLA0 0x2B +#define TEGRA234_SID_PVA0 0x2C + +/ { + overlay-name = "Tegra234 Jetson Overlay"; + compatible = "nvidia,tegra234"; + + fragment@0 { + target-path = "/bus@0/host1x@13e00000"; + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + ranges = <0x14800000 0x14800000 0x02000000>, + <0x24700000 0x24700000 0x00080000>; + + nvjpg@15380000 { + compatible = "nvidia,tegra234-nvjpg"; + reg = <0x15380000 0x00040000>; + clocks = <&bpmp TEGRA234_CLK_NVJPG>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA234_RESET_NVJPG>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVJPGA>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVJPGSRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_NVJPGSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_NVJPG>; + dma-coherent; + + nvidia,host1x-class = <0xc0>; + }; + + nvdec@15480000 { + compatible = "nvidia,tegra234-nvdec"; + reg = <0x15480000 0x00040000>; + clocks = <&bpmp TEGRA234_CLK_NVDEC>, + <&bpmp TEGRA234_CLK_FUSE>, + <&bpmp TEGRA234_CLK_TSEC_PKA>; + clock-names = "nvdec", "fuse", "tsec_pka"; + resets = <&bpmp TEGRA234_RESET_NVDEC>; + reset-names = "nvdec"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; + dma-coherent; + + nvidia,memory-controller = <&mc>; + }; + + nvenc@154c0000 { + compatible = "nvidia,tegra234-nvenc"; + reg = <0x154c0000 0x00040000>; + clocks = <&bpmp TEGRA234_CLK_NVENC>; + clock-names = "nvenc"; + resets = <&bpmp TEGRA234_RESET_NVENC>; + reset-names = "nvenc"; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVENC>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVENCSRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_NVENCSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_NVENC>; + dma-coherent; + }; + + nvjpg@15540000 { + compatible = "nvidia,tegra234-nvjpg"; + reg = <0x15540000 0x00040000>; + clocks = <&bpmp TEGRA234_CLK_NVJPG1>; + clock-names = "nvjpg"; + resets = <&bpmp TEGRA234_RESET_NVJPG1>; + reset-names = "nvjpg"; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVJPGB>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVJPG1SRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_NVJPG1SWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_NVJPG1>; + dma-coherent; + + nvidia,host1x-class = <0x07>; + }; + + nvdla0: nvdla0@15880000 { + compatible = "nvidia,tegra234-nvdla"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAA>; + reg = <0x15880000 0x00040000>; + interrupts = ; + + resets = <&bpmp TEGRA234_RESET_DLA0>; + clocks = <&bpmp TEGRA234_CLK_DLA0_CORE>, + <&bpmp TEGRA234_CLK_DLA0_FALCON>; + clock-names = "nvdla0", "nvdla0_flcn"; + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_DLA0RDA &emc>, + <&mc TEGRA234_MEMORY_CLIENT_DLA0FALRDB &emc>, + <&mc TEGRA234_MEMORY_CLIENT_DLA0WRA &emc>, + <&mc TEGRA234_MEMORY_CLIENT_DLA0FALWRB &emc>; + interconnect-names = "dma-mem", "read-1", "write", "write-1"; + iommus = <&smmu_niso1 TEGRA234_SID_NVDLA0>; + dma-coherent; + status = "okay"; + }; + + nvdla1: nvdla1@158c0000 { + compatible = "nvidia,tegra234-nvdla"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAB>; + reg = <0x158c0000 0x00040000>; + interrupts = ; + + resets = <&bpmp TEGRA234_RESET_DLA1>; + clocks = <&bpmp TEGRA234_CLK_DLA1_CORE>, + <&bpmp TEGRA234_CLK_DLA1_FALCON>; + clock-names = "nvdla1", "nvdla1_flcn"; + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_DLA1RDA &emc>, + <&mc TEGRA234_MEMORY_CLIENT_DLA1FALRDB &emc>, + <&mc TEGRA234_MEMORY_CLIENT_DLA1WRA &emc>, + <&mc TEGRA234_MEMORY_CLIENT_DLA1FALWRB &emc>; + interconnect-names = "dma-mem", "read-1", "write", "write-1"; + iommus = <&smmu_niso0 TEGRA234_SID_NVDLA1>; + dma-coherent; + status = "okay"; + }; + + ofa@15a50000 { + compatible = "nvidia,tegra234-ofa"; + reg = <0x15a50000 0x00040000>; + clocks = <&bpmp TEGRA234_CLK_OFA>; + clock-names = "ofa"; + resets = <&bpmp TEGRA234_RESET_OFA>; + reset-names = "ofa"; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_OFA>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_OFAR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_OFAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_OFA>; + dma-coherent; + }; + + pva0: pva0@16000000 { + compatible = "nvidia,tegra234-pva"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PVA>; + reg = <0x16000000 0x800000>, + <0x24700000 0x080000>; + interrupts = <0 234 0x04>, + <0 432 0x04>, + <0 433 0x04>, + <0 434 0x04>, + <0 435 0x04>, + <0 436 0x04>, + <0 437 0x04>, + <0 438 0x04>, + <0 439 0x04>; + resets = <&bpmp TEGRA234_RESET_PVA0_ALL>; + clocks = <&bpmp TEGRA234_CLK_PVA0_CPU_AXI>, + <&bpmp TEGRA234_CLK_NAFLL_PVA0_VPS>, + <&bpmp TEGRA234_CLK_PVA0_VPS>; + clock-names = "axi", "vps0", "vps1"; + + iommus = <&smmu_niso1 TEGRA234_SID_PVA0>; + dma-coherent; + status = "okay"; + + pva0_ctx0n1: pva0_niso1_ctx0 { + compatible = "nvidia,pva-tegra186-iommu-context"; + iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM0>; + dma-coherent; + status = "okay"; + }; + + pva0_ctx1n1: pva0_niso1_ctx1 { + compatible = "nvidia,pva-tegra186-iommu-context"; + iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM1>; + dma-coherent; + status = "okay"; + }; + + pva0_ctx2n1: pva0_niso1_ctx2 { + compatible = "nvidia,pva-tegra186-iommu-context"; + iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM2>; + dma-coherent; + status = "okay"; + }; + + pva0_ctx3n1: pva0_niso1_ctx3 { + compatible = "nvidia,pva-tegra186-iommu-context"; + iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM3>; + dma-coherent; + status = "okay"; + }; + + pva0_ctx4n1: pva0_niso1_ctx4 { + compatible = "nvidia,pva-tegra186-iommu-context"; + iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM4>; + dma-coherent; + status = "okay"; + }; + + pva0_ctx5n1: pva0_niso1_ctx5 { + compatible = "nvidia,pva-tegra186-iommu-context"; + iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM5>; + dma-coherent; + status = "okay"; + }; + + pva0_ctx6n1: pva0_niso1_ctx6 { + compatible = "nvidia,pva-tegra186-iommu-context"; + iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM6>; + dma-coherent; + status = "okay"; + }; + + pva0_ctx7n1: pva0_niso1_ctx7 { + compatible = "nvidia,pva-tegra186-iommu-context"; + iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM7>; + dma-coherent; + status = "okay"; + }; + }; + }; + }; + + fragment@1 { + target-path = "/bus@0"; + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + + gpu@17000000 { + compatible = "nvidia,ga10b"; + reg = <0x17000000 0x01000000>, + <0x18000000 0x01000000>, + <0x03b41000 0x00001000>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + interrupt-names = "stall0", "stall1", "stall2", "nonstall"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_GPU>; + clocks = <&bpmp TEGRA234_CLK_GPUSYS>, + <&bpmp TEGRA234_CLK_GPC0CLK>, + <&bpmp TEGRA234_CLK_GPC1CLK>; + clock-names = "sysclk", "gpc0clk", "gpc1clk"; + resets = <&bpmp TEGRA234_RESET_GPU>; + dma-coherent; + + nvidia,bpmp = <&bpmp>; + + status = "okay"; + }; + }; + }; + + fragment@2 { + target-path = "/"; + __overlay__ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { /* Needed for nvgpu comptags */ + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x10000000>; /* 256MB */ + alignment = <0x0 0x10000>; + linux,cma-default; + status = "okay"; + }; + }; + }; + }; +};