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arvala: dts: Change p3767 SKU
The public release of the p3767 module will be based on the SKU0, while bringup happened with SKU2. Renaming the files avoid duplicating those files for the SKU0 as both the SKUs are identical except that SKU2 has SD card slot. Bug 3759595 Signed-off-by: Dipen Patel <dipenp@nvidia.com> Change-Id: I37fa3929a7bad6ae16f66d9a22ece09d8e6bb59c Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/platform/t23x/arvala-dts/+/2795932 Reviewed-by: Brad Griffis <bgriffis@nvidia.com> Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/platform/t23x/arvala-dts/+/2798109 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Brad Griffis <bgriffis@nvidia.com>
This commit is contained in:
Dipen Patel
committed by
Laxman Dewangan
Laxman Dewangan
parent
952d12bdb3
commit
70d869c90a
24
overlay/tegra234-p3767-0000+p3509-a02-hdr40.dts
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24
overlay/tegra234-p3767-0000+p3509-a02-hdr40.dts
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/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Device-tree overlay for 40-pin expansion Header.
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*/
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/dts-v1/;
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/plugin/;
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#include "tegra234-p3767-0000-common-hdr40.dtsi"
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164
overlay/tegra234-p3767-0000-common-hdr40.dtsi
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164
overlay/tegra234-p3767-0000-common-hdr40.dtsi
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/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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/ {
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overlay-name = "Jetson 40pin Header";
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compatible = "nvidia,p3509-0000-a2+p3767-0000";
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fragment@0 {
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target = <&pinmux>;
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__overlay__ {
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pinctrl-names = "default";
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pinctrl-0 = <&jetson_io_pinmux>;
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jetson_io_pinmux: exp-header-pinmux {
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hdr40-pin3 {
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nvidia,pins = "gen8_i2c_scl_pdd1";
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nvidia,pin-label = "i2c8";
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};
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hdr40-pin5 {
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nvidia,pins = "gen8_i2c_sda_pdd2";
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nvidia,pin-label = "i2c8";
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};
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hdr40-pin8 {
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nvidia,pins = "uart1_tx_pr2";
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};
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hdr40-pin10 {
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nvidia,pins = "uart1_rx_pr3";
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};
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hdr40-pin11 {
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nvidia,pins = "uart1_rts_pr4";
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nvidia,function = "uarta";
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nvidia,pin-group = "uarta-cts/rts";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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hdr40-pin12 {
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nvidia,pins = "soc_gpio41_ph7";
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nvidia,function = "i2s2";
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nvidia,pin-label = "i2s2_sclk";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin13 {
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nvidia,pins = "spi3_sck_py0";
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nvidia,function = "spi3";
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nvidia,pin-label = "spi3_sck";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin16 {
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nvidia,pins = "spi3_cs0_py3";
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nvidia,function = "spi3";
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nvidia,pin-label = "spi3_cs0";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin18 {
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nvidia,pins = "spi3_cs0_py4";
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nvidia,function = "spi3";
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nvidia,pin-label = "spi3_cs1";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin19 {
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nvidia,pins = "spi1_mosi_pz5";
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nvidia,function = "spi1";
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nvidia,pin-label = "spi1_dout";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin21 {
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nvidia,pins = "spi1_miso_pz4";
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nvidia,function = "spi1";
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nvidia,pin-label = "spi1_din";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin22 {
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nvidia,pins = "spi3_miso_py1";
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nvidia,function = "spi3";
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nvidia,pin-label = "spi3_din";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin23 {
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nvidia,pins = "spi1_sck_pz3";
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nvidia,function = "spi1";
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nvidia,pin-label = "spi1_sck";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin24 {
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nvidia,pins = "spi1_cs0_pz6";
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nvidia,function = "spi1";
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nvidia,pin-label = "spi1_cs0";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin26 {
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nvidia,pins = "spi1_cs1_pz7";
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nvidia,function = "spi1";
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nvidia,pin-label = "spi1_cs1";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin27 {
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nvidia,pins = "gen2_i2c_sda_pdd0";
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};
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hdr40-pin28 {
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nvidia,pins = "gen2_i2c_scl_pcc7";
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};
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hdr40-pin35 {
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nvidia,pins = "soc_gpio44_pi2";
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nvidia,function = "i2s2";
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nvidia,pin-label = "i2s2_fs";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin36 {
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nvidia,pins = "uart1_cts_pr5";
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nvidia,function = "uarta";
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nvidia,pin-group = "uarta-cts/rts";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin37 {
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nvidia,pins = "spi3_mosi_py2";
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nvidia,function = "spi3";
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nvidia,pin-label = "spi3_dout";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin38 {
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nvidia,pins = "soc_gpio43_pi1";
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nvidia,function = "i2s2";
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nvidia,pin-label = "i2s2_din";
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin40 {
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nvidia,pins = "soc_gpio42_pi0";
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nvidia,function = "i2s2";
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nvidia,pin-label = "i2s2_dout";
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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};
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};
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};
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};
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