From 7577f8b5315e3f7ada60beac190a2d66dd4347ae Mon Sep 17 00:00:00 2001
From: Vishwaroop A <va@nvidia.com>
Date: Tue, 5 Mar 2024 05:16:31 +0000
Subject: [PATCH] nv-soc: qspi: set qspi parent and frequency

Configure the QSPI controller parent clock
to PLLC and set the required frequency.

Bug 4509953
Bug 4474594

Signed-off-by: Vishwaroop A <va@nvidia.com>
Change-Id: I9d258778e8ee7932d2bcbd5b3c8b648d9b339624
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3089397
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
---
 nv-soc/tegra234-base-overlay.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/nv-soc/tegra234-base-overlay.dtsi b/nv-soc/tegra234-base-overlay.dtsi
index 8d8dff3..73b1601 100644
--- a/nv-soc/tegra234-base-overlay.dtsi
+++ b/nv-soc/tegra234-base-overlay.dtsi
@@ -423,6 +423,11 @@
 			dma-names = "rx", "tx";
 			dma-coherent;
 			iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>;
+			assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
+					   <&bpmp TEGRA234_CLK_QSPI0_PM>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>,
+						 <&bpmp TEGRA234_CLK_QSPI0_2X_PM>;
+			assigned-clock-rates = <199999998 99999999>;
 		};
 
 		hardware-timestamp@3aa0000 {