diff --git a/overlay/tegra234-base-overlay.dtsi b/overlay/tegra234-base-overlay.dtsi
index a591f4a..9bbdd1f 100644
--- a/overlay/tegra234-base-overlay.dtsi
+++ b/overlay/tegra234-base-overlay.dtsi
@@ -21,12 +21,14 @@
 #define TEGRA234_POWER_DOMAIN_DLAB		33U
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	overlay-name = "Add nvidia,t234 Overlay Support";
 	compatible = "nvidia,tegra234";
 
 	fragment-t234-base@0 {
 		target-path = "/";
 		 __overlay__ {
+#endif
 			aliases {
 				serial0 = "/bus@0/serial@3100000";
 				serial1 = "/bus@0/serial@3110000";
@@ -799,6 +801,8 @@
 					nvidia,vm-irq-id = <3>;
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-camera-p3785.dtsi b/overlay/tegra234-camera-p3785.dtsi
index 8c9e6d2..168242b 100644
--- a/overlay/tegra234-camera-p3785.dtsi
+++ b/overlay/tegra234-camera-p3785.dtsi
@@ -6,9 +6,11 @@
 #define CAM0_PWDN	TEGRA234_AON_GPIO(AA, 4)
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-camera@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			gpio@c2f0000 {
 				camera-control-output-high {
 					gpio-hog;
@@ -402,6 +404,8 @@
 					};
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-dcb-p3737-0000-p3701-0000.dtsi b/overlay/tegra234-dcb-p3737-0000-p3701-0000.dtsi
index 3a85ecf..26c7677 100644
--- a/overlay/tegra234-dcb-p3737-0000-p3701-0000.dtsi
+++ b/overlay/tegra234-dcb-p3737-0000-p3701-0000.dtsi
@@ -2,10 +2,11 @@
 // SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-t234-dcb@0 {
 		target-path = "/";
 		__overlay__ {
-
+#endif
 			display@13800000 {
 				nvidia,dcb-image = [
 					55 aa 16 00 00 37 34 30 30 e9 4c 19 77 cc 56 49
@@ -535,6 +536,8 @@
 					40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00
 					00 00 00 00 00 00 00 ];
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-p3701-0000-prod-overlay.dtsi b/overlay/tegra234-p3701-0000-prod-overlay.dtsi
index 692cf1e..29b5bfd 100644
--- a/overlay/tegra234-p3701-0000-prod-overlay.dtsi
+++ b/overlay/tegra234-p3701-0000-prod-overlay.dtsi
@@ -2,9 +2,11 @@
 // SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-p3701-prod@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			bus@0 {
 				aon@c000000 {
 					prod-settings {
@@ -322,6 +324,8 @@
 					};
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-p3701-0000.dtsi b/overlay/tegra234-p3701-0000.dtsi
index 42db9a5..39aefce 100644
--- a/overlay/tegra234-p3701-0000.dtsi
+++ b/overlay/tegra234-p3701-0000.dtsi
@@ -4,9 +4,11 @@
 #include "tegra234-p3701-0000-prod-overlay.dtsi"
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-t234-p3701-0000@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			bus@0 {
 				i2c@c240000 {
 					ina3221@40 {
@@ -149,6 +151,8 @@
 					status = "okay";
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-p3701-0008.dtsi b/overlay/tegra234-p3701-0008.dtsi
index 942c8d4..944289e 100644
--- a/overlay/tegra234-p3701-0008.dtsi
+++ b/overlay/tegra234-p3701-0008.dtsi
@@ -2,9 +2,11 @@
 // SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-t234-p3701-0008@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			bus@0 {
 				i2c@c240000 {
 					ina3221@40 {
@@ -290,6 +292,8 @@
 					status = "okay";
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-p3737-0000+p3701-0000.dts b/overlay/tegra234-p3737-0000+p3701-0000.dts
index 5ca6cdf..b11502b 100644
--- a/overlay/tegra234-p3737-0000+p3701-0000.dts
+++ b/overlay/tegra234-p3737-0000+p3701-0000.dts
@@ -16,11 +16,12 @@
 #include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	compatible = "nvidia,p3737-0000+p3701-0000";
-
 	fragment-t234-p3737-p3701@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			cpus {
 				idle-states {
 					c7 {
@@ -336,6 +337,8 @@
 			display@13800000 {
 				status = "okay";
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-p3737-0000.dtsi b/overlay/tegra234-p3737-0000.dtsi
index 51442dc..1ed6cf5 100644
--- a/overlay/tegra234-p3737-0000.dtsi
+++ b/overlay/tegra234-p3737-0000.dtsi
@@ -2,9 +2,11 @@
 // SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-t234-p3737-0000@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			bus@0 {
 				spi@3210000{ /* SPI1 in 40 pin conn */
 					spi@0 { /* chip select 0 */
@@ -125,6 +127,8 @@
 					};
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-p3740-0002+p3701-0008-safety.dts b/overlay/tegra234-p3740-0002+p3701-0008-safety.dts
index 15d4987..0fcb904 100644
--- a/overlay/tegra234-p3740-0002+p3701-0008-safety.dts
+++ b/overlay/tegra234-p3740-0002+p3701-0008-safety.dts
@@ -7,9 +7,11 @@
 #include "tegra234-soc-safetyservice-fsicom.dtsi"
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-t234-p3740-p3701-safety@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			compatible = "nvidia,p3740-0002+p3701-0008", "safety", "nvidia,p3701-0008", "nvidia,tegra234";
 
 			bus@0 {
@@ -223,6 +225,8 @@
 					};
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-p3740-0002+p3701-0008.dts b/overlay/tegra234-p3740-0002+p3701-0008.dts
index 68f2f53..01efc77 100644
--- a/overlay/tegra234-p3740-0002+p3701-0008.dts
+++ b/overlay/tegra234-p3740-0002+p3701-0008.dts
@@ -15,11 +15,13 @@
 #include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	compatible = "nvidia,p3740-0002+p3701-0008";
 
 	fragment-t234-p3740-p3701@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			chosen {
 				bootargs = "console=ttyTCU0,115200n8";
 			};
@@ -292,6 +294,8 @@
 			display@13800000 {
 				status = "okay";
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-p3740-0002.dtsi b/overlay/tegra234-p3740-0002.dtsi
index d447990..5162a0c 100644
--- a/overlay/tegra234-p3740-0002.dtsi
+++ b/overlay/tegra234-p3740-0002.dtsi
@@ -4,9 +4,11 @@
 #include "tegra234-soc-audio-dai-links.dtsi"
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-t234-p3740-0002@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			bus@0 {
 				i2c@31c0000 {
 					typec: stusb1600@28 {
@@ -231,6 +233,8 @@
 				regulator-min-microvolt = <5000000>;
 				regulator-max-microvolt = <5000000>;
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-p3767-0000.dtsi b/overlay/tegra234-p3767-0000.dtsi
index 531fb26..f4f739c 100644
--- a/overlay/tegra234-p3767-0000.dtsi
+++ b/overlay/tegra234-p3767-0000.dtsi
@@ -6,10 +6,12 @@
 #include <dt-bindings/interrupt/tegra234-irq.h>
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	p3767-0000-fragment@0 {
 		target-path = "/";
 
 		__overlay__ {
+#endif
 			bus@0 {
 				mmc@3400000 {
 					no-sdio;
@@ -78,6 +80,8 @@
 					status = "okay";
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-p3768-0000+p3767-0000.dts b/overlay/tegra234-p3768-0000+p3767-0000.dts
index c7c77a0..60169ac 100644
--- a/overlay/tegra234-p3768-0000+p3767-0000.dts
+++ b/overlay/tegra234-p3768-0000+p3767-0000.dts
@@ -14,11 +14,13 @@
 #include "tegra234-soc-camera.dtsi"
 #include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	overlay-name = "Tegra234 P3768-0000+P3767-0000 Overlay";
 
 	fragment-t234-p3768-p3767@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			bpmp {
 				i2c {
 					vrs@3c {
@@ -455,6 +457,8 @@
 			display@13800000 {
 				status = "okay";
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-p3768-0000.dtsi b/overlay/tegra234-p3768-0000.dtsi
index 5af19b5..01782e1 100644
--- a/overlay/tegra234-p3768-0000.dtsi
+++ b/overlay/tegra234-p3768-0000.dtsi
@@ -1,10 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-t234-p3768-0000@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			bus@0 {
 
 				aconnect@2900000 {
@@ -36,6 +38,8 @@
 
 				hdr40_snd_link_i2s: nvidia-audio-card,dai-link@77 { };
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-soc-audio-dai-links.dtsi b/overlay/tegra234-soc-audio-dai-links.dtsi
index d10a645..af59bda 100644
--- a/overlay/tegra234-soc-audio-dai-links.dtsi
+++ b/overlay/tegra234-soc-audio-dai-links.dtsi
@@ -7,9 +7,11 @@
 #define ADMAIF_CIF(i)	(TEGRA186_ADMAIF_CIF_OFFSET  + i - 1)
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-audio-links@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			sound {
 				/* ADMAIF <--> XBAR PCM links */
 				admaif1_pcm_link: nvidia-audio-card,dai-link@0 {
@@ -2276,6 +2278,8 @@
 					};
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-soc-camera.dtsi b/overlay/tegra234-soc-camera.dtsi
index f67d457..cbbe983 100644
--- a/overlay/tegra234-soc-camera.dtsi
+++ b/overlay/tegra234-soc-camera.dtsi
@@ -12,10 +12,11 @@
 #include <dt-bindings/memory/tegra234-mc.h>
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-camera@0 {
 		target-path = "/";
 		__overlay__ {
-
+#endif
 			aliases { /* RCE is the Camera RTCPU */
 				tegra-camera-rtcpu = "/rtcpu@bc00000";
 			};
@@ -265,6 +266,8 @@
 					status = "disabled";
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-soc-display-overlay.dtsi b/overlay/tegra234-soc-display-overlay.dtsi
index c50725e..3fdbae4 100644
--- a/overlay/tegra234-soc-display-overlay.dtsi
+++ b/overlay/tegra234-soc-display-overlay.dtsi
@@ -5,8 +5,10 @@
 
 / {
 	fragment-t234-display@0 {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		target-path = "/";
 		__overlay__ {
+#endif
 
 			dce@d800000 {
 				compatible = "nvidia,tegra234-dce";
@@ -179,6 +181,8 @@
 					dma-coherent;
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-soc-overlay.dtsi b/overlay/tegra234-soc-overlay.dtsi
index 9df07f5..5f73c3d 100644
--- a/overlay/tegra234-soc-overlay.dtsi
+++ b/overlay/tegra234-soc-overlay.dtsi
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 //
 // This file contains the DT nodes of T234 which are not in base/tegra234.dtsi
 
@@ -16,9 +16,11 @@
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-t234-soc@0 {
 		target-path = "/";
 		 __overlay__ {
+#endif
 			aliases {
 				nvdla0 = "/bus@0/host1x@13e00000/nvdla0@15880000";
 				nvdla1 = "/bus@0/host1x@13e00000/nvdla1@158c0000";
@@ -1004,6 +1006,8 @@
 					status = "disabled";
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-soc-prod-overlay.dtsi b/overlay/tegra234-soc-prod-overlay.dtsi
index 2fd4cd7..40c8efb 100644
--- a/overlay/tegra234-soc-prod-overlay.dtsi
+++ b/overlay/tegra234-soc-prod-overlay.dtsi
@@ -2,9 +2,11 @@
 // SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-t234-soc-prod@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			bus@0 {
 				i2c@3160000 {
 					prod-settings {
@@ -830,6 +832,8 @@
 					};
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-soc-safetyservice-fsicom.dtsi b/overlay/tegra234-soc-safetyservice-fsicom.dtsi
index 5b8b22b..a1ab6e5 100644
--- a/overlay/tegra234-soc-safetyservice-fsicom.dtsi
+++ b/overlay/tegra234-soc-safetyservice-fsicom.dtsi
@@ -6,8 +6,10 @@
 
 / {
 	fragment-fsicom@0 {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		target-path = "/";
 		__overlay__ {
+#endif
         	reserved-memory {
         		#address-cells = <2>;
         		#size-cells = <2>;
@@ -147,6 +149,8 @@
         		status = "disabled";
         		channelid_list = <0>;
         	};
+#ifndef REMOVE_FRAGMENT_SYNTAX
         };
     };
+#endif
 };
diff --git a/overlay/tegra234-soc-thermal-shutdown.dtsi b/overlay/tegra234-soc-thermal-shutdown.dtsi
index 7689bfe..ba3d679 100644
--- a/overlay/tegra234-soc-thermal-shutdown.dtsi
+++ b/overlay/tegra234-soc-thermal-shutdown.dtsi
@@ -4,9 +4,11 @@
 #define TEGRA234_THERMAL_SHUTDOWN_TEMP 104500
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-t234-thermal-shutdown@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			thermal-zones {
 				cpu-thermal {
 					trips {
@@ -98,6 +100,8 @@
 					};
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-soc-thermal-slowdown-cluster.dtsi b/overlay/tegra234-soc-thermal-slowdown-cluster.dtsi
index 7becb63..1fe9e43 100644
--- a/overlay/tegra234-soc-thermal-slowdown-cluster.dtsi
+++ b/overlay/tegra234-soc-thermal-slowdown-cluster.dtsi
@@ -6,9 +6,11 @@
 #define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-t234-thermal-slowdown-cluster@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			bus@0 {
 				gpu@17000000 {
 					#cooling-cells = <2>;
@@ -222,6 +224,8 @@
 					};
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-soc-thermal-slowdown-corepair.dtsi b/overlay/tegra234-soc-thermal-slowdown-corepair.dtsi
index d756c15..2a35421 100644
--- a/overlay/tegra234-soc-thermal-slowdown-corepair.dtsi
+++ b/overlay/tegra234-soc-thermal-slowdown-corepair.dtsi
@@ -6,9 +6,11 @@
 #define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000
 
 / {
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-t234-thermal-slowdown-corepair@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			bus@0 {
 				gpu@17000000 {
 					#cooling-cells = <2>;
@@ -258,6 +260,8 @@
 					};
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };
diff --git a/overlay/tegra234-soc-thermal.dtsi b/overlay/tegra234-soc-thermal.dtsi
index 01e65dc..6c3bd83 100644
--- a/overlay/tegra234-soc-thermal.dtsi
+++ b/overlay/tegra234-soc-thermal.dtsi
@@ -4,10 +4,11 @@
 #define TEGRA234_THERMAL_POLLING_DELAY 1000
 
 / {
-
+#ifndef REMOVE_FRAGMENT_SYNTAX
 	fragment-t234-thermal@0 {
 		target-path = "/";
 		__overlay__ {
+#endif
 			thermal-zones {
 				cpu-thermal {
 					polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
@@ -54,6 +55,8 @@
 					polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 				};
 			};
+#ifndef REMOVE_FRAGMENT_SYNTAX
 		};
 	};
+#endif
 };